\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
Channel Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#10 : 2
UART0_Rx_Signal
#11 : 3
UART0_Tx_Signal
#100 : 4
UART1_Rx_Signal
#101 : 5
UART1_Tx_Signal
#110 : 6
UART2_Rx_Signal
#111 : 7
UART2_Tx_Signal
#1000 : 8
UART3_Rx_Signal
#1001 : 9
UART3_Tx_Signal
#1010 : 10
UART4_Rx_Signal
#1011 : 11
UART4_Tx_Signal
#1100 : 12
UART5_Rx_Signal
#1101 : 13
UART5_Tx_Signal
#1110 : 14
I2S0_Rx_Signal
#1111 : 15
I2S0_Tx_Signal
#10000 : 16
SPI0_Rx_Signal
#10001 : 17
SPI0_Tx_Signal
#10010 : 18
SPI1_Rx_Signal
#10011 : 19
SPI1_Tx_Signal
#10100 : 20
SPI2_Rx_Signal
#10101 : 21
SPI2_Tx_Signal
#10110 : 22
I2C0_Signal
#10111 : 23
I2C1_Signal
#11000 : 24
FTM0_Channel0_Signal
#11001 : 25
FTM0_Channel1_Signal
#11010 : 26
FTM0_Channel2_Signal
#11011 : 27
FTM0_Channel3_Signal
#11100 : 28
FTM0_Channel4_Signal
#11101 : 29
FTM0_Channel5_Signal
#11110 : 30
FTM0_Channel6_Signal
#11111 : 31
FTM0_Channel7_Signal
#100000 : 32
FTM1_Channel0_Signal
#100001 : 33
FTM1_Channel1_Signal
#100010 : 34
FTM2_Channel0_Signal
#100011 : 35
FTM2_Channel1_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101010 : 42
CMP0_Signal
#101011 : 43
CMP1_Signal
#101100 : 44
CMP2_Signal
#101101 : 45
DAC0_Signal
#101110 : 46
DAC1_Signal
#101111 : 47
CMT_Signal
#110000 : 48
PDB0_Signal
#110001 : 49
PORTA_Signal
#110010 : 50
PORTB_Signal
#110011 : 51
PORTC_Signal
#110100 : 52
PORTD_Signal
#110101 : 53
PORTE_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#10 : 2
UART0_Rx_Signal
#11 : 3
UART0_Tx_Signal
#100 : 4
UART1_Rx_Signal
#101 : 5
UART1_Tx_Signal
#110 : 6
UART2_Rx_Signal
#111 : 7
UART2_Tx_Signal
#1000 : 8
UART3_Rx_Signal
#1001 : 9
UART3_Tx_Signal
#1010 : 10
UART4_Rx_Signal
#1011 : 11
UART4_Tx_Signal
#1100 : 12
UART5_Rx_Signal
#1101 : 13
UART5_Tx_Signal
#1110 : 14
I2S0_Rx_Signal
#1111 : 15
I2S0_Tx_Signal
#10000 : 16
SPI0_Rx_Signal
#10001 : 17
SPI0_Tx_Signal
#10010 : 18
SPI1_Rx_Signal
#10011 : 19
SPI1_Tx_Signal
#10100 : 20
SPI2_Rx_Signal
#10101 : 21
SPI2_Tx_Signal
#10110 : 22
I2C0_Signal
#10111 : 23
I2C1_Signal
#11000 : 24
FTM0_Channel0_Signal
#11001 : 25
FTM0_Channel1_Signal
#11010 : 26
FTM0_Channel2_Signal
#11011 : 27
FTM0_Channel3_Signal
#11100 : 28
FTM0_Channel4_Signal
#11101 : 29
FTM0_Channel5_Signal
#11110 : 30
FTM0_Channel6_Signal
#11111 : 31
FTM0_Channel7_Signal
#100000 : 32
FTM1_Channel0_Signal
#100001 : 33
FTM1_Channel1_Signal
#100010 : 34
FTM2_Channel0_Signal
#100011 : 35
FTM2_Channel1_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101010 : 42
CMP0_Signal
#101011 : 43
CMP1_Signal
#101100 : 44
CMP2_Signal
#101101 : 45
DAC0_Signal
#101110 : 46
DAC1_Signal
#101111 : 47
CMT_Signal
#110000 : 48
PDB0_Signal
#110001 : 49
PORTA_Signal
#110010 : 50
PORTB_Signal
#110011 : 51
PORTC_Signal
#110100 : 52
PORTD_Signal
#110101 : 53
PORTE_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration Register
address_offset : 0x15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#10 : 2
UART0_Rx_Signal
#11 : 3
UART0_Tx_Signal
#100 : 4
UART1_Rx_Signal
#101 : 5
UART1_Tx_Signal
#110 : 6
UART2_Rx_Signal
#111 : 7
UART2_Tx_Signal
#1000 : 8
UART3_Rx_Signal
#1001 : 9
UART3_Tx_Signal
#1010 : 10
UART4_Rx_Signal
#1011 : 11
UART4_Tx_Signal
#1100 : 12
UART5_Rx_Signal
#1101 : 13
UART5_Tx_Signal
#1110 : 14
I2S0_Rx_Signal
#1111 : 15
I2S0_Tx_Signal
#10000 : 16
SPI0_Rx_Signal
#10001 : 17
SPI0_Tx_Signal
#10010 : 18
SPI1_Rx_Signal
#10011 : 19
SPI1_Tx_Signal
#10100 : 20
SPI2_Rx_Signal
#10101 : 21
SPI2_Tx_Signal
#10110 : 22
I2C0_Signal
#10111 : 23
I2C1_Signal
#11000 : 24
FTM0_Channel0_Signal
#11001 : 25
FTM0_Channel1_Signal
#11010 : 26
FTM0_Channel2_Signal
#11011 : 27
FTM0_Channel3_Signal
#11100 : 28
FTM0_Channel4_Signal
#11101 : 29
FTM0_Channel5_Signal
#11110 : 30
FTM0_Channel6_Signal
#11111 : 31
FTM0_Channel7_Signal
#100000 : 32
FTM1_Channel0_Signal
#100001 : 33
FTM1_Channel1_Signal
#100010 : 34
FTM2_Channel0_Signal
#100011 : 35
FTM2_Channel1_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101010 : 42
CMP0_Signal
#101011 : 43
CMP1_Signal
#101100 : 44
CMP2_Signal
#101101 : 45
DAC0_Signal
#101110 : 46
DAC1_Signal
#101111 : 47
CMT_Signal
#110000 : 48
PDB0_Signal
#110001 : 49
PORTA_Signal
#110010 : 50
PORTB_Signal
#110011 : 51
PORTC_Signal
#110100 : 52
PORTD_Signal
#110101 : 53
PORTE_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration Register
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#10 : 2
UART0_Rx_Signal
#11 : 3
UART0_Tx_Signal
#100 : 4
UART1_Rx_Signal
#101 : 5
UART1_Tx_Signal
#110 : 6
UART2_Rx_Signal
#111 : 7
UART2_Tx_Signal
#1000 : 8
UART3_Rx_Signal
#1001 : 9
UART3_Tx_Signal
#1010 : 10
UART4_Rx_Signal
#1011 : 11
UART4_Tx_Signal
#1100 : 12
UART5_Rx_Signal
#1101 : 13
UART5_Tx_Signal
#1110 : 14
I2S0_Rx_Signal
#1111 : 15
I2S0_Tx_Signal
#10000 : 16
SPI0_Rx_Signal
#10001 : 17
SPI0_Tx_Signal
#10010 : 18
SPI1_Rx_Signal
#10011 : 19
SPI1_Tx_Signal
#10100 : 20
SPI2_Rx_Signal
#10101 : 21
SPI2_Tx_Signal
#10110 : 22
I2C0_Signal
#10111 : 23
I2C1_Signal
#11000 : 24
FTM0_Channel0_Signal
#11001 : 25
FTM0_Channel1_Signal
#11010 : 26
FTM0_Channel2_Signal
#11011 : 27
FTM0_Channel3_Signal
#11100 : 28
FTM0_Channel4_Signal
#11101 : 29
FTM0_Channel5_Signal
#11110 : 30
FTM0_Channel6_Signal
#11111 : 31
FTM0_Channel7_Signal
#100000 : 32
FTM1_Channel0_Signal
#100001 : 33
FTM1_Channel1_Signal
#100010 : 34
FTM2_Channel0_Signal
#100011 : 35
FTM2_Channel1_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101010 : 42
CMP0_Signal
#101011 : 43
CMP1_Signal
#101100 : 44
CMP2_Signal
#101101 : 45
DAC0_Signal
#101110 : 46
DAC1_Signal
#101111 : 47
CMT_Signal
#110000 : 48
PDB0_Signal
#110001 : 49
PORTA_Signal
#110010 : 50
PORTB_Signal
#110011 : 51
PORTC_Signal
#110100 : 52
PORTD_Signal
#110101 : 53
PORTE_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration Register
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#10 : 2
UART0_Rx_Signal
#11 : 3
UART0_Tx_Signal
#100 : 4
UART1_Rx_Signal
#101 : 5
UART1_Tx_Signal
#110 : 6
UART2_Rx_Signal
#111 : 7
UART2_Tx_Signal
#1000 : 8
UART3_Rx_Signal
#1001 : 9
UART3_Tx_Signal
#1010 : 10
UART4_Rx_Signal
#1011 : 11
UART4_Tx_Signal
#1100 : 12
UART5_Rx_Signal
#1101 : 13
UART5_Tx_Signal
#1110 : 14
I2S0_Rx_Signal
#1111 : 15
I2S0_Tx_Signal
#10000 : 16
SPI0_Rx_Signal
#10001 : 17
SPI0_Tx_Signal
#10010 : 18
SPI1_Rx_Signal
#10011 : 19
SPI1_Tx_Signal
#10100 : 20
SPI2_Rx_Signal
#10101 : 21
SPI2_Tx_Signal
#10110 : 22
I2C0_Signal
#10111 : 23
I2C1_Signal
#11000 : 24
FTM0_Channel0_Signal
#11001 : 25
FTM0_Channel1_Signal
#11010 : 26
FTM0_Channel2_Signal
#11011 : 27
FTM0_Channel3_Signal
#11100 : 28
FTM0_Channel4_Signal
#11101 : 29
FTM0_Channel5_Signal
#11110 : 30
FTM0_Channel6_Signal
#11111 : 31
FTM0_Channel7_Signal
#100000 : 32
FTM1_Channel0_Signal
#100001 : 33
FTM1_Channel1_Signal
#100010 : 34
FTM2_Channel0_Signal
#100011 : 35
FTM2_Channel1_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101010 : 42
CMP0_Signal
#101011 : 43
CMP1_Signal
#101100 : 44
CMP2_Signal
#101101 : 45
DAC0_Signal
#101110 : 46
DAC1_Signal
#101111 : 47
CMT_Signal
#110000 : 48
PDB0_Signal
#110001 : 49
PORTA_Signal
#110010 : 50
PORTB_Signal
#110011 : 51
PORTC_Signal
#110100 : 52
PORTD_Signal
#110101 : 53
PORTE_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration Register
address_offset : 0x2D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#10 : 2
UART0_Rx_Signal
#11 : 3
UART0_Tx_Signal
#100 : 4
UART1_Rx_Signal
#101 : 5
UART1_Tx_Signal
#110 : 6
UART2_Rx_Signal
#111 : 7
UART2_Tx_Signal
#1000 : 8
UART3_Rx_Signal
#1001 : 9
UART3_Tx_Signal
#1010 : 10
UART4_Rx_Signal
#1011 : 11
UART4_Tx_Signal
#1100 : 12
UART5_Rx_Signal
#1101 : 13
UART5_Tx_Signal
#1110 : 14
I2S0_Rx_Signal
#1111 : 15
I2S0_Tx_Signal
#10000 : 16
SPI0_Rx_Signal
#10001 : 17
SPI0_Tx_Signal
#10010 : 18
SPI1_Rx_Signal
#10011 : 19
SPI1_Tx_Signal
#10100 : 20
SPI2_Rx_Signal
#10101 : 21
SPI2_Tx_Signal
#10110 : 22
I2C0_Signal
#10111 : 23
I2C1_Signal
#11000 : 24
FTM0_Channel0_Signal
#11001 : 25
FTM0_Channel1_Signal
#11010 : 26
FTM0_Channel2_Signal
#11011 : 27
FTM0_Channel3_Signal
#11100 : 28
FTM0_Channel4_Signal
#11101 : 29
FTM0_Channel5_Signal
#11110 : 30
FTM0_Channel6_Signal
#11111 : 31
FTM0_Channel7_Signal
#100000 : 32
FTM1_Channel0_Signal
#100001 : 33
FTM1_Channel1_Signal
#100010 : 34
FTM2_Channel0_Signal
#100011 : 35
FTM2_Channel1_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101010 : 42
CMP0_Signal
#101011 : 43
CMP1_Signal
#101100 : 44
CMP2_Signal
#101101 : 45
DAC0_Signal
#101110 : 46
DAC1_Signal
#101111 : 47
CMT_Signal
#110000 : 48
PDB0_Signal
#110001 : 49
PORTA_Signal
#110010 : 50
PORTB_Signal
#110011 : 51
PORTC_Signal
#110100 : 52
PORTD_Signal
#110101 : 53
PORTE_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#10 : 2
UART0_Rx_Signal
#11 : 3
UART0_Tx_Signal
#100 : 4
UART1_Rx_Signal
#101 : 5
UART1_Tx_Signal
#110 : 6
UART2_Rx_Signal
#111 : 7
UART2_Tx_Signal
#1000 : 8
UART3_Rx_Signal
#1001 : 9
UART3_Tx_Signal
#1010 : 10
UART4_Rx_Signal
#1011 : 11
UART4_Tx_Signal
#1100 : 12
UART5_Rx_Signal
#1101 : 13
UART5_Tx_Signal
#1110 : 14
I2S0_Rx_Signal
#1111 : 15
I2S0_Tx_Signal
#10000 : 16
SPI0_Rx_Signal
#10001 : 17
SPI0_Tx_Signal
#10010 : 18
SPI1_Rx_Signal
#10011 : 19
SPI1_Tx_Signal
#10100 : 20
SPI2_Rx_Signal
#10101 : 21
SPI2_Tx_Signal
#10110 : 22
I2C0_Signal
#10111 : 23
I2C1_Signal
#11000 : 24
FTM0_Channel0_Signal
#11001 : 25
FTM0_Channel1_Signal
#11010 : 26
FTM0_Channel2_Signal
#11011 : 27
FTM0_Channel3_Signal
#11100 : 28
FTM0_Channel4_Signal
#11101 : 29
FTM0_Channel5_Signal
#11110 : 30
FTM0_Channel6_Signal
#11111 : 31
FTM0_Channel7_Signal
#100000 : 32
FTM1_Channel0_Signal
#100001 : 33
FTM1_Channel1_Signal
#100010 : 34
FTM2_Channel0_Signal
#100011 : 35
FTM2_Channel1_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101010 : 42
CMP0_Signal
#101011 : 43
CMP1_Signal
#101100 : 44
CMP2_Signal
#101101 : 45
DAC0_Signal
#101110 : 46
DAC1_Signal
#101111 : 47
CMT_Signal
#110000 : 48
PDB0_Signal
#110001 : 49
PORTA_Signal
#110010 : 50
PORTB_Signal
#110011 : 51
PORTC_Signal
#110100 : 52
PORTD_Signal
#110101 : 53
PORTE_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration Register
address_offset : 0x37 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#10 : 2
UART0_Rx_Signal
#11 : 3
UART0_Tx_Signal
#100 : 4
UART1_Rx_Signal
#101 : 5
UART1_Tx_Signal
#110 : 6
UART2_Rx_Signal
#111 : 7
UART2_Tx_Signal
#1000 : 8
UART3_Rx_Signal
#1001 : 9
UART3_Tx_Signal
#1010 : 10
UART4_Rx_Signal
#1011 : 11
UART4_Tx_Signal
#1100 : 12
UART5_Rx_Signal
#1101 : 13
UART5_Tx_Signal
#1110 : 14
I2S0_Rx_Signal
#1111 : 15
I2S0_Tx_Signal
#10000 : 16
SPI0_Rx_Signal
#10001 : 17
SPI0_Tx_Signal
#10010 : 18
SPI1_Rx_Signal
#10011 : 19
SPI1_Tx_Signal
#10100 : 20
SPI2_Rx_Signal
#10101 : 21
SPI2_Tx_Signal
#10110 : 22
I2C0_Signal
#10111 : 23
I2C1_Signal
#11000 : 24
FTM0_Channel0_Signal
#11001 : 25
FTM0_Channel1_Signal
#11010 : 26
FTM0_Channel2_Signal
#11011 : 27
FTM0_Channel3_Signal
#11100 : 28
FTM0_Channel4_Signal
#11101 : 29
FTM0_Channel5_Signal
#11110 : 30
FTM0_Channel6_Signal
#11111 : 31
FTM0_Channel7_Signal
#100000 : 32
FTM1_Channel0_Signal
#100001 : 33
FTM1_Channel1_Signal
#100010 : 34
FTM2_Channel0_Signal
#100011 : 35
FTM2_Channel1_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101010 : 42
CMP0_Signal
#101011 : 43
CMP1_Signal
#101100 : 44
CMP2_Signal
#101101 : 45
DAC0_Signal
#101110 : 46
DAC1_Signal
#101111 : 47
CMT_Signal
#110000 : 48
PDB0_Signal
#110001 : 49
PORTA_Signal
#110010 : 50
PORTB_Signal
#110011 : 51
PORTC_Signal
#110100 : 52
PORTD_Signal
#110101 : 53
PORTE_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration Register
address_offset : 0x42 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#10 : 2
UART0_Rx_Signal
#11 : 3
UART0_Tx_Signal
#100 : 4
UART1_Rx_Signal
#101 : 5
UART1_Tx_Signal
#110 : 6
UART2_Rx_Signal
#111 : 7
UART2_Tx_Signal
#1000 : 8
UART3_Rx_Signal
#1001 : 9
UART3_Tx_Signal
#1010 : 10
UART4_Rx_Signal
#1011 : 11
UART4_Tx_Signal
#1100 : 12
UART5_Rx_Signal
#1101 : 13
UART5_Tx_Signal
#1110 : 14
I2S0_Rx_Signal
#1111 : 15
I2S0_Tx_Signal
#10000 : 16
SPI0_Rx_Signal
#10001 : 17
SPI0_Tx_Signal
#10010 : 18
SPI1_Rx_Signal
#10011 : 19
SPI1_Tx_Signal
#10100 : 20
SPI2_Rx_Signal
#10101 : 21
SPI2_Tx_Signal
#10110 : 22
I2C0_Signal
#10111 : 23
I2C1_Signal
#11000 : 24
FTM0_Channel0_Signal
#11001 : 25
FTM0_Channel1_Signal
#11010 : 26
FTM0_Channel2_Signal
#11011 : 27
FTM0_Channel3_Signal
#11100 : 28
FTM0_Channel4_Signal
#11101 : 29
FTM0_Channel5_Signal
#11110 : 30
FTM0_Channel6_Signal
#11111 : 31
FTM0_Channel7_Signal
#100000 : 32
FTM1_Channel0_Signal
#100001 : 33
FTM1_Channel1_Signal
#100010 : 34
FTM2_Channel0_Signal
#100011 : 35
FTM2_Channel1_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101010 : 42
CMP0_Signal
#101011 : 43
CMP1_Signal
#101100 : 44
CMP2_Signal
#101101 : 45
DAC0_Signal
#101110 : 46
DAC1_Signal
#101111 : 47
CMT_Signal
#110000 : 48
PDB0_Signal
#110001 : 49
PORTA_Signal
#110010 : 50
PORTB_Signal
#110011 : 51
PORTC_Signal
#110100 : 52
PORTD_Signal
#110101 : 53
PORTE_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration Register
address_offset : 0x4E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#10 : 2
UART0_Rx_Signal
#11 : 3
UART0_Tx_Signal
#100 : 4
UART1_Rx_Signal
#101 : 5
UART1_Tx_Signal
#110 : 6
UART2_Rx_Signal
#111 : 7
UART2_Tx_Signal
#1000 : 8
UART3_Rx_Signal
#1001 : 9
UART3_Tx_Signal
#1010 : 10
UART4_Rx_Signal
#1011 : 11
UART4_Tx_Signal
#1100 : 12
UART5_Rx_Signal
#1101 : 13
UART5_Tx_Signal
#1110 : 14
I2S0_Rx_Signal
#1111 : 15
I2S0_Tx_Signal
#10000 : 16
SPI0_Rx_Signal
#10001 : 17
SPI0_Tx_Signal
#10010 : 18
SPI1_Rx_Signal
#10011 : 19
SPI1_Tx_Signal
#10100 : 20
SPI2_Rx_Signal
#10101 : 21
SPI2_Tx_Signal
#10110 : 22
I2C0_Signal
#10111 : 23
I2C1_Signal
#11000 : 24
FTM0_Channel0_Signal
#11001 : 25
FTM0_Channel1_Signal
#11010 : 26
FTM0_Channel2_Signal
#11011 : 27
FTM0_Channel3_Signal
#11100 : 28
FTM0_Channel4_Signal
#11101 : 29
FTM0_Channel5_Signal
#11110 : 30
FTM0_Channel6_Signal
#11111 : 31
FTM0_Channel7_Signal
#100000 : 32
FTM1_Channel0_Signal
#100001 : 33
FTM1_Channel1_Signal
#100010 : 34
FTM2_Channel0_Signal
#100011 : 35
FTM2_Channel1_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101010 : 42
CMP0_Signal
#101011 : 43
CMP1_Signal
#101100 : 44
CMP2_Signal
#101101 : 45
DAC0_Signal
#101110 : 46
DAC1_Signal
#101111 : 47
CMT_Signal
#110000 : 48
PDB0_Signal
#110001 : 49
PORTA_Signal
#110010 : 50
PORTB_Signal
#110011 : 51
PORTC_Signal
#110100 : 52
PORTD_Signal
#110101 : 53
PORTE_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration Register
address_offset : 0x5B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#10 : 2
UART0_Rx_Signal
#11 : 3
UART0_Tx_Signal
#100 : 4
UART1_Rx_Signal
#101 : 5
UART1_Tx_Signal
#110 : 6
UART2_Rx_Signal
#111 : 7
UART2_Tx_Signal
#1000 : 8
UART3_Rx_Signal
#1001 : 9
UART3_Tx_Signal
#1010 : 10
UART4_Rx_Signal
#1011 : 11
UART4_Tx_Signal
#1100 : 12
UART5_Rx_Signal
#1101 : 13
UART5_Tx_Signal
#1110 : 14
I2S0_Rx_Signal
#1111 : 15
I2S0_Tx_Signal
#10000 : 16
SPI0_Rx_Signal
#10001 : 17
SPI0_Tx_Signal
#10010 : 18
SPI1_Rx_Signal
#10011 : 19
SPI1_Tx_Signal
#10100 : 20
SPI2_Rx_Signal
#10101 : 21
SPI2_Tx_Signal
#10110 : 22
I2C0_Signal
#10111 : 23
I2C1_Signal
#11000 : 24
FTM0_Channel0_Signal
#11001 : 25
FTM0_Channel1_Signal
#11010 : 26
FTM0_Channel2_Signal
#11011 : 27
FTM0_Channel3_Signal
#11100 : 28
FTM0_Channel4_Signal
#11101 : 29
FTM0_Channel5_Signal
#11110 : 30
FTM0_Channel6_Signal
#11111 : 31
FTM0_Channel7_Signal
#100000 : 32
FTM1_Channel0_Signal
#100001 : 33
FTM1_Channel1_Signal
#100010 : 34
FTM2_Channel0_Signal
#100011 : 35
FTM2_Channel1_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101010 : 42
CMP0_Signal
#101011 : 43
CMP1_Signal
#101100 : 44
CMP2_Signal
#101101 : 45
DAC0_Signal
#101110 : 46
DAC1_Signal
#101111 : 47
CMT_Signal
#110000 : 48
PDB0_Signal
#110001 : 49
PORTA_Signal
#110010 : 50
PORTB_Signal
#110011 : 51
PORTC_Signal
#110100 : 52
PORTD_Signal
#110101 : 53
PORTE_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#10 : 2
UART0_Rx_Signal
#11 : 3
UART0_Tx_Signal
#100 : 4
UART1_Rx_Signal
#101 : 5
UART1_Tx_Signal
#110 : 6
UART2_Rx_Signal
#111 : 7
UART2_Tx_Signal
#1000 : 8
UART3_Rx_Signal
#1001 : 9
UART3_Tx_Signal
#1010 : 10
UART4_Rx_Signal
#1011 : 11
UART4_Tx_Signal
#1100 : 12
UART5_Rx_Signal
#1101 : 13
UART5_Tx_Signal
#1110 : 14
I2S0_Rx_Signal
#1111 : 15
I2S0_Tx_Signal
#10000 : 16
SPI0_Rx_Signal
#10001 : 17
SPI0_Tx_Signal
#10010 : 18
SPI1_Rx_Signal
#10011 : 19
SPI1_Tx_Signal
#10100 : 20
SPI2_Rx_Signal
#10101 : 21
SPI2_Tx_Signal
#10110 : 22
I2C0_Signal
#10111 : 23
I2C1_Signal
#11000 : 24
FTM0_Channel0_Signal
#11001 : 25
FTM0_Channel1_Signal
#11010 : 26
FTM0_Channel2_Signal
#11011 : 27
FTM0_Channel3_Signal
#11100 : 28
FTM0_Channel4_Signal
#11101 : 29
FTM0_Channel5_Signal
#11110 : 30
FTM0_Channel6_Signal
#11111 : 31
FTM0_Channel7_Signal
#100000 : 32
FTM1_Channel0_Signal
#100001 : 33
FTM1_Channel1_Signal
#100010 : 34
FTM2_Channel0_Signal
#100011 : 35
FTM2_Channel1_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101010 : 42
CMP0_Signal
#101011 : 43
CMP1_Signal
#101100 : 44
CMP2_Signal
#101101 : 45
DAC0_Signal
#101110 : 46
DAC1_Signal
#101111 : 47
CMT_Signal
#110000 : 48
PDB0_Signal
#110001 : 49
PORTA_Signal
#110010 : 50
PORTB_Signal
#110011 : 51
PORTC_Signal
#110100 : 52
PORTD_Signal
#110101 : 53
PORTE_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration Register
address_offset : 0x69 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#10 : 2
UART0_Rx_Signal
#11 : 3
UART0_Tx_Signal
#100 : 4
UART1_Rx_Signal
#101 : 5
UART1_Tx_Signal
#110 : 6
UART2_Rx_Signal
#111 : 7
UART2_Tx_Signal
#1000 : 8
UART3_Rx_Signal
#1001 : 9
UART3_Tx_Signal
#1010 : 10
UART4_Rx_Signal
#1011 : 11
UART4_Tx_Signal
#1100 : 12
UART5_Rx_Signal
#1101 : 13
UART5_Tx_Signal
#1110 : 14
I2S0_Rx_Signal
#1111 : 15
I2S0_Tx_Signal
#10000 : 16
SPI0_Rx_Signal
#10001 : 17
SPI0_Tx_Signal
#10010 : 18
SPI1_Rx_Signal
#10011 : 19
SPI1_Tx_Signal
#10100 : 20
SPI2_Rx_Signal
#10101 : 21
SPI2_Tx_Signal
#10110 : 22
I2C0_Signal
#10111 : 23
I2C1_Signal
#11000 : 24
FTM0_Channel0_Signal
#11001 : 25
FTM0_Channel1_Signal
#11010 : 26
FTM0_Channel2_Signal
#11011 : 27
FTM0_Channel3_Signal
#11100 : 28
FTM0_Channel4_Signal
#11101 : 29
FTM0_Channel5_Signal
#11110 : 30
FTM0_Channel6_Signal
#11111 : 31
FTM0_Channel7_Signal
#100000 : 32
FTM1_Channel0_Signal
#100001 : 33
FTM1_Channel1_Signal
#100010 : 34
FTM2_Channel0_Signal
#100011 : 35
FTM2_Channel1_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101010 : 42
CMP0_Signal
#101011 : 43
CMP1_Signal
#101100 : 44
CMP2_Signal
#101101 : 45
DAC0_Signal
#101110 : 46
DAC1_Signal
#101111 : 47
CMT_Signal
#110000 : 48
PDB0_Signal
#110001 : 49
PORTA_Signal
#110010 : 50
PORTB_Signal
#110011 : 51
PORTC_Signal
#110100 : 52
PORTD_Signal
#110101 : 53
PORTE_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration Register
address_offset : 0x78 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#10 : 2
UART0_Rx_Signal
#11 : 3
UART0_Tx_Signal
#100 : 4
UART1_Rx_Signal
#101 : 5
UART1_Tx_Signal
#110 : 6
UART2_Rx_Signal
#111 : 7
UART2_Tx_Signal
#1000 : 8
UART3_Rx_Signal
#1001 : 9
UART3_Tx_Signal
#1010 : 10
UART4_Rx_Signal
#1011 : 11
UART4_Tx_Signal
#1100 : 12
UART5_Rx_Signal
#1101 : 13
UART5_Tx_Signal
#1110 : 14
I2S0_Rx_Signal
#1111 : 15
I2S0_Tx_Signal
#10000 : 16
SPI0_Rx_Signal
#10001 : 17
SPI0_Tx_Signal
#10010 : 18
SPI1_Rx_Signal
#10011 : 19
SPI1_Tx_Signal
#10100 : 20
SPI2_Rx_Signal
#10101 : 21
SPI2_Tx_Signal
#10110 : 22
I2C0_Signal
#10111 : 23
I2C1_Signal
#11000 : 24
FTM0_Channel0_Signal
#11001 : 25
FTM0_Channel1_Signal
#11010 : 26
FTM0_Channel2_Signal
#11011 : 27
FTM0_Channel3_Signal
#11100 : 28
FTM0_Channel4_Signal
#11101 : 29
FTM0_Channel5_Signal
#11110 : 30
FTM0_Channel6_Signal
#11111 : 31
FTM0_Channel7_Signal
#100000 : 32
FTM1_Channel0_Signal
#100001 : 33
FTM1_Channel1_Signal
#100010 : 34
FTM2_Channel0_Signal
#100011 : 35
FTM2_Channel1_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101010 : 42
CMP0_Signal
#101011 : 43
CMP1_Signal
#101100 : 44
CMP2_Signal
#101101 : 45
DAC0_Signal
#101110 : 46
DAC1_Signal
#101111 : 47
CMT_Signal
#110000 : 48
PDB0_Signal
#110001 : 49
PORTA_Signal
#110010 : 50
PORTB_Signal
#110011 : 51
PORTC_Signal
#110100 : 52
PORTD_Signal
#110101 : 53
PORTE_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration Register
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#10 : 2
UART0_Rx_Signal
#11 : 3
UART0_Tx_Signal
#100 : 4
UART1_Rx_Signal
#101 : 5
UART1_Tx_Signal
#110 : 6
UART2_Rx_Signal
#111 : 7
UART2_Tx_Signal
#1000 : 8
UART3_Rx_Signal
#1001 : 9
UART3_Tx_Signal
#1010 : 10
UART4_Rx_Signal
#1011 : 11
UART4_Tx_Signal
#1100 : 12
UART5_Rx_Signal
#1101 : 13
UART5_Tx_Signal
#1110 : 14
I2S0_Rx_Signal
#1111 : 15
I2S0_Tx_Signal
#10000 : 16
SPI0_Rx_Signal
#10001 : 17
SPI0_Tx_Signal
#10010 : 18
SPI1_Rx_Signal
#10011 : 19
SPI1_Tx_Signal
#10100 : 20
SPI2_Rx_Signal
#10101 : 21
SPI2_Tx_Signal
#10110 : 22
I2C0_Signal
#10111 : 23
I2C1_Signal
#11000 : 24
FTM0_Channel0_Signal
#11001 : 25
FTM0_Channel1_Signal
#11010 : 26
FTM0_Channel2_Signal
#11011 : 27
FTM0_Channel3_Signal
#11100 : 28
FTM0_Channel4_Signal
#11101 : 29
FTM0_Channel5_Signal
#11110 : 30
FTM0_Channel6_Signal
#11111 : 31
FTM0_Channel7_Signal
#100000 : 32
FTM1_Channel0_Signal
#100001 : 33
FTM1_Channel1_Signal
#100010 : 34
FTM2_Channel0_Signal
#100011 : 35
FTM2_Channel1_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101010 : 42
CMP0_Signal
#101011 : 43
CMP1_Signal
#101100 : 44
CMP2_Signal
#101101 : 45
DAC0_Signal
#101110 : 46
DAC1_Signal
#101111 : 47
CMT_Signal
#110000 : 48
PDB0_Signal
#110001 : 49
PORTA_Signal
#110010 : 50
PORTB_Signal
#110011 : 51
PORTC_Signal
#110100 : 52
PORTD_Signal
#110101 : 53
PORTE_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration Register
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#10 : 2
UART0_Rx_Signal
#11 : 3
UART0_Tx_Signal
#100 : 4
UART1_Rx_Signal
#101 : 5
UART1_Tx_Signal
#110 : 6
UART2_Rx_Signal
#111 : 7
UART2_Tx_Signal
#1000 : 8
UART3_Rx_Signal
#1001 : 9
UART3_Tx_Signal
#1010 : 10
UART4_Rx_Signal
#1011 : 11
UART4_Tx_Signal
#1100 : 12
UART5_Rx_Signal
#1101 : 13
UART5_Tx_Signal
#1110 : 14
I2S0_Rx_Signal
#1111 : 15
I2S0_Tx_Signal
#10000 : 16
SPI0_Rx_Signal
#10001 : 17
SPI0_Tx_Signal
#10010 : 18
SPI1_Rx_Signal
#10011 : 19
SPI1_Tx_Signal
#10100 : 20
SPI2_Rx_Signal
#10101 : 21
SPI2_Tx_Signal
#10110 : 22
I2C0_Signal
#10111 : 23
I2C1_Signal
#11000 : 24
FTM0_Channel0_Signal
#11001 : 25
FTM0_Channel1_Signal
#11010 : 26
FTM0_Channel2_Signal
#11011 : 27
FTM0_Channel3_Signal
#11100 : 28
FTM0_Channel4_Signal
#11101 : 29
FTM0_Channel5_Signal
#11110 : 30
FTM0_Channel6_Signal
#11111 : 31
FTM0_Channel7_Signal
#100000 : 32
FTM1_Channel0_Signal
#100001 : 33
FTM1_Channel1_Signal
#100010 : 34
FTM2_Channel0_Signal
#100011 : 35
FTM2_Channel1_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101010 : 42
CMP0_Signal
#101011 : 43
CMP1_Signal
#101100 : 44
CMP2_Signal
#101101 : 45
DAC0_Signal
#101110 : 46
DAC1_Signal
#101111 : 47
CMT_Signal
#110000 : 48
PDB0_Signal
#110001 : 49
PORTA_Signal
#110010 : 50
PORTB_Signal
#110011 : 51
PORTC_Signal
#110100 : 52
PORTD_Signal
#110101 : 53
PORTE_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
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