Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x88 byte (0x0)
mem_usage : registers
protection : not protected
LCDC screen start address register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSA : Screen start address of LCD panel
bits : 2 - 31 (30 bit)
access : read-write
LCDC cursor width, height, and blink register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BD : Blink divisor
bits : 0 - 7 (8 bit)
access : read-write
CH : Cursor height
bits : 16 - 20 (5 bit)
access : read-write
CW : Cursor width
bits : 24 - 28 (5 bit)
access : read-write
BK_EN : Blink enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Blink is disabled.
#1 : 1
Blink is enabled.
End of enumeration elements list.
LCDC color cursor mapping register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CUR_COL_B : Cursor blue field
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 000000
No blue
#111111 : 111111
Full blue
End of enumeration elements list.
CUR_COL_G : Cursor green field
bits : 6 - 11 (6 bit)
access : read-write
Enumeration:
#0 : 000000
No green
#111111 : 111111
Full green
End of enumeration elements list.
CUR_COL_R : Cursor red field
bits : 12 - 17 (6 bit)
access : read-write
Enumeration:
#0 : 000000
No red
#111111 : 111111
Full red
End of enumeration elements list.
LCDC panel configuration register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCD : Pixel clock divider
bits : 0 - 5 (6 bit)
access : read-write
SCLKSEL : LSCLK select
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable OE and LSCLK in TFT mode when no data output.
#1 : 1
Always enable LSCLK in TFT mode even if there is no data output.
End of enumeration elements list.
ACD : Alternate crystal direction
bits : 8 - 14 (7 bit)
access : read-write
ACDSEL : ACD clock source select
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use FLM as a clock source for ACD count.
#1 : 1
Use LP/HSYNC as a clock source for ACD count.
End of enumeration elements list.
REV_VS : Reverse vertical scan
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Vertical scan in normal direction.
#1 : 1
Vertical scan in reverse direction.
End of enumeration elements list.
SWAP_SEL : Swap select
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
24 bpp, 18 bpp, 16 bpp, 12 bpp mode.
#1 : 1
8 bpp, 4 bpp, 2 bpp, and 1 bpp mode.
End of enumeration elements list.
END_SEL : Endian select
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Little Endian
#1 : 1
Big Endian
End of enumeration elements list.
SCLKIDLE : LSCLK idle enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable LSCLK
#1 : 1
Enable LSCLK
End of enumeration elements list.
OEPOL : Output enable polarity
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Active high
#1 : 1
Active low
End of enumeration elements list.
CLKPOL : LCD shift clock polarity
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Active on negative edge of LSCLK. In TFT mode, active on positive edge of LSCLK.
#1 : 1
Active on positive edge of LSCLK. In TFT mode, active on negative edge of LSCLK.
End of enumeration elements list.
LPPOL : Line pulse polarity
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Active high
#1 : 1
Active low
End of enumeration elements list.
FLMPOL : First line marker polarity
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Active high
#1 : 1
Active low
End of enumeration elements list.
PIXPOL : Pixel polarity
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Active high
#1 : 1
Active low
End of enumeration elements list.
BPIX : Bits per pixel
bits : 25 - 27 (3 bit)
access : read-write
Enumeration:
#000 : 000
1 bpp, FRC bypassed
#001 : 001
2 bpp
#010 : 010
4 bpp
#011 : 011
8 bpp
#100 : 100
12 bpp (16-bits of memory used)
#101 : 101
16 bpp
#110 : 110
18 bpp (32-bits of memory used)
#111 : 111
24 bpp (32-bits of memory used)
End of enumeration elements list.
PBSIZ : Panel bus width
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 000
1-bit
#01 : 001
2-bit
#10 : 010
4-bit
#11 : 011
8-bit
End of enumeration elements list.
COLOR : Interfaces to color display
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
LCD panel is a Monochrome display.
#1 : 1
LCD panel is a Color display.
End of enumeration elements list.
TFT : Interfaces to TFT display
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
LCD panel is a passive display.
#1 : 1
LCD panel is an active display: "digital CRT" signal format, FRC is bypassed.
End of enumeration elements list.
LCDC horizontal configuration register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H_WAIT_2 : Wait between HSYNC and start of next line
bits : 0 - 7 (8 bit)
access : read-write
H_WAIT_1 : Wait between OE and HSYNC
bits : 8 - 15 (8 bit)
access : read-write
H_WIDTH : Horizontal sync pulse width
bits : 26 - 31 (6 bit)
access : read-write
LCDC vertical configuration register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V_WAIT_2 : Wait between frames 2
bits : 0 - 7 (8 bit)
access : read-write
V_WAIT_1 : Wait between frames 1
bits : 8 - 15 (8 bit)
access : read-write
V_WIDTH : Vertical sync pulse width
bits : 26 - 31 (6 bit)
access : read-write
LCDC panning offset register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POS : Panning offset
bits : 0 - 4 (5 bit)
access : read-write
LCDC PWM contrast control register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PW : Pulse-width
bits : 0 - 7 (8 bit)
access : read-write
CC_EN : Contrast control enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Contrast control is off.
#1 : 1
Contrast control is on.
End of enumeration elements list.
SCR : Source select
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 00
Line pulse
#01 : 01
Pixel clock
#10 : 10
LCD clock
End of enumeration elements list.
LDMSK : LD mask
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
LD [23:0] is normal.
#1 : 1
LD [23:0] always equals 0.
End of enumeration elements list.
LCDC DMA control register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TM : DMA trigger mark
bits : 0 - 6 (7 bit)
access : read-write
HM : DMA high mark
bits : 16 - 22 (7 bit)
access : read-write
BURST : Burst length
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Burst length is dynamic.
#1 : 1
Burst length is fixed.
End of enumeration elements list.
LCDC refresh mode control register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SELF_REF : Self-refresh
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable self-refresh
#1 : 1
Enable self-refresh
End of enumeration elements list.
LCDC interrupt configuration register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTCON : Interrupt condition
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt flag is set when the end of frame (EOF) is reached.
#1 : 1
Interrupt flag is set when the beginning of frame (BOF) is reached.
End of enumeration elements list.
INTSYN : Interrupt source
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt flag is set on loading the last/first data of frame from memory.
#1 : 1
Interrupt flag is set on output of the last/first data of frame to LCD panel.
End of enumeration elements list.
GW_INT_CON : Graphic window interrupt condition
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt flag is set when end of graphic window is reached.
#1 : 1
Interrupt flag is set when beginning of graphic window is reached.
End of enumeration elements list.
LCDC interrupt enable register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOF_EN : Beginning of frame interrupt enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask interrupt.
#1 : 1
Enable interrupt.
End of enumeration elements list.
EOF_EN : End of frame interrupt enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask interrupt.
#1 : 1
Enable interrupt.
End of enumeration elements list.
UDR_ERR_EN : Under run error interrupt enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask interrupt.
#1 : 1
Enable interrupt.
End of enumeration elements list.
GW_BOF_EN : Graphic window beginning of frame interrupt enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask interrupt.
#1 : 1
Enable interrupt.
End of enumeration elements list.
GW_EOF_EN : Graphic window end of frame interrupt enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask interrupt.
#1 : 1
Enable interrupt.
End of enumeration elements list.
GW_UDR_ERR_EN : Graphic window under run error interrupt enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask interrupt.
#1 : 1
Enable interrupt.
End of enumeration elements list.
LCDC size register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
YMAX : Screen height
bits : 0 - 9 (10 bit)
access : read-write
XMAX : Screen width divided by 16
bits : 20 - 26 (7 bit)
access : read-write
LCDC interrupt status register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BOF : Beginning of frame
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt has not occurred.
#1 : 1
Interrupt has occurred.
End of enumeration elements list.
EOF : End of frame
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt has not occurred.
#1 : 1
Interrupt has occurred.
End of enumeration elements list.
UDR_ERR : Under run error
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt has not occurred.
#1 : 1
Interrupt has occurred.
End of enumeration elements list.
GW_BOF : Graphic window beginning of frame
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt has not occurred.
#1 : 1
Interrupt has occurred.
End of enumeration elements list.
GW_EOF : Graphic window end of frame
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt has not occurred.
#1 : 1
Interrupt has occurred.
End of enumeration elements list.
GW_UDR_ERR : Graphic window under run error
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Graphic window under run has not occurred.
#1 : 1
Graphic window under run has occurred.
End of enumeration elements list.
LCDC graphic window start address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GWSA : Graphic window start address on LCD screen
bits : 2 - 31 (30 bit)
access : read-write
LCDC graphic window size register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GWH : Graphic window height
bits : 0 - 9 (10 bit)
access : read-write
GWW : Graphic window width divided by 16
bits : 20 - 26 (7 bit)
access : read-write
LCDC graphic window virtual page width register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GWVPW : Graphic window virtual page width
bits : 0 - 10 (11 bit)
access : read-write
LCDC graphic window panning offset register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GWPO : Graphic window panning offset
bits : 0 - 4 (5 bit)
access : read-write
LCDC graphic window position register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GWYP : Graphic window Y position
bits : 0 - 9 (10 bit)
access : read-write
GWXP : Graphic window X position
bits : 16 - 25 (10 bit)
access : read-write
LCDC graphic window control register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GWCKB : Graphic window color keying blue component
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 000000
No blue
#111111 : 111111
Full blue
End of enumeration elements list.
GWCKG : Graphic window color keying green component
bits : 6 - 11 (6 bit)
access : read-write
Enumeration:
#0 : 000000
No green
#111111 : 111111
Full green
End of enumeration elements list.
GWCKR : Graphic window color keying red component
bits : 12 - 17 (6 bit)
access : read-write
Enumeration:
#0 : 000000
No red
#111111 : 111111
Full red
End of enumeration elements list.
GW_RVS : Graphic window reverse vertical scan
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Vertical scan in normal direction.
#1 : 1
Vertical scan in reverse direction.
End of enumeration elements list.
GWE : Graphic window enable
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable graphic window on screen.
#1 : 1
Enable graphic window on screen.
End of enumeration elements list.
GWCKE : Graphic window color keying enable
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable color keying of graphic window.
#1 : 1
Enable color keying of graphic window.
End of enumeration elements list.
GWAV : Graphic window alpha value
bits : 24 - 31 (8 bit)
access : read-write
Enumeration:
#0 : 0
Graphic window totally transparent (not displayed on LCD screen).
#1 : 1
Graphic window totally opaque (completely visible on LCD screen).
End of enumeration elements list.
LCDC graphic window DMA control register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GWTM : Graphic window DMA low mark
bits : 0 - 6 (7 bit)
access : read-write
GWHM : Graphic window DMA high mark
bits : 16 - 22 (7 bit)
access : read-write
GWBT : Graphic window DMA burst type
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Burst length is dynamic.
#1 : 1
Burst length is fixed.
End of enumeration elements list.
LCDC virtual page width register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VPW : Virtual page width
bits : 0 - 10 (11 bit)
access : read-write
LCDC AUS mode control register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AGWCKB : AUS graphic window color keying blue component
bits : 0 - 7 (8 bit)
access : read-write
AGWCKG : AUS graphic window color keying green component
bits : 8 - 15 (8 bit)
access : read-write
AGWCKR : AUS graphic window color keying red component
bits : 16 - 23 (8 bit)
access : read-write
AUS_Mode : AUS mode control
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal mode
#1 : 1
AUS mode
End of enumeration elements list.
LCDC AUS mode cursor control register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACUR_COL_B : AUS cursor red field
bits : 0 - 7 (8 bit)
access : read-write
ACUR_COL_G : AUS cursor green field
bits : 8 - 15 (8 bit)
access : read-write
ACUR_COL_R : AUS cursor red field
bits : 16 - 23 (8 bit)
access : read-write
LCDC cursor position register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CYP : Cursor Y position
bits : 0 - 9 (10 bit)
access : read-write
CXP : Cursor X position
bits : 16 - 25 (10 bit)
access : read-write
OP : Arithmetic operation control
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable arithmetic operation
#1 : 1
Enable arithmetic operation
End of enumeration elements list.
CC : Cursor control
bits : 30 - 31 (2 bit)
access : read-write
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