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WDOG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected

Registers

STCTRLH

TMROUTH

TMROUTL

RSTCNT

PRESC

STCTRLL

TOVALH

TOVALL

WINH

WINL

REFRESH

UNLOCK


STCTRLH

Watchdog Status and Control Register High
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STCTRLH STCTRLH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDOGEN CLKSRC IRQRSTEN WINEN ALLOWUPDATE DBGEN STOPEN WAITEN TESTWDOG TESTSEL BYTESEL DISTESTWDOG

WDOGEN : Enables or disables the WDOG's operation
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

WDOG is disabled.

#1 : 1

WDOG is enabled.

End of enumeration elements list.

CLKSRC : Selects clock source for the WDOG timer and other internal timing operations.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

WDOG clock sourced from LPO .

#1 : 1

WDOG clock sourced from alternate clock source.

End of enumeration elements list.

IRQRSTEN : Used to enable the debug breadcrumbs feature
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

WDOG time-out generates reset only.

#1 : 1

WDOG time-out initially generates an interrupt. After WCT, it generates a reset.

End of enumeration elements list.

WINEN : Enables Windowing mode.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Windowing mode is disabled.

#1 : 1

Windowing mode is enabled.

End of enumeration elements list.

ALLOWUPDATE : Enables updates to watchdog write-once registers, after the reset-triggered initial configuration window (WCT) closes, through unlock sequence
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No further updates allowed to WDOG write-once registers.

#1 : 1

WDOG write-once registers can be unlocked for updating.

End of enumeration elements list.

DBGEN : Enables or disables WDOG in Debug mode.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

WDOG is disabled in CPU Debug mode.

#1 : 1

WDOG is enabled in CPU Debug mode.

End of enumeration elements list.

STOPEN : Enables or disables WDOG in Stop mode.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

WDOG is disabled in CPU Stop mode.

#1 : 1

WDOG is enabled in CPU Stop mode.

End of enumeration elements list.

WAITEN : Enables or disables WDOG in Wait mode.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

WDOG is disabled in CPU Wait mode.

#1 : 1

WDOG is enabled in CPU Wait mode.

End of enumeration elements list.

TESTWDOG : Puts the watchdog in the functional test mode
bits : 10 - 10 (1 bit)
access : read-write

TESTSEL : Effective only if TESTWDOG is set. Selects the test to be run on the watchdog timer.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test.

#1 : 1

Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing.

End of enumeration elements list.

BYTESEL : This 2-bit field selects the byte to be tested when the watchdog is in the byte test mode.
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 00

Byte 0 selected

#01 : 01

Byte 1 selected

#10 : 10

Byte 2 selected

#11 : 11

Byte 3 selected

End of enumeration elements list.

DISTESTWDOG : Allows the WDOG's functional test mode to be disabled permanently
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

WDOG functional test mode is not disabled.

#1 : 1

WDOG functional test mode is disabled permanently until reset.

End of enumeration elements list.


TMROUTH

Watchdog Timer Output Register High
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMROUTH TMROUTH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMEROUTHIGH

TIMEROUTHIGH : Shows the value of the upper 16 bits of the watchdog timer.
bits : 0 - 15 (16 bit)
access : read-write


TMROUTL

Watchdog Timer Output Register Low
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMROUTL TMROUTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMEROUTLOW

TIMEROUTLOW : Shows the value of the lower 16 bits of the watchdog timer.
bits : 0 - 15 (16 bit)
access : read-write


RSTCNT

Watchdog Reset Count Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTCNT RSTCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTCNT

RSTCNT : Counts the number of times the watchdog resets the system
bits : 0 - 15 (16 bit)
access : read-write


PRESC

Watchdog Prescaler Register
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRESC PRESC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESCVAL

PRESCVAL : 3-bit prescaler for the watchdog clock source
bits : 8 - 10 (3 bit)
access : read-write


STCTRLL

Watchdog Status and Control Register Low
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STCTRLL STCTRLL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTFLG

INTFLG : Interrupt flag
bits : 15 - 15 (1 bit)
access : read-write


TOVALH

Watchdog Time-out Value Register High
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOVALH TOVALH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOVALHIGH

TOVALHIGH : Defines the upper 16 bits of the 32-bit time-out value for the watchdog timer
bits : 0 - 15 (16 bit)
access : read-write


TOVALL

Watchdog Time-out Value Register Low
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TOVALL TOVALL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOVALLOW

TOVALLOW : Defines the lower 16 bits of the 32-bit time-out value for the watchdog timer
bits : 0 - 15 (16 bit)
access : read-write


WINH

Watchdog Window Register High
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WINH WINH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WINHIGH

WINHIGH : Defines the upper 16 bits of the 32-bit window for the windowed mode of operation of the watchdog
bits : 0 - 15 (16 bit)
access : read-write


WINL

Watchdog Window Register Low
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WINL WINL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WINLOW

WINLOW : Defines the lower 16 bits of the 32-bit window for the windowed mode of operation of the watchdog
bits : 0 - 15 (16 bit)
access : read-write


REFRESH

Watchdog Refresh Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REFRESH REFRESH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDOGREFRESH

WDOGREFRESH : Watchdog refresh register
bits : 0 - 15 (16 bit)
access : read-write


UNLOCK

Watchdog Unlock Register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UNLOCK UNLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDOGUNLOCK

WDOGUNLOCK : Writing the unlock sequence values to this register to makes the watchdog write-once registers writable again
bits : 0 - 15 (16 bit)
access : read-write



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