Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x106C byte (0x0)
mem_usage : registers
protection : not protected
System Options Register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAMSIZE : RAM size
bits : 12 - 15 (4 bit)
access : read-only
Enumeration:
#0001 : 0001
8 KB
#0011 : 0011
16 KB
#0100 : 0100
24 KB
#0101 : 0101
32 KB
#0110 : 0110
48 KB
#0111 : 0111
64 KB
#1000 : 1000
96 KB
#1001 : 1001
128 KB
#1011 : 1011
256 KB
End of enumeration elements list.
OSC32KSEL : 32K oscillator clock select
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
System oscillator (OSC32KCLK)
#10 : 10
RTC 32.768kHz oscillator
#11 : 11
LPO 1 kHz
End of enumeration elements list.
USBVSTBY : USB voltage regulator in standby mode during VLPR and VLPW modes
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB voltage regulator not in standby during VLPR and VLPW modes.
#1 : 1
USB voltage regulator in standby during VLPR and VLPW modes.
End of enumeration elements list.
USBSSTBY : USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes.
#1 : 1
USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
End of enumeration elements list.
USBREGEN : USB voltage regulator enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB voltage regulator is disabled.
#1 : 1
USB voltage regulator is enabled.
End of enumeration elements list.
System Options Register 2
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTCCLKOUTSEL : RTC clock out select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC 1 Hz clock is output on the RTC_CLKOUT pin.
#1 : 1
RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
End of enumeration elements list.
CLKOUTSEL : CLKOUT select
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
#000 : 000
FlexBus CLKOUT
#010 : 010
Flash clock
#011 : 011
LPO clock (1 kHz)
#100 : 100
MCGIRCLK
#101 : 101
RTC 32.768kHz clock
#110 : 110
OSCERCLK0
#111 : 111
IRC 48 MHz clock
End of enumeration elements list.
FBSL : FlexBus security level
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
All off-chip accesses (instruction and data) via the FlexBus or SDRAM are disallowed.
#01 : 01
All off-chip accesses (instruction and data) via the FlexBus or SDRAM are disallowed.
#10 : 10
Off-chip instruction accesses are disallowed. Data accesses are allowed.
#11 : 11
Off-chip instruction accesses and data accesses are allowed.
End of enumeration elements list.
TRACECLKSEL : Debug trace clock select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
MCGOUTCLK, divided by the TRACECLK fractional divider as configured by SIM_CLKDIV4[TRACEFRAC, TRACEDIV]
#1 : 1
Core/system clock
End of enumeration elements list.
PLLFLLSEL : PLL/FLL clock select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
MCGFLLCLK clock
#01 : 01
MCGPLLCLK clock
#11 : 11
IRC48 MHz clock
End of enumeration elements list.
USBSRC : USB clock source select
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
External bypass clock (USB_CLKIN).
#1 : 1
MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by SIM_CLKDIV2[USBFRAC, USBDIV].
End of enumeration elements list.
FLEXIOSRC : FlexIO Module Clock Source Select
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 00
System clock
#01 : 01
MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the PLLFLLCLK fractional divider as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV].
#10 : 10
OSCERCLK clock
#11 : 11
MCGIRCLK clock
End of enumeration elements list.
TPMSRC : TPM clock source select
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
Clock disabled
#01 : 01
MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the PLLFLLCLK fractional divider as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV].
#10 : 10
OSCERCLK clock
#11 : 11
MCGIRCLK clock
End of enumeration elements list.
LPUARTSRC : LPUART clock source select
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 00
Clock disabled
#01 : 01
MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the PLLFLLCLK fractional divider as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV].
#10 : 10
OSCERCLK clock
#11 : 11
MCGIRCLK clock
End of enumeration elements list.
SDHCSRC : SDHC clock source select
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 00
Core/system clock.
#01 : 01
MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL].
#10 : 10
OSCERCLK clock
#11 : 11
External bypass clock (SDHC0_CLKIN)
End of enumeration elements list.
EMVSIMSRC : EMVSIM Module Clock Source Select
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 00
Clock disabled
#01 : 01
MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the PLLFLLCLK fractional divider as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV].
#10 : 10
OSCERCLK clock
#11 : 11
MCGIRCLK clock
End of enumeration elements list.
System Options Register 4
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTM0FLT0 : FTM0 Fault 0 Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM0_FLT0 pin
#1 : 1
CMP0 out
End of enumeration elements list.
FTM0FLT1 : FTM0 Fault 1 Select
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM0_FLT1 pin
#1 : 1
CMP1 out
End of enumeration elements list.
FTM1FLT0 : FTM1 Fault 0 Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM1_FLT0 pin
#1 : 1
CMP0 out
End of enumeration elements list.
FTM2FLT0 : FTM2 Fault 0 Select
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM2_FLT0 pin
#1 : 1
CMP0 out
End of enumeration elements list.
FTM3FLT0 : FTM3 Fault 0 Select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM3_FLT0 pin
#1 : 1
CMP0 out
End of enumeration elements list.
FTM1CH0SRC : FTM1 channel 0 input capture source select
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
FTM1_CH0 signal
#01 : 01
CMP0 output
#10 : 10
CMP1 output
#11 : 11
USB start of frame pulse
End of enumeration elements list.
FTM2CH0SRC : FTM2 channel 0 input capture source select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
FTM2_CH0 signal
#01 : 01
CMP0 output
#10 : 10
CMP1 output
End of enumeration elements list.
FTM2CH1SRC : FTM2 channel 1 input capture source select
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM2_CH1 signal
#1 : 1
Exclusive OR of FTM2_CH1, FTM2_CH0 and FTM1_CH1.
End of enumeration elements list.
FTM0CLKSEL : FlexTimer 0 External Clock Pin Select
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM_CLK0 pin
#1 : 1
FTM_CLK1 pin
End of enumeration elements list.
FTM1CLKSEL : FTM1 External Clock Pin Select
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM_CLK0 pin
#1 : 1
FTM_CLK1 pin
End of enumeration elements list.
FTM2CLKSEL : FlexTimer 2 External Clock Pin Select
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM2 external clock driven by FTM_CLK0 pin.
#1 : 1
FTM2 external clock driven by FTM_CLK1 pin.
End of enumeration elements list.
FTM3CLKSEL : FlexTimer 3 External Clock Pin Select
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM3 external clock driven by FTM_CLK0 pin.
#1 : 1
FTM3 external clock driven by FTM_CLK1 pin.
End of enumeration elements list.
FTM0TRG0SRC : FlexTimer 0 Hardware Trigger 0 Source Select
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
HSCMP0 output drives FTM0 hardware trigger 0
#1 : 1
FTM1 channel match drives FTM0 hardware trigger 0
End of enumeration elements list.
FTM0TRG1SRC : FlexTimer 0 Hardware Trigger 1 Source Select
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDB output trigger 1 drives FTM0 hardware trigger 1
#1 : 1
FTM2 channel match drives FTM0 hardware trigger 1
End of enumeration elements list.
FTM3TRG0SRC : FlexTimer 3 Hardware Trigger 0 Source Select
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#1 : 1
FTM1 channel match drives FTM3 hardware trigger 0
End of enumeration elements list.
FTM3TRG1SRC : FlexTimer 3 Hardware Trigger 1 Source Select
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#1 : 1
FTM2 channel match drives FTM3 hardware trigger 1
End of enumeration elements list.
System Options Register 5
address_offset : 0x1010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPUART0TXSRC : LPUART0 transmit data source select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 00
LPUART0_TX pin
#01 : 01
LPUART0_TX pin modulated with TPM1 channel 0 output
#10 : 10
LPUART0_TX pin modulated with TPM2 channel 0 output
End of enumeration elements list.
LPUART0RXSRC : LPUART0 receive data source select
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
LPUART0_RX pin
#01 : 01
CMP0 output
#10 : 10
CMP1 output
End of enumeration elements list.
LPUART1TXSRC : LPUART1 transmit data source select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
LPUART1_TX pin
#01 : 01
LPUART1_TX pin modulated with TPM1 channel 0 output
#10 : 10
LPUART0_TX pin modulated with TPM2 channel 0 output
End of enumeration elements list.
LPUART1RXSRC : LPUART1 receive data source select
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 00
LPUART1_RX pin
#01 : 01
CMP0 output
#10 : 10
CMP1 output
End of enumeration elements list.
System Options Register 7
address_offset : 0x1018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0TRGSEL : ADC0 trigger select
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
PDB external trigger pin input (PDB0_EXTRG)
#0001 : 0001
High speed comparator 0 output
#0010 : 0010
High speed comparator 1 output
#0100 : 0100
PIT trigger 0
#0101 : 0101
PIT trigger 1
#0110 : 0110
PIT trigger 2
#0111 : 0111
PIT trigger 3
#1000 : 1000
FTM0 trigger
#1001 : 1001
FTM1 trigger
#1010 : 1010
FTM2 trigger
#1011 : 1011
FTM3 trigger
#1100 : 1100
RTC alarm
#1101 : 1101
RTC seconds
#1110 : 1110
Low-power timer (LPTMR) trigger
#1111 : 1111
TPM1 channel 0 (A pretrigger) and channel 1 (B pretrigger)
End of enumeration elements list.
ADC0PRETRGSEL : ADC0 pretrigger select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pre-trigger A
#1 : 1
Pre-trigger B
End of enumeration elements list.
ADC0ALTTRGEN : ADC0 alternate trigger enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDB trigger selected for ADC0.
#1 : 1
Alternate trigger selected for ADC0.
End of enumeration elements list.
System Options Register 8
address_offset : 0x101C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTM0SYNCBIT : FTM0 Hardware Trigger 0 Software Synchronization
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert.
End of enumeration elements list.
FTM1SYNCBIT : FTM1 Hardware Trigger 0 Software Synchronization
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
Write 1 to assert the TRIG0 input to FTM1, software must clear this bit to allow other trigger sources to assert.
End of enumeration elements list.
FTM2SYNCBIT : FTM2 Hardware Trigger 0 Software Synchronization
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
Write 1 to assert the TRIG0 input to FTM2, software must clear this bit to allow other trigger sources to assert.
End of enumeration elements list.
FTM3SYNCBIT : FTM3 Hardware Trigger 0 Software Synchronization
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
Write 1 to assert the TRIG0 input to FTM3, software must clear this bit to allow other trigger sources to assert.
End of enumeration elements list.
FTM0OCH0SRC : FTM0 channel 0 output source
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM0_CH0 pin is output of FTM0 channel 0 output
#1 : 1
FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by FTM1 channel 1 output
End of enumeration elements list.
FTM0OCH1SRC : FTM0 channel 1 output source
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM0_CH1 pin is output of FTM0 channel 1 output
#1 : 1
FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by FTM1 channel 1 output
End of enumeration elements list.
FTM0OCH2SRC : FTM0 channel 2 output source
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM0_CH2 pin is output of FTM0 channel 2 output
#1 : 1
FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by FTM1 channel 1 output
End of enumeration elements list.
FTM0OCH3SRC : FTM0 channel 3 output source
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM0_CH3 pin is output of FTM0 channel 3 output
#1 : 1
FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by FTM1 channel 1 output
End of enumeration elements list.
FTM0OCH4SRC : FTM0 channel 4 output source
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM0_CH4 pin is output of FTM0 channel 4 output
#1 : 1
FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by FTM1 channel 1 output
End of enumeration elements list.
FTM0OCH5SRC : FTM0 channel 5 output source
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM0_CH5 pin is output of FTM0 channel 5 output
#1 : 1
FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by FTM1 channel 1 output
End of enumeration elements list.
FTM0OCH6SRC : FTM0 channel 6 output source
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM0_CH6 pin is output of FTM0 channel 6 output
#1 : 1
FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by FTM1 channel 1 output
End of enumeration elements list.
FTM0OCH7SRC : FTM0 channel 7 output source
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM0_CH7 pin is output of FTM0 channel 7 output
#1 : 1
FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by FTM1 channel 1 output
End of enumeration elements list.
FTM3OCH0SRC : FTM3 channel 0 output source
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM3_CH0 pin is output of FTM3 channel 0 output
#1 : 1
FTM3_CH0 pin is output of FTM3 channel 0 output modulated by FTM2 channel 1 output.
End of enumeration elements list.
FTM3OCH1SRC : FTM3 channel 1 output source
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM3_CH1 pin is output of FTM3 channel 1 output
#1 : 1
FTM3_CH1 pin is output of FTM3 channel 1 output modulated by FTM2 channel 1 output.
End of enumeration elements list.
FTM3OCH2SRC : FTM3 channel 2 output source
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM3_CH2 pin is output of FTM3 channel 2 output
#1 : 1
FTM3_CH2 pin is output of FTM3 channel 2 output modulated by FTM2 channel 1 output.
End of enumeration elements list.
FTM3OCH3SRC : FTM3 channel 3 output source
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM3_CH3 pin is output of FTM3 channel 3 output
#1 : 1
FTM3_CH3 pin is output of FTM3 channel 3 output modulated by FTM2 channel 1 output.
End of enumeration elements list.
FTM3OCH4SRC : FTM3 channel 4 output source
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM3_CH4 pin is output of FTM3 channel 4 output
#1 : 1
FTM3_CH4 pin is output of FTM3 channel 4 output modulated by FTM2 channel 1 output.
End of enumeration elements list.
FTM3OCH5SRC : FTM3 channel 5 output source
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM3_CH5 pin is output of FTM3 channel 5 output
#1 : 1
FTM3_CH5 pin is output of FTM3 channel 5 output modulated by FTM2 channel 1 output.
End of enumeration elements list.
FTM3OCH6SRC : FTM3 channel 6 output source
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM3_CH6 pin is output of FTM3 channel 6 output
#1 : 1
FTM3_CH6 pin is output of FTM3 channel 6 output modulated by FTM2 channel 1 output.
End of enumeration elements list.
FTM3OCH7SRC : FTM3 channel 7 output source
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM3_CH7 pin is output of FTM3 channel 7 output
#1 : 1
FTM3_CH7 pin is output of FTM3 channel 7 output modulated by FTM2 channel 1 output.
End of enumeration elements list.
System Options Register 9
address_offset : 0x1020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPM1CH0SRC : TPM1 channel 0 input capture source select
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
TPM1_CH0 signal
#01 : 01
CMP0 output
#10 : 10
CMP1 output
End of enumeration elements list.
TPM2CH0SRC : TPM2 channel 0 input capture source select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
TPM2_CH0 signal
#01 : 01
CMP0 output
#10 : 10
CMP1 output
End of enumeration elements list.
TPM1CLKSEL : TPM1 External Clock Pin Select
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
TPM_CLKIN0 pin
#1 : 1
TPM_CLKIN1 pin
End of enumeration elements list.
TPM2CLKSEL : TPM2 External Clock Pin Select
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
TPM_CLKIN0 pin
#1 : 1
TPM_CLKIN1 pin
End of enumeration elements list.
System Device Identification Register
address_offset : 0x1024 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PINID : Pincount identification
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
#0010 : 0010
32-pin
#0100 : 0100
48-pin
#0101 : 0101
64-pin
#0110 : 0110
80-pin
#0111 : 0111
81-pin or 121-pin
#1000 : 1000
100-pin
#1001 : 1001
121-pin
#1010 : 1010
144-pin
#1011 : 1011
Custom pinout (WLCSP)
#1100 : 1100
169-pin
#1110 : 1110
256-pin
End of enumeration elements list.
FAMID : Kinetis family identification
bits : 4 - 6 (3 bit)
access : read-only
Enumeration:
#000 : 000
K1x Family (without tamper)
#001 : 001
K2x Family (without tamper)
#010 : 010
K3x Family or K1x/K6x Family (with tamper)
#011 : 011
K4x Family or K2x Family (with tamper)
#100 : 100
K6x Family (without tamper)
#101 : 101
K7x Family
End of enumeration elements list.
DIEID : Device Die ID
bits : 7 - 11 (5 bit)
access : read-only
REVID : Device revision number
bits : 12 - 15 (4 bit)
access : read-only
SERIESID : Kinetis Series ID
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
#0000 : 0000
Kinetis K series
#0001 : 0001
Kinetis L series
#0101 : 0101
Kinetis W series
#0110 : 0110
Kinetis V series
End of enumeration elements list.
SUBFAMID : Kinetis Sub-Family ID
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
#0000 : 0000
Kx0 Subfamily
#0001 : 0001
Kx1 Subfamily (tamper detect)
#0010 : 0010
Kx2 Subfamily
#0011 : 0011
Kx3 Subfamily (tamper detect)
#0100 : 0100
Kx4 Subfamily
#0101 : 0101
Kx5 Subfamily (tamper detect)
#0110 : 0110
Kx6 Subfamily
End of enumeration elements list.
FAMILYID : Kinetis Family ID
bits : 28 - 31 (4 bit)
access : read-only
Enumeration:
#0000 : 0000
K0x Family
#0001 : 0001
K1x Family
#0010 : 0010
K2x Family
#0011 : 0011
K3x Family
#0100 : 0100
K4x Family
#0110 : 0110
K6x Family
#0111 : 0111
K7x Family
#1000 : 1000
K8x Family
End of enumeration elements list.
System Clock Gating Control Register 1
address_offset : 0x1028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C2 : I2C2 Clock Gate Control
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
I2C3 : I2C3 Clock Gate Control
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Gating Control Register 2
address_offset : 0x102C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPUART0 : LPUART0 Clock Gate Control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
LPUART1 : LPUART1 Clock Gate Control
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
LPUART2 : LPUART2 Clock Gate Control
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
LPUART3 : LPUART3 Clock Gate Control
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
TPM1 : TPM1 Clock Gate Control
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
TPM2 : TPM2 Clock Gate Control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
DAC0 : DAC0 Clock Gate Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
EMVSIM0 : EMVSIM0 Clock Gate Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
EMVSIM1 : EMVSIM1 Clock Gate Control
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
LPUART4 : LPUART4 Clock Gate Control
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
QSPI : QSPI Clock Gate Control
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
FLEXIO : FlexIO Clock Gate Control
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Gating Control Register 3
address_offset : 0x1030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRNG : TRNG Clock Gate Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
SPI2 : SPI2 Clock Gate Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
SDHC : SDHC Clock Gate Control
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
FTM2 : FTM2 Clock Gate Control
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
FTM3 : FTM3 Clock Gate Control
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Gating Control Register 4
address_offset : 0x1034 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EWM : EWM Clock Gate Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
CMT : CMT Clock Gate Control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
I2C0 : I2C0 Clock Gate Control
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
I2C1 : I2C1 Clock Gate Control
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
USBOTG : USB Clock Gate Control
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
CMP : Comparator Clock Gate Control
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
VREF : VREF Clock Gate Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Gating Control Register 5
address_offset : 0x1038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTMR : Low Power Timer Access Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Access disabled
#1 : 1
Access enabled
End of enumeration elements list.
LPTMR1 : LPTMR1 Clock Gate Control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Access disabled
#1 : 1
Access enabled
End of enumeration elements list.
TSI : TSI Clock Gate Control
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTA : Port A Clock Gate Control
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTB : Port B Clock Gate Control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTC : Port C Clock Gate Control
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTD : Port D Clock Gate Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTE : Port E Clock Gate Control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Gating Control Register 6
address_offset : 0x103C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTF : Flash Memory Clock Gate Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
DMAMUX : DMA Mux Clock Gate Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
SPI0 : SPI0 Clock Gate Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
SPI1 : SPI1 Clock Gate Control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
I2S : I2S Clock Gate Control
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
CRC : CRC Clock Gate Control
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
USBDCD : USB DCD Clock Gate Control
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PDB : PDB Clock Gate Control
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PIT : PIT Clock Gate Control
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
FTM0 : FTM0 Clock Gate Control
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
FTM1 : FTM1 Clock Gate Control
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
FTM2 : FTM2 Clock Gate Control
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
ADC0 : ADC0 Clock Gate Control
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
RTC : RTC Access Control
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Access and interrupts disabled
#1 : 1
Access and interrupts enabled
End of enumeration elements list.
DAC0 : DAC0 Clock Gate Control
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Gating Control Register 7
address_offset : 0x1040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLEXBUS : FlexBus Clock Gate Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
DMA : DMA Clock Gate Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
MPU : MPU Clock Gate Control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
SDRAMC : SDRAMC Clock Gate Control
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Divider Register 1
address_offset : 0x1044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTDIV4 : Clock 4 output divider value
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide-by-1.
#0001 : 0001
Divide-by-2.
#0010 : 0010
Divide-by-3.
#0011 : 0011
Divide-by-4.
#0100 : 0100
Divide-by-5.
#0101 : 0101
Divide-by-6.
#0110 : 0110
Divide-by-7.
#0111 : 0111
Divide-by-8.
#1000 : 1000
Divide-by-9.
#1001 : 1001
Divide-by-10.
#1010 : 1010
Divide-by-11.
#1011 : 1011
Divide-by-12.
#1100 : 1100
Divide-by-13.
#1101 : 1101
Divide-by-14.
#1110 : 1110
Divide-by-15.
#1111 : 1111
Divide-by-16.
End of enumeration elements list.
OUTDIV3 : Clock 3 output divider value
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide-by-1.
#0001 : 0001
Divide-by-2.
#0010 : 0010
Divide-by-3.
#0011 : 0011
Divide-by-4.
#0100 : 0100
Divide-by-5.
#0101 : 0101
Divide-by-6.
#0110 : 0110
Divide-by-7.
#0111 : 0111
Divide-by-8.
#1000 : 1000
Divide-by-9.
#1001 : 1001
Divide-by-10.
#1010 : 1010
Divide-by-11.
#1011 : 1011
Divide-by-12.
#1100 : 1100
Divide-by-13.
#1101 : 1101
Divide-by-14.
#1110 : 1110
Divide-by-15.
#1111 : 1111
Divide-by-16.
End of enumeration elements list.
OUTDIV2 : Clock 2 output divider value
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide-by-1.
#0001 : 0001
Divide-by-2.
#0010 : 0010
Divide-by-3.
#0011 : 0011
Divide-by-4.
#0100 : 0100
Divide-by-5.
#0101 : 0101
Divide-by-6.
#0110 : 0110
Divide-by-7.
#0111 : 0111
Divide-by-8.
#1000 : 1000
Divide-by-9.
#1001 : 1001
Divide-by-10.
#1010 : 1010
Divide-by-11.
#1011 : 1011
Divide-by-12.
#1100 : 1100
Divide-by-13.
#1101 : 1101
Divide-by-14.
#1110 : 1110
Divide-by-15.
#1111 : 1111
Divide-by-16.
End of enumeration elements list.
OUTDIV1 : Clock 1 output divider value
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide-by-1.
#0001 : 0001
Divide-by-2.
#0010 : 0010
Divide-by-3.
#0011 : 0011
Divide-by-4.
#0100 : 0100
Divide-by-5.
#0101 : 0101
Divide-by-6.
#0110 : 0110
Divide-by-7.
#0111 : 0111
Divide-by-8.
#1000 : 1000
Divide-by-9.
#1001 : 1001
Divide-by-10.
#1010 : 1010
Divide-by-11.
#1011 : 1011
Divide-by-12.
#1100 : 1100
Divide-by-13.
#1101 : 1101
Divide-by-14.
#1110 : 1110
Divide-by-15.
#1111 : 1111
Divide-by-16.
End of enumeration elements list.
System Clock Divider Register 2
address_offset : 0x1048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBFRAC : USB clock divider fraction
bits : 0 - 0 (1 bit)
access : read-write
USBDIV : USB clock divider divisor
bits : 1 - 3 (3 bit)
access : read-write
Flash Configuration Register 1
address_offset : 0x104C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLASHDIS : Flash Disable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash is enabled
#1 : 1
Flash is disabled
End of enumeration elements list.
FLASHDOZE : Flash Doze
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash remains enabled during Wait mode
#1 : 1
Flash is disabled for the duration of Wait mode
End of enumeration elements list.
PFSIZE : Program flash size
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
#0011 : 0011
32 KB of program flash memory
#0101 : 0101
64 KB of program flash memory
#0111 : 0111
128 KB of program flash memory
#1001 : 1001
256 KB of program flash memory
#1011 : 1011
512 KB of program flash memory
#1101 : 1101
1024 KB of program flash memory
#1111 : 1111
256 KB of program flash memory
End of enumeration elements list.
Flash Configuration Register 2
address_offset : 0x1050 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MAXADDR1 : Max address block 1
bits : 16 - 22 (7 bit)
access : read-only
MAXADDR0 : Max address block 0
bits : 24 - 30 (7 bit)
access : read-only
Unique Identification Register High
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only
Unique Identification Register Mid-High
address_offset : 0x1058 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only
Unique Identification Register Mid Low
address_offset : 0x105C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only
Unique Identification Register Low
address_offset : 0x1060 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only
System Clock Divider Register 3
address_offset : 0x1064 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLFLLFRAC : PLLFLL clock divider fraction
bits : 0 - 0 (1 bit)
access : read-write
PLLFLLDIV : PLLFLL clock divider divisor
bits : 1 - 3 (3 bit)
access : read-write
System Clock Divider Register 4
address_offset : 0x1068 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRACEFRAC : Trace clock divider fraction
bits : 0 - 0 (1 bit)
access : read-write
TRACEDIV : Trace clock divider divisor
bits : 1 - 3 (3 bit)
access : read-write
SOPT1 Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
URWE : USB voltage regulator enable write enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
SOPT1 USBREGEN cannot be written.
#1 : 1
SOPT1 USBREGEN can be written.
End of enumeration elements list.
UVSWE : USB voltage regulator VLP standby write enable
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
SOPT1 USBVSTBY cannot be written.
#1 : 1
SOPT1 USBVSTBY can be written.
End of enumeration elements list.
USSWE : USB voltage regulator stop standby write enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
SOPT1 USBSSTBY cannot be written.
#1 : 1
SOPT1 USBSSTBY can be written.
End of enumeration elements list.
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