\n

TRNG0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xF8 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MCTL

SDCTL

SBLIM

TOTSAM

FRQMIN

FRQCNT

FRQMAX

SCMC

SCML

SCR1C

SCR1L

SCR2C

SCR2L

SCR3C

SCR3L

SCR4C

SCR4L

SCR5C

SCR5L

SCR6PC

SCR6PL

STATUS

SCMISC

ENT0

ENT1

ENT2

ENT3

ENT4

ENT5

ENT6

ENT7

ENT8

ENT9

ENT10

ENT11

ENT12

ENT13

ENT14

ENT15

PKRRNG

PKRCNT10

PKRCNT32

PKRCNT54

PKRCNT76

PKRCNT98

PKRCNTBA

PKRCNTDC

PKRCNTFE

SEC_CFG

INT_CTRL

INT_MASK

INT_STATUS

PKRMAX

PKRSQ

VID1

VID2


MCTL

RNG Miscellaneous Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTL MCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMP_MODE OSC_DIV UNUSED TRNG_ACC RST_DEF FOR_SCLK FCT_FAIL FCT_VAL ENT_VAL TST_OUT ERR TSTOP_OK PRGM

SAMP_MODE : Sample Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

use Von Neumann data into both Entropy shifter and Statistical Checker

#01 : 01

use raw data into both Entropy shifter and Statistical Checker

#10 : 10

use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker

End of enumeration elements list.

OSC_DIV : Oscillator Divide
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

use ring oscillator with no divide

#01 : 01

use ring oscillator divided-by-2

#10 : 10

use ring oscillator divided-by-4

#11 : 11

use ring oscillator divided-by-8

End of enumeration elements list.

UNUSED : This bit is unused but write-able. Must be left as zero.
bits : 4 - 4 (1 bit)
access : read-write

TRNG_ACC : TRNG Access Mode
bits : 5 - 5 (1 bit)
access : read-write

RST_DEF : Reset Defaults
bits : 6 - 6 (1 bit)
access : write-only

FOR_SCLK : Force System Clock
bits : 7 - 7 (1 bit)
access : read-write

FCT_FAIL : Read only: Frequency Count Fail
bits : 8 - 8 (1 bit)
access : read-only

FCT_VAL : Read only: Frequency Count Valid. Indicates that a valid frequency count may be read from FRQCNT.
bits : 9 - 9 (1 bit)
access : read-only

ENT_VAL : Read only: Entropy Valid
bits : 10 - 10 (1 bit)
access : read-only

TST_OUT : Read only: Test point inside ring oscillator.
bits : 11 - 11 (1 bit)
access : read-only

ERR : Read: Error status
bits : 12 - 12 (1 bit)
access : read-write

TSTOP_OK : TRNG_OK_TO_STOP
bits : 13 - 13 (1 bit)
access : read-only

PRGM : Programming Mode Select
bits : 16 - 16 (1 bit)
access : read-write


SDCTL

RNG Seed Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDCTL SDCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMP_SIZE ENT_DLY

SAMP_SIZE : Sample Size
bits : 0 - 15 (16 bit)
access : read-write

ENT_DLY : Entropy Delay
bits : 16 - 31 (16 bit)
access : read-write


SBLIM

RNG Sparse Bit Limit Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TRNG0
reset_Mask : 0x0

SBLIM SBLIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SB_LIM

SB_LIM : Sparse Bit Limit
bits : 0 - 9 (10 bit)
access : read-write


TOTSAM

RNG Total Samples Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : TRNG0
reset_Mask : 0x0

TOTSAM TOTSAM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOT_SAM

TOT_SAM : Total Samples
bits : 0 - 19 (20 bit)
access : read-only


FRQMIN

RNG Frequency Count Minimum Limit Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRQMIN FRQMIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRQ_MIN

FRQ_MIN : Frequency Count Minimum Limit
bits : 0 - 21 (22 bit)
access : read-write


FRQCNT

RNG Frequency Count Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : TRNG0
reset_Mask : 0x0

FRQCNT FRQCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRQ_CT

FRQ_CT : Frequency Count
bits : 0 - 21 (22 bit)
access : read-only


FRQMAX

RNG Frequency Count Maximum Limit Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TRNG0
reset_Mask : 0x0

FRQMAX FRQMAX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRQ_MAX

FRQ_MAX : Frequency Counter Maximum Limit
bits : 0 - 21 (22 bit)
access : read-write


SCMC

RNG Statistical Check Monobit Count Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : TRNG0
reset_Mask : 0x0

SCMC SCMC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MONO_CT

MONO_CT : Monobit Count
bits : 0 - 15 (16 bit)
access : read-only


SCML

RNG Statistical Check Monobit Limit Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TRNG0
reset_Mask : 0x0

SCML SCML read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MONO_MAX MONO_RNG

MONO_MAX : Monobit Maximum Limit
bits : 0 - 15 (16 bit)
access : read-write

MONO_RNG : Monobit Range
bits : 16 - 31 (16 bit)
access : read-write


SCR1C

RNG Statistical Check Run Length 1 Count Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : TRNG0
reset_Mask : 0x0

SCR1C SCR1C read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R1_0_CT R1_1_CT

R1_0_CT : Runs of Zero, Length 1 Count
bits : 0 - 14 (15 bit)
access : read-only

R1_1_CT : Runs of One, Length 1 Count
bits : 16 - 30 (15 bit)
access : read-only


SCR1L

RNG Statistical Check Run Length 1 Limit Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TRNG0
reset_Mask : 0x0

SCR1L SCR1L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUN1_MAX RUN1_RNG

RUN1_MAX : Run Length 1 Maximum Limit
bits : 0 - 14 (15 bit)
access : read-write

RUN1_RNG : Run Length 1 Range
bits : 16 - 30 (15 bit)
access : read-write


SCR2C

RNG Statistical Check Run Length 2 Count Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : TRNG0
reset_Mask : 0x0

SCR2C SCR2C read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R2_0_CT R2_1_CT

R2_0_CT : Runs of Zero, Length 2 Count
bits : 0 - 13 (14 bit)
access : read-only

R2_1_CT : Runs of One, Length 2 Count
bits : 16 - 29 (14 bit)
access : read-only


SCR2L

RNG Statistical Check Run Length 2 Limit Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TRNG0
reset_Mask : 0x0

SCR2L SCR2L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUN2_MAX RUN2_RNG

RUN2_MAX : Run Length 2 Maximum Limit
bits : 0 - 13 (14 bit)
access : read-write

RUN2_RNG : Run Length 2 Range
bits : 16 - 29 (14 bit)
access : read-write


SCR3C

RNG Statistical Check Run Length 3 Count Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : TRNG0
reset_Mask : 0x0

SCR3C SCR3C read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R3_0_CT R3_1_CT

R3_0_CT : Runs of Zeroes, Length 3 Count
bits : 0 - 12 (13 bit)
access : read-only

R3_1_CT : Runs of Ones, Length 3 Count
bits : 16 - 28 (13 bit)
access : read-only


SCR3L

RNG Statistical Check Run Length 3 Limit Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TRNG0
reset_Mask : 0x0

SCR3L SCR3L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUN3_MAX RUN3_RNG

RUN3_MAX : Run Length 3 Maximum Limit
bits : 0 - 12 (13 bit)
access : read-write

RUN3_RNG : Run Length 3 Range
bits : 16 - 28 (13 bit)
access : read-write


SCR4C

RNG Statistical Check Run Length 4 Count Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : TRNG0
reset_Mask : 0x0

SCR4C SCR4C read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R4_0_CT R4_1_CT

R4_0_CT : Runs of Zero, Length 4 Count
bits : 0 - 11 (12 bit)
access : read-only

R4_1_CT : Runs of One, Length 4 Count
bits : 16 - 27 (12 bit)
access : read-only


SCR4L

RNG Statistical Check Run Length 4 Limit Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TRNG0
reset_Mask : 0x0

SCR4L SCR4L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUN4_MAX RUN4_RNG

RUN4_MAX : Run Length 4 Maximum Limit
bits : 0 - 11 (12 bit)
access : read-write

RUN4_RNG : Run Length 4 Range
bits : 16 - 27 (12 bit)
access : read-write


SCR5C

RNG Statistical Check Run Length 5 Count Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : TRNG0
reset_Mask : 0x0

SCR5C SCR5C read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R5_0_CT R5_1_CT

R5_0_CT : Runs of Zero, Length 5 Count
bits : 0 - 10 (11 bit)
access : read-only

R5_1_CT : Runs of One, Length 5 Count
bits : 16 - 26 (11 bit)
access : read-only


SCR5L

RNG Statistical Check Run Length 5 Limit Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TRNG0
reset_Mask : 0x0

SCR5L SCR5L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUN5_MAX RUN5_RNG

RUN5_MAX : Run Length 5 Maximum Limit
bits : 0 - 10 (11 bit)
access : read-write

RUN5_RNG : Run Length 5 Range
bits : 16 - 26 (11 bit)
access : read-write


SCR6PC

RNG Statistical Check Run Length 6+ Count Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : TRNG0
reset_Mask : 0x0

SCR6PC SCR6PC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6P_0_CT R6P_1_CT

R6P_0_CT : Runs of Zero, Length 6+ Count
bits : 0 - 10 (11 bit)
access : read-only

R6P_1_CT : Runs of One, Length 6+ Count
bits : 16 - 26 (11 bit)
access : read-only


SCR6PL

RNG Statistical Check Run Length 6+ Limit Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TRNG0
reset_Mask : 0x0

SCR6PL SCR6PL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUN6P_MAX RUN6P_RNG

RUN6P_MAX : Run Length 6+ Maximum Limit
bits : 0 - 10 (11 bit)
access : read-write

RUN6P_RNG : Run Length 6+ Range
bits : 16 - 26 (11 bit)
access : read-write


STATUS

RNG Status Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TF1BR0 TF1BR1 TF2BR0 TF2BR1 TF3BR0 TF3BR1 TF4BR0 TF4BR1 TF5BR0 TF5BR1 TF6PBR0 TF6PBR1 TFSB TFLR TFP TFMB RETRY_CT

TF1BR0 : Test Fail, 1-Bit Run, Sampling 0s. If TF1BR0=1, the 1-Bit Run, Sampling 0s Test has failed.
bits : 0 - 0 (1 bit)
access : read-only

TF1BR1 : Test Fail, 1-Bit Run, Sampling 1s. If TF1BR1=1, the 1-Bit Run, Sampling 1s Test has failed.
bits : 1 - 1 (1 bit)
access : read-only

TF2BR0 : Test Fail, 2-Bit Run, Sampling 0s. If TF2BR0=1, the 2-Bit Run, Sampling 0s Test has failed.
bits : 2 - 2 (1 bit)
access : read-only

TF2BR1 : Test Fail, 2-Bit Run, Sampling 1s. If TF2BR1=1, the 2-Bit Run, Sampling 1s Test has failed.
bits : 3 - 3 (1 bit)
access : read-only

TF3BR0 : Test Fail, 3-Bit Run, Sampling 0s. If TF3BR0=1, the 3-Bit Run, Sampling 0s Test has failed.
bits : 4 - 4 (1 bit)
access : read-only

TF3BR1 : Test Fail, 3-Bit Run, Sampling 1s. If TF3BR1=1, the 3-Bit Run, Sampling 1s Test has failed.
bits : 5 - 5 (1 bit)
access : read-only

TF4BR0 : Test Fail, 4-Bit Run, Sampling 0s. If TF4BR0=1, the 4-Bit Run, Sampling 0s Test has failed.
bits : 6 - 6 (1 bit)
access : read-only

TF4BR1 : Test Fail, 4-Bit Run, Sampling 1s. If TF4BR1=1, the 4-Bit Run, Sampling 1s Test has failed.
bits : 7 - 7 (1 bit)
access : read-only

TF5BR0 : Test Fail, 5-Bit Run, Sampling 0s. If TF5BR0=1, the 5-Bit Run, Sampling 0s Test has failed.
bits : 8 - 8 (1 bit)
access : read-only

TF5BR1 : Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed.
bits : 9 - 9 (1 bit)
access : read-only

TF6PBR0 : Test Fail, 6 Plus Bit Run, Sampling 0s
bits : 10 - 10 (1 bit)
access : read-only

TF6PBR1 : Test Fail, 6 Plus Bit Run, Sampling 1s
bits : 11 - 11 (1 bit)
access : read-only

TFSB : Test Fail, Sparse Bit. If TFSB=1, the Sparse Bit Test has failed.
bits : 12 - 12 (1 bit)
access : read-only

TFLR : Test Fail, Long Run. If TFLR=1, the Long Run Test has failed.
bits : 13 - 13 (1 bit)
access : read-only

TFP : Test Fail, Poker. If TFP=1, the Poker Test has failed.
bits : 14 - 14 (1 bit)
access : read-only

TFMB : Test Fail, Mono Bit. If TFMB=1, the Mono Bit Test has failed.
bits : 15 - 15 (1 bit)
access : read-only

RETRY_CT : RETRY COUNT
bits : 16 - 19 (4 bit)
access : read-only


SCMISC

RNG Statistical Check Miscellaneous Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCMISC SCMISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LRUN_MAX RTY_CT

LRUN_MAX : LONG RUN MAX LIMIT
bits : 0 - 7 (8 bit)
access : read-write

RTY_CT : RETRY COUNT
bits : 16 - 19 (4 bit)
access : read-write


ENT0

RNG TRNG Entropy Read Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT0 ENT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


ENT1

RNG TRNG Entropy Read Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT1 ENT1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


ENT2

RNG TRNG Entropy Read Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT2 ENT2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


ENT3

RNG TRNG Entropy Read Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT3 ENT3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


ENT4

RNG TRNG Entropy Read Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT4 ENT4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


ENT5

RNG TRNG Entropy Read Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT5 ENT5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


ENT6

RNG TRNG Entropy Read Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT6 ENT6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


ENT7

RNG TRNG Entropy Read Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT7 ENT7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


ENT8

RNG TRNG Entropy Read Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT8 ENT8 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


ENT9

RNG TRNG Entropy Read Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT9 ENT9 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


ENT10

RNG TRNG Entropy Read Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT10 ENT10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


ENT11

RNG TRNG Entropy Read Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT11 ENT11 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


ENT12

RNG TRNG Entropy Read Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT12 ENT12 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


ENT13

RNG TRNG Entropy Read Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT13 ENT13 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


ENT14

RNG TRNG Entropy Read Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT14 ENT14 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


ENT15

RNG TRNG Entropy Read Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ENT15 ENT15 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENT

ENT : Entropy Value
bits : 0 - 31 (32 bit)
access : read-only


PKRRNG

RNG Poker Range Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PKRRNG PKRRNG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKR_RNG

PKR_RNG : Poker Range
bits : 0 - 15 (16 bit)
access : read-write


PKRCNT10

RNG Statistical Check Poker Count 1 and 0 Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PKRCNT10 PKRCNT10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKR_0_CT PKR_1_CT

PKR_0_CT : Poker 0h Count
bits : 0 - 15 (16 bit)
access : read-only

PKR_1_CT : Poker 1h Count
bits : 16 - 31 (16 bit)
access : read-only


PKRCNT32

RNG Statistical Check Poker Count 3 and 2 Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PKRCNT32 PKRCNT32 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKR_2_CT PKR_3_CT

PKR_2_CT : Poker 2h Count
bits : 0 - 15 (16 bit)
access : read-only

PKR_3_CT : Poker 3h Count
bits : 16 - 31 (16 bit)
access : read-only


PKRCNT54

RNG Statistical Check Poker Count 5 and 4 Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PKRCNT54 PKRCNT54 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKR_4_CT PKR_5_CT

PKR_4_CT : Poker 4h Count
bits : 0 - 15 (16 bit)
access : read-only

PKR_5_CT : Poker 5h Count
bits : 16 - 31 (16 bit)
access : read-only


PKRCNT76

RNG Statistical Check Poker Count 7 and 6 Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PKRCNT76 PKRCNT76 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKR_6_CT PKR_7_CT

PKR_6_CT : Poker 6h Count
bits : 0 - 15 (16 bit)
access : read-only

PKR_7_CT : Poker 7h Count
bits : 16 - 31 (16 bit)
access : read-only


PKRCNT98

RNG Statistical Check Poker Count 9 and 8 Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PKRCNT98 PKRCNT98 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKR_8_CT PKR_9_CT

PKR_8_CT : Poker 8h Count
bits : 0 - 15 (16 bit)
access : read-only

PKR_9_CT : Poker 9h Count
bits : 16 - 31 (16 bit)
access : read-only


PKRCNTBA

RNG Statistical Check Poker Count B and A Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PKRCNTBA PKRCNTBA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKR_A_CT PKR_B_CT

PKR_A_CT : Poker Ah Count
bits : 0 - 15 (16 bit)
access : read-only

PKR_B_CT : Poker Bh Count
bits : 16 - 31 (16 bit)
access : read-only


PKRCNTDC

RNG Statistical Check Poker Count D and C Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PKRCNTDC PKRCNTDC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKR_C_CT PKR_D_CT

PKR_C_CT : Poker Ch Count
bits : 0 - 15 (16 bit)
access : read-only

PKR_D_CT : Poker Dh Count
bits : 16 - 31 (16 bit)
access : read-only


PKRCNTFE

RNG Statistical Check Poker Count F and E Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PKRCNTFE PKRCNTFE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKR_E_CT PKR_F_CT

PKR_E_CT : Poker Eh Count
bits : 0 - 15 (16 bit)
access : read-only

PKR_F_CT : Poker Fh Count
bits : 16 - 31 (16 bit)
access : read-only


SEC_CFG

RNG Security Configuration Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEC_CFG SEC_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SH0 NO_PRGM SK_VAL

SH0 : Reserved. DRNG specific, not applicable to this version.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

See DRNG version.

#1 : 1

See DRNG version.

End of enumeration elements list.

NO_PRGM : If set the TRNG registers cannot be programmed
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Programability of registers controlled only by the RNG Miscellaneous Control Register's access mode bit.

#1 : 1

Overides RNG Miscellaneous Control Register access mode and prevents TRNG register programming.

End of enumeration elements list.

SK_VAL : Reserved. DRNG-specific, not applicable to this version.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

See DRNG version.

#1 : 1

See DRNG version.

End of enumeration elements list.


INT_CTRL

RNG Interrupt Control Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_CTRL INT_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ERR ENT_VAL FRQ_CT_FAIL UNUSED

HW_ERR : Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding bit of INT_STATUS cleared.

#1 : 1

Corresponding bit of INT_STATUS active.

End of enumeration elements list.

ENT_VAL : Same behavior as bit 0 above.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Same behavior as bit 0 above.

#1 : 1

Same behavior as bit 0 above.

End of enumeration elements list.

FRQ_CT_FAIL : Same behavior as bit 0 above.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Same behavior as bit 0 above.

#1 : 1

Same behavior as bit 0 above.

End of enumeration elements list.

UNUSED : Reserved but writeable.
bits : 3 - 31 (29 bit)
access : read-write


INT_MASK

RNG Mask Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_MASK INT_MASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ERR ENT_VAL FRQ_CT_FAIL

HW_ERR : Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding interrupt of INT_STATUS is masked.

#1 : 1

Corresponding bit of INT_STATUS is active.

End of enumeration elements list.

ENT_VAL : Same behavior as bit 0 above.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Same behavior as bit 0 above.

#1 : 1

Same behavior as bit 0 above.

End of enumeration elements list.

FRQ_CT_FAIL : Same behavior as bit 0 above.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Same behavior as bit 0 above.

#1 : 1

Same behavior as bit 0 above.

End of enumeration elements list.


INT_STATUS

RNG Interrupt Status Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_STATUS INT_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ERR ENT_VAL FRQ_CT_FAIL

HW_ERR : Read: Error status
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

no error

#1 : 1

error detected.

End of enumeration elements list.

ENT_VAL : Read only: Entropy Valid
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Busy generation entropy. Any value read is invalid.

#1 : 1

TRNG can be stopped and entropy is valid if read.

End of enumeration elements list.

FRQ_CT_FAIL : Read only: Frequency Count Fail
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No hardware nor self test frequency errors.

#1 : 1

The frequency counter has detected a failure.

End of enumeration elements list.


PKRMAX

RNG Poker Maximum Limit Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TRNG0
reset_Mask : 0x0

PKRMAX PKRMAX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKR_MAX

PKR_MAX : Poker Maximum Limit
bits : 0 - 23 (24 bit)
access : read-write


PKRSQ

RNG Poker Square Calculation Result Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : TRNG0
reset_Mask : 0x0

PKRSQ PKRSQ read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKR_SQ

PKR_SQ : Poker Square Calculation Result
bits : 0 - 23 (24 bit)
access : read-only


VID1

RNG Version ID Register (MS)
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VID1 VID1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RNG_MIN_REV RNG_MAJ_REV RNG_IP_ID

RNG_MIN_REV : Shows the Freescale IP's Minor revision of the TRNG.
bits : 0 - 7 (8 bit)
access : read-only

Enumeration:

#0 : 0x00

Minor revision number for TRNG.

End of enumeration elements list.

RNG_MAJ_REV : Shows the Freescale IP's Major revision of the TRNG.
bits : 8 - 15 (8 bit)
access : read-only

Enumeration:

#1 : 0x01

Major revision number for TRNG.

End of enumeration elements list.

RNG_IP_ID : Shows the Freescale IP ID.
bits : 16 - 31 (16 bit)
access : read-only


VID2

RNG Version ID Register (LS)
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VID2 VID2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RNG_CONFIG_OPT RNG_ECO_REV RNG_INTG_OPT RNG_ERA

RNG_CONFIG_OPT : Shows the Freescale IP's Configuaration options for the TRNG.
bits : 0 - 7 (8 bit)
access : read-only

Enumeration:

#0 : 0x00

TRNG_CONFIG_OPT for TRNG.

End of enumeration elements list.

RNG_ECO_REV : Shows the Freescale IP's ECO revision of the TRNG.
bits : 8 - 15 (8 bit)
access : read-only

Enumeration:

#0 : 0x00

TRNG_ECO_REV for TRNG.

End of enumeration elements list.

RNG_INTG_OPT : Shows the Freescale integration options for the TRNG.
bits : 16 - 23 (8 bit)
access : read-only

Enumeration:

#0 : 0x00

INTG_OPT for TRNG.

End of enumeration elements list.

RNG_ERA : Shows the Freescale compile options for the TRNG.
bits : 24 - 31 (8 bit)
access : read-only

Enumeration:

#0 : 0x00

COMPILE_OPT for TRNG.

End of enumeration elements list.



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