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RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x808 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TSR

CR

SR

LR

IER

TTSR

MER

MCLR

MCHR

TER

TDR

TTR

TIR

TPR

TAR

WAR

RAR

TCR


TSR

RTC Time Seconds Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSR TSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSR

TSR : Time Seconds Register
bits : 0 - 31 (32 bit)
access : read-write


CR

RTC Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWR WPE SUP UM RESERVED OSCE CLKO SC16P SC8P SC4P SC2P RESERVED RESERVED

SWR : Software Reset
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers. The SWR bit is cleared after VBAT POR and by software explicitly clearing it.

End of enumeration elements list.

WPE : Wakeup Pin Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Wakeup pin is disabled.

#1 : 1

Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts and the chip is powered down.

End of enumeration elements list.

SUP : Supervisor Access
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Non-supervisor mode write accesses are not supported and generate a bus error.

#1 : 1

Non-supervisor mode write accesses are supported.

End of enumeration elements list.

UM : Update Mode
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Registers cannot be written when locked.

#1 : 1

Registers can be written when locked under limited conditions.

End of enumeration elements list.

RESERVED : no description available
bits : 4 - 7 (4 bit)
access : read-only

OSCE : Oscillator Enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

32.768 kHz oscillator is disabled.

#1 : 1

32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.

End of enumeration elements list.

CLKO : Clock Output
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

The 32kHz clock is output to other peripherals

#1 : 1

The 32kHz clock is not output to other peripherals

End of enumeration elements list.

SC16P : Oscillator 16pF load configure
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the load.

#1 : 1

Enable the additional load.

End of enumeration elements list.

SC8P : Oscillator 8pF load configure
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the load.

#1 : 1

Enable the additional load.

End of enumeration elements list.

SC4P : Oscillator 4pF load configure
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the load.

#1 : 1

Enable the additional load.

End of enumeration elements list.

SC2P : Oscillator 2pF load configure
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the load.

#1 : 1

Enable the additional load.

End of enumeration elements list.

RESERVED : no description available
bits : 14 - 14 (1 bit)
access : read-only

RESERVED : no description available
bits : 14 - 14 (1 bit)
access : read-only


SR

RTC Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIF TOF TAF MOF TCE RESERVED

TIF : Time Invalid Flag
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Time is valid.

#1 : 1

Time is invalid and time counter is read as zero.

End of enumeration elements list.

TOF : Time Overflow Flag
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Time overflow has not occurred.

#1 : 1

Time overflow has occurred and time counter is read as zero.

End of enumeration elements list.

TAF : Time Alarm Flag
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Time alarm has not occurred.

#1 : 1

Time alarm has occurred.

End of enumeration elements list.

MOF : Monotonic Overflow Flag
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

Monotonic counter overflow has not occurred.

#1 : 1

Monotonic counter overflow has occurred and monotonic counter is read as zero.

End of enumeration elements list.

TCE : Time Counter Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Time counter is disabled.

#1 : 1

Time counter is enabled.

End of enumeration elements list.

RESERVED : no description available
bits : 5 - 31 (27 bit)
access : read-only


LR

RTC Lock Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LR LR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED TCL CRL SRL LRL RESERVED RESERVED TTSL MEL MCLL MCHL TEL TDL TTL TIL

RESERVED : no description available
bits : 0 - 2 (3 bit)
access : read-only

TCL : Time Compensation Lock
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Time compensation register is locked and writes are ignored.

#1 : 1

Time compensation register is not locked and writes complete as normal.

End of enumeration elements list.

CRL : Control Register Lock
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Control register is locked and writes are ignored.

#1 : 1

Control register is not locked and writes complete as normal.

End of enumeration elements list.

SRL : Status Register Lock
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Status register is locked and writes are ignored.

#1 : 1

Status register is not locked and writes complete as normal.

End of enumeration elements list.

LRL : Lock Register Lock
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Lock register is locked and writes are ignored.

#1 : 1

Lock register is not locked and writes complete as normal.

End of enumeration elements list.

RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only

RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only

TTSL : Tamper Time Seconds Lock
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper time seconds register is locked and writes are ignored.

#1 : 1

Tamper time seconds register is not locked and writes complete as normal.

End of enumeration elements list.

MEL : Monotonic Enable Lock
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Monotonic enable register is locked and writes are ignored.

#1 : 1

Monotonic enable register is not locked and writes complete as normal.

End of enumeration elements list.

MCLL : Monotonic Counter Low Lock
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Monotonic counter low register is locked and writes are ignored.

#1 : 1

Monotonic counter low register is not locked and writes complete as normal.

End of enumeration elements list.

MCHL : Monotonic Counter High Lock
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Monotonic counter high register is locked and writes are ignored.

#1 : 1

Monotonic counter high register is not locked and writes complete as normal.

End of enumeration elements list.

TEL : Tamper Enable Lock
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper enable register is locked and writes are ignored.

#1 : 1

Tamper enable register is not locked and writes complete as normal.

End of enumeration elements list.

TDL : Tamper Detect Lock
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper detect register is locked and writes are ignored.

#1 : 1

Tamper detect register is not locked and writes complete as normal.

End of enumeration elements list.

TTL : Tamper Trim Lock
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper trim register is locked and writes are ignored.

#1 : 1

Tamper trim register is not locked and writes complete as normal.

End of enumeration elements list.

TIL : Tamper Interrupt Lock
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper interrupt register is locked and writes are ignored.

#1 : 1

Tamper interrupt register is not locked and writes complete as normal.

End of enumeration elements list.


IER

RTC Interrupt Enable Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIIE TOIE TAIE MOIE TSIE RESERVED RESERVED

TIIE : Time Invalid Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Time invalid flag does not generate an interrupt.

#1 : 1

Time invalid flag does generate an interrupt.

End of enumeration elements list.

TOIE : Time Overflow Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Time overflow flag does not generate an interrupt.

#1 : 1

Time overflow flag does generate an interrupt.

End of enumeration elements list.

TAIE : Time Alarm Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Time alarm flag does not generate an interrupt.

#1 : 1

Time alarm flag does generate an interrupt.

End of enumeration elements list.

MOIE : Monotonic Overflow Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Monotonic overflow flag does not generate an interrupt.

#1 : 1

Monotonic overflow flag does generate an interrupt.

End of enumeration elements list.

TSIE : Time Seconds Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Seconds interrupt is disabled.

#1 : 1

Seconds interrupt is enabled.

End of enumeration elements list.

RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-write

RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-write


TTSR

RTC Tamper Time Seconds Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TTSR TTSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TTS

TTS : Tamper Time Seconds
bits : 0 - 31 (32 bit)
access : read-only


MER

RTC Monotonic Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MER MER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED RESERVED MCE

RESERVED : no description available
bits : 0 - 3 (4 bit)
access : read-only

RESERVED : no description available
bits : 0 - 3 (4 bit)
access : read-only

MCE : Monotonic Counter Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writes to the monotonic counter load the counter with the value written.

#1 : 1

Writes to the monotonic counter increment the counter.

End of enumeration elements list.


MCLR

RTC Monotonic Counter Low Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCLR MCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCL

MCL : Monotonic Counter Low
bits : 0 - 31 (32 bit)
access : read-write


MCHR

RTC Monotonic Counter High Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCHR MCHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCH

MCH : Monotonic Counter High
bits : 0 - 31 (32 bit)
access : read-write


TER

RTC Tamper Enable Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TER TER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTE VTE CTE TTE FSE TME RESERVED

DTE : DryIce Tamper Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper source disabled.

#1 : 1

Set the time invalid flag if the DryIce tamper flag is set.

End of enumeration elements list.

VTE : Voltage Tamper Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper source disabled.

#1 : 1

Set the time invalid flag if the voltage tamper flag is set.

End of enumeration elements list.

CTE : Clock Tamper Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper source disabled.

#1 : 1

Set the time invalid flag if the clock tamper flag is set.

End of enumeration elements list.

TTE : Temperature Tamper Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper source disabled.

#1 : 1

Set the time invalid flag if the temperature tamper flag is set.

End of enumeration elements list.

FSE : Flash Security Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper source disabled.

#1 : 1

Set the time invalid flag if the flash security flag is set.

End of enumeration elements list.

TME : Test Mode Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper source disabled.

#1 : 1

Set the time invalid flag if the test mode flag is set.

End of enumeration elements list.

RESERVED : no description available
bits : 6 - 31 (26 bit)
access : read-only


TDR

RTC Tamper Detect Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TDR TDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTF VTF CTF TTF FSF TMF RESERVED

DTF : DryIce Tamper Flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper not detected.

#1 : 1

DryIce tamper detected.

End of enumeration elements list.

VTF : Voltage Tamper Flag
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper not detected.

#1 : 1

Voltage tampering detected.

End of enumeration elements list.

CTF : Clock Tamper Flag
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper not detected.

#1 : 1

Clock tampering detected.

End of enumeration elements list.

TTF : Temperature Tamper Flag
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper not detected.

#1 : 1

Temperature tampering detected.

End of enumeration elements list.

FSF : Flash Security Flag
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper not detected.

#1 : 1

Flash security tamper detected.

End of enumeration elements list.

TMF : Test Mode Flag
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper not detected.

#1 : 1

Test mode tamper detected.

End of enumeration elements list.

RESERVED : no description available
bits : 6 - 31 (26 bit)
access : read-only


TTR

RTC Tamper Trim Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TTR TTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VDTL VDTH CDTL CDTH TDTH TDTL RESERVED RESERVED

VDTL : Voltage Detect Trim Low
bits : 0 - 2 (3 bit)
access : read-write

VDTH : Voltage Detect Trim High
bits : 3 - 5 (3 bit)
access : read-write

CDTL : Clock Detect Trim Low
bits : 6 - 8 (3 bit)
access : read-write

CDTH : Clock Detect Trim High
bits : 9 - 11 (3 bit)
access : read-write

TDTH : Temperature Detect Trim High
bits : 12 - 14 (3 bit)
access : read-write

TDTL : Temperature Detect Trim Low
bits : 15 - 17 (3 bit)
access : read-write

RESERVED : no description available
bits : 18 - 28 (11 bit)
access : read-only

RESERVED : no description available
bits : 18 - 28 (11 bit)
access : read-only


TIR

RTC Tamper Interrupt Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIR TIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTIE VTIE CTIE TTIE FSIE TMIE RESERVED

DTIE : DryIce Tamper Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interupt disabled.

#1 : 1

An interrupt is generated when DryIce tamper flag is set.

End of enumeration elements list.

VTIE : Voltage Tamper Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interupt disabled.

#1 : 1

An interrupt is generated when the voltage tamper flag is set.

End of enumeration elements list.

CTIE : Clock Tamper Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interupt disabled.

#1 : 1

An interrupt is generated when the clock tamper flag is set.

End of enumeration elements list.

TTIE : Temperature Tamper Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interupt disabled.

#1 : 1

An interrupt is generated when the temperature tamper flag is set.

End of enumeration elements list.

FSIE : Flash Security Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interupt disabled.

#1 : 1

An interrupt is generated when the flash security flag is set.

End of enumeration elements list.

TMIE : Test Mode Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interupt disabled.

#1 : 1

An interrupt is generated when the test mode flag is set.

End of enumeration elements list.

RESERVED : no description available
bits : 6 - 31 (26 bit)
access : read-only


TPR

RTC Time Prescaler Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPR TPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPR RESERVED

TPR : Time Prescaler Register
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only


TAR

RTC Time Alarm Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAR TAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAR

TAR : Time Alarm Register
bits : 0 - 31 (32 bit)
access : read-write


WAR

RTC Write Access Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WAR WAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSRW TPRW TARW TCRW CRW SRW LRW IERW TTSW MERW MCLW MCHW TERW TDRW TTRW TIRW RESERVED

TSRW : Time Seconds Register Write
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writes to the time seconds register are ignored.

#1 : 1

Writes to the time seconds register complete as normal.

End of enumeration elements list.

TPRW : Time Prescaler Register Write
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writes to the time prescaler register are ignored.

#1 : 1

Writes to the time prescaler register complete as normal.

End of enumeration elements list.

TARW : Time Alarm Register Write
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writes to the time alarm register are ignored.

#1 : 1

Writes to the time alarm register complete as normal.

End of enumeration elements list.

TCRW : Time Compensation Register Write
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writes to the time compensation register are ignored.

#1 : 1

Writes to the time compensation register complete as normal.

End of enumeration elements list.

CRW : Control Register Write
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writes to the control register are ignored.

#1 : 1

Writes to the control register complete as normal.

End of enumeration elements list.

SRW : Status Register Write
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writes to the status register are ignored.

#1 : 1

Writes to the status register complete as normal.

End of enumeration elements list.

LRW : Lock Register Write
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writes to the lock register are ignored.

#1 : 1

Writes to the lock register complete as normal.

End of enumeration elements list.

IERW : Interrupt Enable Register Write
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writes to the interupt enable register are ignored.

#1 : 1

Writes to the interrupt enable register complete as normal.

End of enumeration elements list.

TTSW : Tamper Time Seconds Write
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writes to the tamper time seconds register are ignored.

#1 : 1

Writes to the tamper time seconds register complete as normal.

End of enumeration elements list.

MERW : Monotonic Enable Register Write
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writes to the monotonic enable register are ignored.

#1 : 1

Writes to the monotonic enable register complete as normal.

End of enumeration elements list.

MCLW : Monotonic Counter Low Write
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writes to the monotonic counter low register are ignored.

#1 : 1

Writes to the monotonic counter low register complete as normal.

End of enumeration elements list.

MCHW : Monotonic Counter High Write
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writes to the monotonic counter high register are ignored.

#1 : 1

Writes to the monotonic counter high register complete as normal.

End of enumeration elements list.

TERW : Tamper Enable Register Write
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writes to the tamper enable register are ignored.

#1 : 1

Writes to the tamper enable register complete as normal.

End of enumeration elements list.

TDRW : Tamper Detect Register Write
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writes to the tamper detect register are ignored.

#1 : 1

Writes to the tamper detect register complete as normal.

End of enumeration elements list.

TTRW : Tamper Trim Register Write
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writes to the tamper trim register are ignored.

#1 : 1

Writes to the tamper trim register complete as normal.

End of enumeration elements list.

TIRW : Tamper Interrupt Register Write
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writes to the tamper interrupt register are ignored.

#1 : 1

Writes to the tamper interrupt register complete as normal.

End of enumeration elements list.

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only


RAR

RTC Read Access Register
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAR RAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSRR TPRR TARR TCRR CRR SRR LRR IERR TTSR MERR MCLR MCHR TERR TDRR TTRR TIRR RESERVED

TSRR : Time Seconds Register Read
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reads to the time seconds register are ignored.

#1 : 1

Reads to the time seconds register complete as normal.

End of enumeration elements list.

TPRR : Time Prescaler Register Read
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reads to the time prescaler register are ignored.

#1 : 1

Reads to the time prescaler register complete as normal.

End of enumeration elements list.

TARR : Time Alarm Register Read
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reads to the time alarm register are ignored.

#1 : 1

Reads to the time alarm register complete as normal.

End of enumeration elements list.

TCRR : Time Compensation Register Read
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reads to the time compensation register are ignored.

#1 : 1

Reads to the time compensation register complete as normal.

End of enumeration elements list.

CRR : Control Register Read
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reads to the control register are ignored.

#1 : 1

Reads to the control register complete as normal.

End of enumeration elements list.

SRR : Status Register Read
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reads to the status register are ignored.

#1 : 1

Reads to the status register complete as normal.

End of enumeration elements list.

LRR : Lock Register Read
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reads to the lock register are ignored.

#1 : 1

Reads to the lock register complete as normal.

End of enumeration elements list.

IERR : Interrupt Enable Register Read
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reads to the interrupt enable register are ignored.

#1 : 1

Reads to the interrupt enable register complete as normal.

End of enumeration elements list.

TTSR : Tamper Time Seconds Read
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reads to the tamper time seconds register are ignored.

#1 : 1

Reads to the tamper time seconds register complete as normal.

End of enumeration elements list.

MERR : Monotonic Enable Register Read
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reads to the monotonic enable register are ignored.

#1 : 1

Reads to the monotonic enable register complete as normal.

End of enumeration elements list.

MCLR : Monotonic Counter Low Read
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reads to the monotonic counter low register are ignored.

#1 : 1

Reads to the monotonic counter low register complete as normal.

End of enumeration elements list.

MCHR : Monotonic Counter High Read
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reads to the monotonic counter high register are ignored.

#1 : 1

Reads to the monotonic counter high register complete as normal.

End of enumeration elements list.

TERR : Tamper Enable Register Read
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reads to the tamper enable register are ignored.

#1 : 1

Reads to the tamper enable register complete as normal.

End of enumeration elements list.

TDRR : Tamper Detect Register Read
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reads to the tamper detect register are ignored.

#1 : 1

Reads to the tamper detect register complete as normal.

End of enumeration elements list.

TTRR : Tamper Trim Register Read
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reads to the tamper trim register are ignored.

#1 : 1

Reads to the tamper trim register complete as normal.

End of enumeration elements list.

TIRR : Tamper Interrupt Register Read
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Reads to the tamper interrupt register are ignored.

#1 : 1

Reads to the tamper interrupt register complete as normal.

End of enumeration elements list.

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only


TCR

RTC Time Compensation Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCR CIR TCV CIC

TCR : Time Compensation Register
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

#10000000 : 10000000

Time prescaler register overflows every 32896 clock cycles.

#11111111 : 11111111

Time prescaler register overflows every 32769 clock cycles.

#0 : 0

Time prescaler register overflows every 32768 clock cycles.

#1 : 1

Time prescaler register overflows every 32767 clock cycles.

#1111111 : 1111111

Time prescaler register overflows every 32641 clock cycles.

End of enumeration elements list.

CIR : Compensation Interval Register
bits : 8 - 15 (8 bit)
access : read-write

TCV : Time Compensation Value
bits : 16 - 23 (8 bit)
access : read-only

CIC : Compensation Interval Counter
bits : 24 - 31 (8 bit)
access : read-only



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