\n
address_offset : 0x0 Bytes (0x0)
size : 0x300 byte (0x0)
mem_usage : registers
protection : not protected
Flash Access Protection Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0AP : Master 0 Access Protection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M1AP : Master 1 Access Protection
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M2AP : Master 2 Access Protection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M3AP : Master 3 Access Protection
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M4AP : Master 4 Access Protection
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
No access may be performed by this master
#01 : 01
Only read accesses may be performed by this master
#10 : 10
Only write accesses may be performed by this master
#11 : 11
Both read and write accesses may be performed by this master
End of enumeration elements list.
M0PFD : Master 0 Prefetch Disable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
M1PFD : Master 1 Prefetch Disable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
M2PFD : Master 2 Prefetch Disable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
M3PFD : Master 3 Prefetch Disable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
M4PFD : Master 4 Prefetch Disable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Prefetching for this master is enabled.
#1 : 1
Prefetching for this master is disabled.
End of enumeration elements list.
Cache Tag Storage
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write
Cache Tag Storage
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write
Cache Tag Storage
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write
Cache Tag Storage
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write
Cache Tag Storage
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write
Cache Tag Storage
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write
Cache Tag Storage
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write
Cache Tag Storage
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write
Flash Bank 0 Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
B0SEBE : Bank 0 Single Entry Buffer Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Single entry buffer is disabled.
#1 : 1
Single entry buffer is enabled.
End of enumeration elements list.
B0IPE : Bank 0 Instruction Prefetch Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not prefetch in response to instruction fetches.
#1 : 1
Enable prefetches in response to instruction fetches.
End of enumeration elements list.
B0DPE : Bank 0 Data Prefetch Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not prefetch in response to data references.
#1 : 1
Enable prefetches in response to data references.
End of enumeration elements list.
B0ICE : Bank 0 Instruction Cache Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not cache instruction fetches.
#1 : 1
Cache instruction fetches.
End of enumeration elements list.
B0DCE : Bank 0 Data Cache Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not cache data references.
#1 : 1
Cache data references.
End of enumeration elements list.
CRC : Cache Replacement Control
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
#000 : 000
LRU replacement algorithm per set across all four ways
#010 : 010
Independent LRU with ways [0-1] for ifetches, [2-3] for data
#011 : 011
Independent LRU with ways [0-2] for ifetches, [3] for data
End of enumeration elements list.
B0MW : Bank 0 Memory Width
bits : 17 - 18 (2 bit)
access : read-only
Enumeration:
#00 : 00
32 bits
#01 : 01
64 bits
#10 : 10
128 bits
End of enumeration elements list.
S_B_INV : Invalidate Prefetch Speculation Buffer
bits : 19 - 19 (1 bit)
access : write-only
Enumeration:
#0 : 0
Speculation buffer and single entry buffer are not affected.
#1 : 1
Invalidate (clear) speculation buffer and single entry buffer.
End of enumeration elements list.
CINV_WAY : Cache Invalidate Way x
bits : 20 - 23 (4 bit)
access : write-only
Enumeration:
#0000 : 0
No cache way invalidation for the corresponding cache
#0001 : 1
Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected
End of enumeration elements list.
CLCK_WAY : Cache Lock Way x
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
Cache way is unlocked and may be displaced
#0001 : 1
Cache way is locked and its contents are not displaced
End of enumeration elements list.
B0RWSC : Bank 0 Read Wait State Control
bits : 28 - 31 (4 bit)
access : read-only
Cache Data Storage (uppermost word)
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-upper word)
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write
Cache Data Storage (mid-lower word)
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lowermost word)
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write
Cache Data Storage (uppermost word)
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-upper word)
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write
Cache Data Storage (mid-lower word)
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lowermost word)
address_offset : 0x498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0x4CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write
Cache Data Storage (uppermost word)
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-upper word)
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-lower word)
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write
Cache Data Storage (lowermost word)
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write
Cache Data Storage (uppermost word)
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-upper word)
address_offset : 0x588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-lower word)
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lowermost word)
address_offset : 0x598 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Tag Storage
address_offset : 0x5B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write
Cache Tag Storage
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write
cache_tag : 14-bit tag for cache entry
bits : 6 - 19 (14 bit)
access : read-write
Cache Data Storage (uppermost word)
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-upper word)
address_offset : 0x61C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-lower word)
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lowermost word)
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (uppermost word)
address_offset : 0x6D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-upper word)
address_offset : 0x6DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-lower word)
address_offset : 0x6E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lowermost word)
address_offset : 0x6F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (uppermost word)
address_offset : 0x790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-upper word)
address_offset : 0x79C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-lower word)
address_offset : 0x7A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lowermost word)
address_offset : 0x7B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Reserved
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Cache Data Storage (uppermost word)
address_offset : 0x830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-upper word)
address_offset : 0x840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-lower word)
address_offset : 0x850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (uppermost word)
address_offset : 0x850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-upper word)
address_offset : 0x85C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lowermost word)
address_offset : 0x860 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-lower word)
address_offset : 0x868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lowermost word)
address_offset : 0x874 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (uppermost word)
address_offset : 0x930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-upper word)
address_offset : 0x940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-lower word)
address_offset : 0x950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lowermost word)
address_offset : 0x960 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (uppermost word)
address_offset : 0xA30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-upper word)
address_offset : 0xA40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-lower word)
address_offset : 0xA50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (uppermost word)
address_offset : 0xA60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lowermost word)
address_offset : 0xA60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-upper word)
address_offset : 0xA74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-lower word)
address_offset : 0xA88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lowermost word)
address_offset : 0xA9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (uppermost word)
address_offset : 0xB30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-upper word)
address_offset : 0xB40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-lower word)
address_offset : 0xB50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lowermost word)
address_offset : 0xB60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (uppermost word)
address_offset : 0xBA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-upper word)
address_offset : 0xBB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-lower word)
address_offset : 0xBC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lowermost word)
address_offset : 0xBDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (uppermost word)
address_offset : 0xCE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-upper word)
address_offset : 0xCF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-lower word)
address_offset : 0xD08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lowermost word)
address_offset : 0xD1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (uppermost word)
address_offset : 0xE20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [127:96] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-upper word)
address_offset : 0xE34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [95:64] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (mid-lower word)
address_offset : 0xE48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write
Cache Data Storage (lowermost word)
address_offset : 0xE5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write
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