\n
address_offset : 0x0 Bytes (0x0)
size : 0xCC byte (0x0)
mem_usage : registers
protection : not protected
Pin Control Register n
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x57C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x5E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x6CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x7C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Global Pin Control Low Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
GPWD : Global Pin Write Data
bits : 0 - 15 (16 bit)
access : write-only
GPWE : Global Pin Write Enable
bits : 16 - 31 (16 bit)
access : write-only
Global Pin Control High Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
GPWD : Global Pin Write Data
bits : 0 - 15 (16 bit)
access : write-only
GPWE : Global Pin Write Enable
bits : 16 - 31 (16 bit)
access : write-only
Pin Control Register n
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Interrupt Status Flag Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISF : Interrupt Status Flag
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to the flag. If configured for a level sensitive interrupt and the pin remains asserted then the flag will set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Pin Control Register n
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
Digital Filter Enable Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFE : Digital Filter Enable
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
#0 : 0
Digital Filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the bit.
#1 : 1
Digital Filter is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
Digital Filter Clock Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CS : Clock Source
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital Filters are clocked by the bus clock.
#1 : 1
Digital Filters are clocked by the 1 kHz LPO clock.
End of enumeration elements list.
RESERVED : no description available
bits : 1 - 31 (31 bit)
access : read-only
Digital Filter Width Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILT : Filter Length
bits : 0 - 4 (5 bit)
access : read-write
RESERVED : no description available
bits : 5 - 31 (27 bit)
access : read-only
Pin Control Register n
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
#1 : 1
Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pull-up or pull-down resistor is not enabled on the corresponding pin.
#1 : 1
Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive Input Filter is disabled on the corresponding pin.
#1 : 1
Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open Drain output is disabled on the corresponding pin.
#1 : 1
Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin Disabled (Analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip specific).
#011 : 011
Alternative 3 (chip specific).
#100 : 100
Alternative 4 (chip specific).
#101 : 101
Alternative 5 (chip specific).
#110 : 110
Alternative 6 (chip specific).
#111 : 111
Alternative 7 (chip specific / JTAG / NMI).
End of enumeration elements list.
RESERVED : no description available
bits : 11 - 14 (4 bit)
access : read-only
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register bits [15:0] are not locked.
#1 : 1
Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt/DMA Request disabled.
#0001 : 0001
DMA Request on rising edge.
#0010 : 0010
DMA Request on falling edge.
#0011 : 0011
DMA Request on either edge.
#0100 : 0100
Reserved.
#1000 : 1000
Interrupt when logic zero.
#1001 : 1001
Interrupt on rising edge.
#1010 : 1010
Interrupt on falling edge.
#1011 : 1011
Interrupt on either edge.
#1100 : 1100
Interrupt when logic one.
End of enumeration elements list.
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt has not been detected.
#1 : 1
Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately.
End of enumeration elements list.
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