\n
address_offset : 0x0 Bytes (0x0)
size : 0xA4 byte (0x0)
mem_usage : registers
protection : not protected
Pin Control Register n
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x57C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x5E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x6CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x7C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Global Pin Control Low Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
GPWD : Global Pin Write Data
bits : 0 - 15 (16 bit)
access : write-only
GPWE : Global Pin Write Enable
bits : 16 - 31 (16 bit)
access : write-only
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
Global Pin Control High Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
GPWD : Global Pin Write Data
bits : 0 - 15 (16 bit)
access : write-only
GPWE : Global Pin Write Enable
bits : 16 - 31 (16 bit)
access : write-only
Enumeration:
#0 : 0
Corresponding Pin Control Register is not updated with the value in GPWD.
#1 : 1
Corresponding Pin Control Register is updated with the value in GPWD.
End of enumeration elements list.
Pin Control Register n
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Interrupt Status Flag Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISF : Interrupt Status Flag
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
Pin Control Register n
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
#1 : 1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
End of enumeration elements list.
PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#1 : 1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
End of enumeration elements list.
SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1 : 1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Passive input filter is disabled on the corresponding pin.
#1 : 1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
End of enumeration elements list.
ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Open drain output is disabled on the corresponding pin.
#1 : 1
Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
End of enumeration elements list.
DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1 : 1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
End of enumeration elements list.
MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Pin disabled (Alternative 0) (analog).
#001 : 001
Alternative 1 (GPIO).
#010 : 010
Alternative 2 (chip-specific).
#011 : 011
Alternative 3 (chip-specific).
#100 : 100
Alternative 4 (chip-specific).
#101 : 101
Alternative 5 (chip-specific).
#110 : 110
Alternative 6 (chip-specific).
#111 : 111
Alternative 7 (chip-specific).
End of enumeration elements list.
LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Control Register fields [15:0] are not locked.
#1 : 1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
End of enumeration elements list.
IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Interrupt Status Flag (ISF) is disabled.
#0001 : 0001
ISF flag and DMA request on rising edge.
#0010 : 0010
ISF flag and DMA request on falling edge.
#0011 : 0011
ISF flag and DMA request on either edge.
#1000 : 1000
ISF flag and Interrupt when logic 0.
#1001 : 1001
ISF flag and Interrupt on rising-edge.
#1010 : 1010
ISF flag and Interrupt on falling-edge.
#1011 : 1011
ISF flag and Interrupt on either edge.
#1100 : 1100
ISF flag and Interrupt when logic 1.
End of enumeration elements list.
ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configured interrupt is not detected.
#1 : 1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
End of enumeration elements list.
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