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MCM

Peripheral Memory Blocks

address_offset : 0x8 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

Registers

ISCR

ETBCC

ETBRL

ETBCNT

FADR

FATR

FDR

PID

PLASC

PLAMC

CR


ISCR

Interrupt Status and control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISCR ISCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED IRQ NMI DHREQ CWBER RESERVED FIOC FDZC FOFC FUFC FIXC RESERVED FIDC RESERVED CWBEE RESERVED RESERVED FIOCE FDZCE FOFCE FUFCE FIXCE FIDCE

RESERVED : no description available
bits : 0 - 0 (1 bit)
access : read-only

IRQ : Normal Interrupt Pending
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No pending interrupt

#1 : 1

Due to the ETB counter expiring, a normal interrupt is pending

End of enumeration elements list.

NMI : Nonmaskable Interrupt Pending
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No pending NMI

#1 : 1

Due to the ETB counter expiring, an NMI is pending

End of enumeration elements list.

DHREQ : Debug Halt Request Indicator
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

No debug halt request

#1 : 1

Debug halt request initiated

End of enumeration elements list.

CWBER : Cache write buffer error status
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No error

#1 : 1

Error occurred

End of enumeration elements list.

RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-only

FIOC : FPU invalid operation interrupt status
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

#0 : 0

No interrupt

#1 : 1

Interrupt occurred

End of enumeration elements list.

FDZC : FPU divide-by-zero interrupt status
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

#0 : 0

No interrupt

#1 : 1

Interrupt occurred

End of enumeration elements list.

FOFC : FPU overflow interrupt status
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

#0 : 0

No interrupt

#1 : 1

Interrupt occurred

End of enumeration elements list.

FUFC : FPU underflow interrupt status
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

#0 : 0

No interrupt

#1 : 1

Interrupt occurred

End of enumeration elements list.

FIXC : FPU inexact interrupt status
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

#0 : 0

No interrupt

#1 : 1

Interrupt occurred

End of enumeration elements list.

RESERVED : no description available
bits : 13 - 14 (2 bit)
access : read-only

FIDC : FPU input denormal interrupt status
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

#0 : 0

No interrupt

#1 : 1

Interrupt occurred

End of enumeration elements list.

RESERVED : no description available
bits : 16 - 19 (4 bit)
access : read-only

CWBEE : Cache write buffer error enable
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable error interrupt

#1 : 1

Enable error interrupt

End of enumeration elements list.

RESERVED : no description available
bits : 21 - 23 (3 bit)
access : read-only

RESERVED : no description available
bits : 21 - 23 (3 bit)
access : read-only

FIOCE : FPU invalid operation interrupt enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt

#1 : 1

Enable interrupt

End of enumeration elements list.

FDZCE : FPU divide-by-zero interrupt enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt

#1 : 1

Enable interrupt

End of enumeration elements list.

FOFCE : FPU overflow interrupt enable
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt

#1 : 1

Enable interrupt

End of enumeration elements list.

FUFCE : FPU underflow interrupt enable
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt

#1 : 1

Enable interrupt

End of enumeration elements list.

FIXCE : FPU inexact interrupt enable
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt

#1 : 1

Enable interrupt

End of enumeration elements list.

FIDCE : FPU input denormal interrupt enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable interrupt

#1 : 1

Enable interrupt

End of enumeration elements list.


ETBCC

ETB Counter Control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETBCC ETBCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTEN RSPT RLRQ ETDIS ITDIS RESERVED

CNTEN : Counter Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

ETB counter disabled

#1 : 1

ETB counter enabled

End of enumeration elements list.

RSPT : Response Type
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 00

No response when the ETB count expires

#01 : 01

Generate a normal interrupt when the ETB count expires

#10 : 10

Generate an NMI when the ETB count expires

#11 : 11

Generate a debug halt when the ETB count expires

End of enumeration elements list.

RLRQ : Reload Request
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clears pending debug halt, NMI, or IRQ interrupt requests

End of enumeration elements list.

ETDIS : ETM-To-TPIU Disable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

ETM-to-TPIU trace path enabled

#1 : 1

ETM-to-TPIU trace path disabled

End of enumeration elements list.

ITDIS : ITM-To-TPIU Disable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

ITM-to-TPIU trace path enabled

#1 : 1

ITM-to-TPIU trace path disabled

End of enumeration elements list.

RESERVED : no description available
bits : 6 - 31 (26 bit)
access : read-only


ETBRL

ETB Reload register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ETBRL ETBRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RELOAD RESERVED

RELOAD : Byte Count Reload Value
bits : 0 - 10 (11 bit)
access : read-write

RESERVED : no description available
bits : 11 - 31 (21 bit)
access : read-only


ETBCNT

ETB Counter Value register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ETBCNT ETBCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNTER RESERVED

COUNTER : Byte Count Counter Value
bits : 0 - 10 (11 bit)
access : read-only

RESERVED : no description available
bits : 11 - 31 (21 bit)
access : read-only


FADR

Fault address register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FADR FADR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS

ADDRESS : Fault address
bits : 0 - 31 (32 bit)
access : read-only


FATR

Fault attributes register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FATR FATR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BEDA BEMD RESERVED BESZ RESERVED RESERVED BEWT BEMN BEOVR

BEDA : Bus error access type
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Instruction

#1 : 1

Data

End of enumeration elements list.

BEMD : Bus error privilege level
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

User mode

#1 : 1

Supervisor/privileged mode

End of enumeration elements list.

RESERVED : no description available
bits : 2 - 3 (2 bit)
access : read-only

BESZ : Bus error size
bits : 4 - 5 (2 bit)
access : read-only

Enumeration:

#00 : 00

8-bit access

#01 : 01

16-bit access

#10 : 10

32-bit access

#11 : 11

Reserved

End of enumeration elements list.

RESERVED : no description available
bits : 6 - 6 (1 bit)
access : read-only

RESERVED : no description available
bits : 6 - 6 (1 bit)
access : read-only

BEWT : Bus error write
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

Read access

#1 : 1

Write access

End of enumeration elements list.

BEMN : Bus error master number
bits : 8 - 11 (4 bit)
access : read-only

BEOVR : Bus error overrun
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

No bus error overrun

#1 : 1

Bus error overrun occurred. The FADR and FDR registers and the other FATR bits are not updated to reflect this new bus error.

End of enumeration elements list.


FDR

Fault data register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDR FDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Fault data
bits : 0 - 31 (32 bit)
access : read-only


PID

Process ID register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PID PID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID RESERVED

PID : M0_PID and M1_PID for MPU
bits : 0 - 7 (8 bit)
access : read-write

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only


PLASC

Crossbar Switch (AXBS) Slave Configuration
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PLASC PLASC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASC RESERVED

ASC : Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.
bits : 0 - 7 (8 bit)
access : read-only

Enumeration:

#0 : 0

A bus slave connection to AXBS input port n is absent

#1 : 1

A bus slave connection to AXBS input port n is present

End of enumeration elements list.

RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only


PLAMC

Crossbar Switch (AXBS) Master Configuration
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PLAMC PLAMC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMC RESERVED

AMC : Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
bits : 0 - 7 (8 bit)
access : read-only

Enumeration:

#0 : 0

A bus master connection to AXBS input port n is absent

#1 : 1

A bus master connection to AXBS input port n is present

End of enumeration elements list.

RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only


CR

Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED RESERVED RESERVED DDRSIZE RESERVED SRAMUAP SRAMUWP RESERVED RESERVED SRAMLAP SRAMLWP

RESERVED : no description available
bits : 0 - 8 (9 bit)
access : read-only

RESERVED : no description available
bits : 9 - 9 (1 bit)
access : read-only

RESERVED : no description available
bits : 10 - 19 (10 bit)
access : read-only

DDRSIZE : DDR address size translation
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 00

DDR address translation is disabled

#01 : 01

DDR size is 128 Mbytes

#10 : 10

DDR size is 256 Mbytes

#11 : 11

DDR size is 512 Mbytes

End of enumeration elements list.

RESERVED : no description available
bits : 22 - 23 (2 bit)
access : read-only

SRAMUAP : SRAM_U arbitration priority
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 00

Round robin

#01 : 01

Special round robin (favors SRAM backoor accesses over the processor)

#10 : 10

Fixed priority. Processor has highest, backdoor has lowest

#11 : 11

Fixed priority. Backdoor has highest, processor has lowest

End of enumeration elements list.

SRAMUWP : SRAM_U write protect
bits : 26 - 26 (1 bit)
access : read-write

RESERVED : no description available
bits : 27 - 27 (1 bit)
access : read-only

RESERVED : no description available
bits : 27 - 27 (1 bit)
access : read-only

SRAMLAP : SRAM_L arbitration priority
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

#00 : 00

Round robin

#01 : 01

Special round robin (favors SRAM backoor accesses over the processor)

#10 : 10

Fixed priority. Processor has highest, backdoor has lowest

#11 : 11

Fixed priority. Backdoor has highest, processor has lowest

End of enumeration elements list.

SRAMLWP : SRAM_L Write Protect
bits : 30 - 30 (1 bit)
access : read-write



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