Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1400 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDBG : Enable Debug
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
When in debug mode, the DMA continues to operate.
#1 : 1
When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
End of enumeration elements list.
ERCA : Enable Round Robin Channel Arbitration
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fixed priority arbitration is used for channel selection within each group.
#1 : 1
Round robin arbitration is used for channel selection within each group.
End of enumeration elements list.
ERGA : Enable Round Robin Group Arbitration
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fixed priority arbitration is used for selection among the groups.
#1 : 1
Round robin arbitration is used for selection among the groups.
End of enumeration elements list.
HOE : Halt On Error
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
End of enumeration elements list.
HALT : Halt DMA Operations
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
End of enumeration elements list.
CLM : Continuous Link Mode
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
A minor loop channel link made to itself goes through channel arbitration before being activated again.
#1 : 1
A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.
End of enumeration elements list.
EMLM : Enable Minor Loop Mapping
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
#1 : 1
Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.
End of enumeration elements list.
GRP0PRI : Channel Group 0 Priority
bits : 8 - 8 (1 bit)
access : read-write
GRP1PRI : Channel Group 1 Priority
bits : 10 - 10 (1 bit)
access : read-write
ECX : Error Cancel Transfer
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.
End of enumeration elements list.
CX : Cancel Transfer
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x1069 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x10D20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x10D60 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x10D80 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x10DA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x10DA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x10DA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x10DE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x10E20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x10E60 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x10E80 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x10E80 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x10EA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x10EE0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x10F00 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x10F00 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x1178 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x11F00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x11F44 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x11F66 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x11F88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x11F88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x11F88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x11FCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x12010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x12054 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x12076 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x12076 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x12098 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x120DC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x120FE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x120FE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x1288 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x13100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x13148 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x1316C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x13190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x13190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x13190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x131D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x13220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x13268 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1328C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1328C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x132B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x132F8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1331C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1331C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x1399 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
Enable Error Interrupt Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EEI0 : Enable Error Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI1 : Enable Error Interrupt 1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI2 : Enable Error Interrupt 2
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI3 : Enable Error Interrupt 3
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI4 : Enable Error Interrupt 4
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI5 : Enable Error Interrupt 5
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI6 : Enable Error Interrupt 6
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI7 : Enable Error Interrupt 7
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI8 : Enable Error Interrupt 8
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI9 : Enable Error Interrupt 9
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI10 : Enable Error Interrupt 10
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI11 : Enable Error Interrupt 11
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI12 : Enable Error Interrupt 12
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI13 : Enable Error Interrupt 13
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI14 : Enable Error Interrupt 14
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI15 : Enable Error Interrupt 15
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI16 : Enable Error Interrupt 16
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI17 : Enable Error Interrupt 17
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI18 : Enable Error Interrupt 18
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI19 : Enable Error Interrupt 19
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI20 : Enable Error Interrupt 20
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI21 : Enable Error Interrupt 21
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI22 : Enable Error Interrupt 22
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI23 : Enable Error Interrupt 23
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI24 : Enable Error Interrupt 24
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI25 : Enable Error Interrupt 25
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI26 : Enable Error Interrupt 26
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI27 : Enable Error Interrupt 27
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI28 : Enable Error Interrupt 28
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI29 : Enable Error Interrupt 29
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI30 : Enable Error Interrupt 30
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
EEI31 : Enable Error Interrupt 31
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error signal for corresponding channel does not generate an error interrupt
#1 : 1
The assertion of the error signal for corresponding channel generates an error interrupt request
End of enumeration elements list.
TCD Source Address
address_offset : 0x14320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x1436C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x14392 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x143B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x143B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x143B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x14404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x14450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x1449C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x144C2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x144C2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x144E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x14534 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1455A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1455A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x14AB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x15560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x155B0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x155D8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x15600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x15600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x15600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x15650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x156A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x156F0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x15718 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x15718 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x15740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x15790 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x157B8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x157B8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x15BE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x167C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x16814 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x1683E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x16868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x16868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x16868 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x168BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x16910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x16964 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1698E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1698E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x169B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x16A0C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x16A36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x16A36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x16D2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x17A40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x17A98 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x17AC4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x17AF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x17AF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x17AF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x17B48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x17BA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x17BF8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x17C24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x17C24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x17C50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x17CA8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x17CD4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x17CD4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x17E7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
Clear Enable Error Interrupt Register
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CEEI : Clear Enable Error Interrupt
bits : 0 - 4 (5 bit)
access : write-only
CAEE : Clear All Enable Error Interrupts
bits : 6 - 6 (1 bit)
access : write-only
Enumeration:
#0 : 0
Clear only the EEI bit specified in the CEEI field
#1 : 1
Clear all bits in EEI
End of enumeration elements list.
NOP : No Op enable
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
#0 : 0
Normal operation
#1 : 1
No operation, ignore the other bits in this register
End of enumeration elements list.
TCD Source Address
address_offset : 0x18CE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x18D3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x18D6A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x18D98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x18D98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x18D98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x18DF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x18E50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x18EAC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x18EDA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x18EDA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x18F08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x18F64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x18F92 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x18F92 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x18FD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
Set Enable Error Interrupt Register
address_offset : 0x19 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SEEI : Set Enable Error Interrupt
bits : 0 - 4 (5 bit)
access : write-only
SAEE : Sets All Enable Error Interrupts
bits : 6 - 6 (1 bit)
access : write-only
Enumeration:
#0 : 0
Set only the EEI bit specified in the SEEI field.
#1 : 1
Sets all bits in EEI
End of enumeration elements list.
NOP : No Op enable
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
#0 : 0
Normal operation
#1 : 1
No operation, ignore the other bits in this register
End of enumeration elements list.
TCD Source Address
address_offset : 0x19FA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
Clear Enable Request Register
address_offset : 0x1A Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CERQ : Clear Enable Request
bits : 0 - 4 (5 bit)
access : write-only
CAER : Clear All Enable Requests
bits : 6 - 6 (1 bit)
access : write-only
Enumeration:
#0 : 0
Clear only the ERQ bit specified in the CERQ field
#1 : 1
Clear all bits in ERQ
End of enumeration elements list.
NOP : No Op enable
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
#0 : 0
Normal operation
#1 : 1
No operation, ignore the other bits in this register
End of enumeration elements list.
TCD Signed Source Address Offset
address_offset : 0x1A000 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x1A030 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x1A060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x1A060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x1A060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x1A0C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x1A120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
Channel n Priority Register
address_offset : 0x1A14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Signed Destination Address Offset
address_offset : 0x1A180 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1A1B0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1A1B0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x1A1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x1A240 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1A270 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1A270 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Set Enable Request Register
address_offset : 0x1B Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SERQ : Set Enable Request
bits : 0 - 4 (5 bit)
access : write-only
SAER : Set All Enable Requests
bits : 6 - 6 (1 bit)
access : write-only
Enumeration:
#0 : 0
Set only the ERQ bit specified in the SERQ field
#1 : 1
Set all bits in ERQ
End of enumeration elements list.
NOP : No Op enable
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
#0 : 0
Normal operation
#1 : 1
No operation, ignore the other bits in this register
End of enumeration elements list.
TCD Source Address
address_offset : 0x1B280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
Channel n Priority Register
address_offset : 0x1B2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Signed Source Address Offset
address_offset : 0x1B2E4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x1B316 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x1B348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x1B348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x1B348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x1B3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x1B410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x1B474 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1B4A6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1B4A6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x1B4D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x1B53C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1B56E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1B56E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Clear DONE Status Bit Register
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CDNE : Clear DONE Bit
bits : 0 - 4 (5 bit)
access : write-only
CADN : Clears All DONE Bits
bits : 6 - 6 (1 bit)
access : write-only
Enumeration:
#0 : 0
Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
#1 : 1
Clears all bits in TCDn_CSR[DONE]
End of enumeration elements list.
NOP : No Op enable
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
#0 : 0
Normal operation
#1 : 1
No operation, ignore the other bits in this register
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x1C45 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x1C580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x1C5E8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x1C61C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x1C650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x1C650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x1C650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x1C6B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x1C720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x1C788 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1C7BC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1C7BC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x1C7F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x1C858 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1C88C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1C88C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Set START Bit Register
address_offset : 0x1D Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SSRT : Set START Bit
bits : 0 - 4 (5 bit)
access : write-only
SAST : Set All START Bits (activates all channels)
bits : 6 - 6 (1 bit)
access : write-only
Enumeration:
#0 : 0
Set only the TCDn_CSR[START] bit specified in the SSRT field
#1 : 1
Set all bits in TCDn_CSR[START]
End of enumeration elements list.
NOP : No Op enable
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
#0 : 0
Normal operation
#1 : 1
No operation, ignore the other bits in this register
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x1D5F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x1D8A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x1D90C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x1D942 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x1D978 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x1D978 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x1D978 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x1D9E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x1DA50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x1DABC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1DAF2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1DAF2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x1DB28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x1DB94 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1DBCA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1DBCA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Clear Error Register
address_offset : 0x1E Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CERR : Clear Error Indicator
bits : 0 - 4 (5 bit)
access : write-only
CAEI : Clear All Error Indicators
bits : 6 - 6 (1 bit)
access : write-only
Enumeration:
#0 : 0
Clear only the ERR bit specified in the CERR field
#1 : 1
Clear all bits in ERR
End of enumeration elements list.
NOP : No Op enable
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
#0 : 0
Normal operation
#1 : 1
No operation, ignore the other bits in this register
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x1E7A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x1EBE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x1EC50 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x1EC88 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x1ECC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x1ECC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x1ECC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x1ED30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x1EDA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x1EE10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1EE48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1EE48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x1EE80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x1EEF0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x1EF28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x1EF28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Clear Interrupt Request Register
address_offset : 0x1F Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CINT : Clear Interrupt Request
bits : 0 - 4 (5 bit)
access : write-only
CAIR : Clear All Interrupt Requests
bits : 6 - 6 (1 bit)
access : write-only
Enumeration:
#0 : 0
Clear only the INT bit specified in the CINT field
#1 : 1
Clear all bits in INT
End of enumeration elements list.
NOP : No Op enable
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
#0 : 0
Normal operation
#1 : 1
No operation, ignore the other bits in this register
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x1F96 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x1FF40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x1FFB4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x1FFEE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x200 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x2000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x20028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x20028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x20028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Source Address Offset
address_offset : 0x2008 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Last Source Address Adjustment
address_offset : 0x2009C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x200C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x2010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x2010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x2010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Destination Address
address_offset : 0x20110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Last Source Address Adjustment
address_offset : 0x2018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x20184 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x201BE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x201BE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x201F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x2020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x2026C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Signed Destination Address Offset
address_offset : 0x2028 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x202A6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x202A6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x202C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x202C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x2030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x2038 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x203C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x203C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x20B3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x212C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x21338 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x21374 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x213B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x213B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x213B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x21428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x214A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x21518 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x21554 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x21554 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x21590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x21608 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x21644 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x21644 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x21D1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x22660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x226DC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x2271A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x22758 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x22758 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x22758 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x227D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x22850 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x228CC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x2290A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x2290A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x22948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x229C4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x22A02 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x22A02 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x22F0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x23A20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x23AA0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x23AE0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x23B20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x23B20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x23B20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x23BA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x23C20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x23CA0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x23CE0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x23CE0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x23D20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x23DA0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x23DE0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x23DE0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Interrupt Request Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT0 : Interrupt Request 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT1 : Interrupt Request 1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT2 : Interrupt Request 2
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT3 : Interrupt Request 3
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT4 : Interrupt Request 4
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT5 : Interrupt Request 5
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT6 : Interrupt Request 6
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT7 : Interrupt Request 7
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT8 : Interrupt Request 8
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT9 : Interrupt Request 9
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT10 : Interrupt Request 10
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT11 : Interrupt Request 11
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT12 : Interrupt Request 12
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT13 : Interrupt Request 13
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT14 : Interrupt Request 14
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT15 : Interrupt Request 15
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT16 : Interrupt Request 16
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT17 : Interrupt Request 17
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT18 : Interrupt Request 18
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT19 : Interrupt Request 19
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT20 : Interrupt Request 20
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT21 : Interrupt Request 21
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT22 : Interrupt Request 22
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT23 : Interrupt Request 23
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT24 : Interrupt Request 24
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT25 : Interrupt Request 25
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT26 : Interrupt Request 26
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT27 : Interrupt Request 27
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT28 : Interrupt Request 28
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT29 : Interrupt Request 29
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT30 : Interrupt Request 30
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
INT31 : Interrupt Request 31
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt request for corresponding channel is cleared
#1 : 1
The interrupt request for corresponding channel is active
End of enumeration elements list.
TCD Source Address
address_offset : 0x24E00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x24E84 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x24EC6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x24F08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x24F08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x24F08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x24F8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x25010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x25094 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x250D6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x250D6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x25118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x2519C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x251DE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x251DE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Error Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERR0 : Error In Channel 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR1 : Error In Channel 1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR2 : Error In Channel 2
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR3 : Error In Channel 3
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR4 : Error In Channel 4
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR5 : Error In Channel 5
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR6 : Error In Channel 6
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR7 : Error In Channel 7
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR8 : Error In Channel 8
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR9 : Error In Channel 9
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR10 : Error In Channel 10
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR11 : Error In Channel 11
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR12 : Error In Channel 12
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR13 : Error In Channel 13
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR14 : Error In Channel 14
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR15 : Error In Channel 15
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR16 : Error In Channel 16
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR17 : Error In Channel 17
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR18 : Error In Channel 18
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR19 : Error In Channel 19
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR20 : Error In Channel 20
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR21 : Error In Channel 21
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR22 : Error In Channel 22
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR23 : Error In Channel 23
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR24 : Error In Channel 24
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR25 : Error In Channel 25
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR26 : Error In Channel 26
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR27 : Error In Channel 27
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR28 : Error In Channel 28
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR29 : Error In Channel 29
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR30 : Error In Channel 30
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
ERR31 : Error In Channel 31
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
An error in this channel has not occurred
#1 : 1
An error in this channel has occurred
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x301 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x3020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x302C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x3032 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x3038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x3038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x3038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x3044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x3050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x305C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x3062 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x3062 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x3068 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x3074 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x307A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x307A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Hardware Request Status Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HRS0 : Hardware Request Status Channel 0
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 0 is not present
#1 : 1
A hardware service request for channel 0 is present
End of enumeration elements list.
HRS1 : Hardware Request Status Channel 1
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 1 is not present
#1 : 1
A hardware service request for channel 1 is present
End of enumeration elements list.
HRS2 : Hardware Request Status Channel 2
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 2 is not present
#1 : 1
A hardware service request for channel 2 is present
End of enumeration elements list.
HRS3 : Hardware Request Status Channel 3
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 3 is not present
#1 : 1
A hardware service request for channel 3 is present
End of enumeration elements list.
HRS4 : Hardware Request Status Channel 4
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 4 is not present
#1 : 1
A hardware service request for channel 4 is present
End of enumeration elements list.
HRS5 : Hardware Request Status Channel 5
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 5 is not present
#1 : 1
A hardware service request for channel 5 is present
End of enumeration elements list.
HRS6 : Hardware Request Status Channel 6
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 6 is not present
#1 : 1
A hardware service request for channel 6 is present
End of enumeration elements list.
HRS7 : Hardware Request Status Channel 7
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 7 is not present
#1 : 1
A hardware service request for channel 7 is present
End of enumeration elements list.
HRS8 : Hardware Request Status Channel 8
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 8 is not present
#1 : 1
A hardware service request for channel 8 is present
End of enumeration elements list.
HRS9 : Hardware Request Status Channel 9
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 9 is not present
#1 : 1
A hardware service request for channel 9 is present
End of enumeration elements list.
HRS10 : Hardware Request Status Channel 10
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 10 is not present
#1 : 1
A hardware service request for channel 10 is present
End of enumeration elements list.
HRS11 : Hardware Request Status Channel 11
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 11 is not present
#1 : 1
A hardware service request for channel 11 is present
End of enumeration elements list.
HRS12 : Hardware Request Status Channel 12
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 12 is not present
#1 : 1
A hardware service request for channel 12 is present
End of enumeration elements list.
HRS13 : Hardware Request Status Channel 13
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 13 is not present
#1 : 1
A hardware service request for channel 13 is present
End of enumeration elements list.
HRS14 : Hardware Request Status Channel 14
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 14 is not present
#1 : 1
A hardware service request for channel 14 is present
End of enumeration elements list.
HRS15 : Hardware Request Status Channel 15
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 15 is not present
#1 : 1
A hardware service request for channel 15 is present
End of enumeration elements list.
HRS16 : Hardware Request Status Channel 16
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 16 is not present
#1 : 1
A hardware service request for channel 16 is present
End of enumeration elements list.
HRS17 : Hardware Request Status Channel 17
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 17 is not present
#1 : 1
A hardware service request for channel 17 is present
End of enumeration elements list.
HRS18 : Hardware Request Status Channel 18
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 18 is not present
#1 : 1
A hardware service request for channel 18 is present
End of enumeration elements list.
HRS19 : Hardware Request Status Channel 19
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 19 is not present
#1 : 1
A hardware service request for channel 19 is present
End of enumeration elements list.
HRS20 : Hardware Request Status Channel 20
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 20 is not present
#1 : 1
A hardware service request for channel 20 is present
End of enumeration elements list.
HRS21 : Hardware Request Status Channel 21
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 21 is not present
#1 : 1
A hardware service request for channel 21 is present
End of enumeration elements list.
HRS22 : Hardware Request Status Channel 22
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 22 is not present
#1 : 1
A hardware service request for channel 22 is present
End of enumeration elements list.
HRS23 : Hardware Request Status Channel 23
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 23 is not present
#1 : 1
A hardware service request for channel 23 is present
End of enumeration elements list.
HRS24 : Hardware Request Status Channel 24
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 24 is not present
#1 : 1
A hardware service request for channel 24 is present
End of enumeration elements list.
HRS25 : Hardware Request Status Channel 25
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 25 is not present
#1 : 1
A hardware service request for channel 25 is present
End of enumeration elements list.
HRS26 : Hardware Request Status Channel 26
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 26 is not present
#1 : 1
A hardware service request for channel 26 is present
End of enumeration elements list.
HRS27 : Hardware Request Status Channel 27
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 27 is not present
#1 : 1
A hardware service request for channel 27 is present
End of enumeration elements list.
HRS28 : Hardware Request Status Channel 28
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 28 is not present
#1 : 1
A hardware service request for channel 28 is present
End of enumeration elements list.
HRS29 : Hardware Request Status Channel 29
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 29 is not preset
#1 : 1
A hardware service request for channel 29 is present
End of enumeration elements list.
HRS30 : Hardware Request Status Channel 30
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 30 is not present
#1 : 1
A hardware service request for for channel 30 is present
End of enumeration elements list.
HRS31 : Hardware Request Status Channel 31
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
A hardware service request for channel 31 is not present
#1 : 1
A hardware service request for channel 31 is present
End of enumeration elements list.
Error Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DBE : Destination Bus Error
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
No destination bus error
#1 : 1
The last recorded error was a bus error on a destination write
End of enumeration elements list.
SBE : Source Bus Error
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
No source bus error
#1 : 1
The last recorded error was a bus error on a source read
End of enumeration elements list.
SGE : Scatter/Gather Configuration Error
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
No scatter/gather configuration error
#1 : 1
The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
End of enumeration elements list.
NCE : NBYTES/CITER Configuration Error
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
No NBYTES/CITER configuration error
#1 : 1
The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
End of enumeration elements list.
DOE : Destination Offset Error
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
No destination offset configuration error
#1 : 1
The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
End of enumeration elements list.
DAE : Destination Address Error
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
No destination address configuration error
#1 : 1
The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
End of enumeration elements list.
SOE : Source Offset Error
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
No source offset configuration error
#1 : 1
The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
End of enumeration elements list.
SAE : Source Address Error
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No source address configuration error.
#1 : 1
The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
End of enumeration elements list.
ERRCHN : Error Channel Number or Canceled Channel Number
bits : 8 - 12 (5 bit)
access : read-only
CPE : Channel Priority Error
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
No channel priority error
#1 : 1
The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique.
End of enumeration elements list.
GPE : Group Priority Error
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
No group priority error
#1 : 1
The last recorded error was a configuration error among the group priorities. All group priorities are not unique.
End of enumeration elements list.
ECX : Transfer Canceled
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
No canceled transfers
#1 : 1
The last recorded entry was a canceled transfer by the error cancel transfer input
End of enumeration elements list.
VLD : Logical OR of all ERR status bits
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
No ERR bits are set.
#1 : 1
At least one ERR bit is set indicating a valid error exists that has not been cleared.
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x403 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x4060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x4070 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x4078 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x4080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x4080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x4080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x4090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x40A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x40B0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x40B8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x40B8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x40C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x40D0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x40D8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x40D8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Enable Asynchronous Request in Stop Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDREQ_0 : Enable asynchronous DMA request in stop mode for channel 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 0.
#1 : 1
Enable asynchronous DMA request for channel 0.
End of enumeration elements list.
EDREQ_1 : Enable asynchronous DMA request in stop mode for channel 1.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 1
#1 : 1
Enable asynchronous DMA request for channel 1.
End of enumeration elements list.
EDREQ_2 : Enable asynchronous DMA request in stop mode for channel 2.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 2.
#1 : 1
Enable asynchronous DMA request for channel 2.
End of enumeration elements list.
EDREQ_3 : Enable asynchronous DMA request in stop mode for channel 3.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 3.
#1 : 1
Enable asynchronous DMA request for channel 3.
End of enumeration elements list.
EDREQ_4 : Enable asynchronous DMA request in stop mode for channel 4
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 4.
#1 : 1
Enable asynchronous DMA request for channel 4.
End of enumeration elements list.
EDREQ_5 : Enable asynchronous DMA request in stop mode for channel 5
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 5.
#1 : 1
Enable asynchronous DMA request for channel 5.
End of enumeration elements list.
EDREQ_6 : Enable asynchronous DMA request in stop mode for channel 6
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 6.
#1 : 1
Enable asynchronous DMA request for channel 6.
End of enumeration elements list.
EDREQ_7 : Enable asynchronous DMA request in stop mode for channel 7
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 7.
#1 : 1
Enable asynchronous DMA request for channel 7.
End of enumeration elements list.
EDREQ_8 : Enable asynchronous DMA request in stop mode for channel 8
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 8.
#1 : 1
Enable asynchronous DMA request for channel 8.
End of enumeration elements list.
EDREQ_9 : Enable asynchronous DMA request in stop mode for channel 9
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 9.
#1 : 1
Enable asynchronous DMA request for channel 9.
End of enumeration elements list.
EDREQ_10 : Enable asynchronous DMA request in stop mode for channel 10
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 10.
#1 : 1
Enable asynchronous DMA request for channel 10.
End of enumeration elements list.
EDREQ_11 : Enable asynchronous DMA request in stop mode for channel 11
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 11.
#1 : 1
Enable asynchronous DMA request for channel 11.
End of enumeration elements list.
EDREQ_12 : Enable asynchronous DMA request in stop mode for channel 12
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 12.
#1 : 1
Enable asynchronous DMA request for channel 12.
End of enumeration elements list.
EDREQ_13 : Enable asynchronous DMA request in stop mode for channel 13
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 13.
#1 : 1
Enable asynchronous DMA request for channel 13.
End of enumeration elements list.
EDREQ_14 : Enable asynchronous DMA request in stop mode for channel 14
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 14.
#1 : 1
Enable asynchronous DMA request for channel 14.
End of enumeration elements list.
EDREQ_15 : Enable asynchronous DMA request in stop mode for channel 15
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 15.
#1 : 1
Enable asynchronous DMA request for channel 15.
End of enumeration elements list.
EDREQ_16 : Enable asynchronous DMA request in stop mode for channel 16
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 16
#1 : 1
Enable asynchronous DMA request for channel 16
End of enumeration elements list.
EDREQ_17 : Enable asynchronous DMA request in stop mode for channel 17
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 17
#1 : 1
Enable asynchronous DMA request for channel 17
End of enumeration elements list.
EDREQ_18 : Enable asynchronous DMA request in stop mode for channel 18
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 18
#1 : 1
Enable asynchronous DMA request for channel 18
End of enumeration elements list.
EDREQ_19 : Enable asynchronous DMA request in stop mode for channel 19
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 19
#1 : 1
Enable asynchronous DMA request for channel 19
End of enumeration elements list.
EDREQ_20 : Enable asynchronous DMA request in stop mode for channel 20
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 20
#1 : 1
Enable asynchronous DMA request for channel 20
End of enumeration elements list.
EDREQ_21 : Enable asynchronous DMA request in stop mode for channel 21
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 21
#1 : 1
Enable asynchronous DMA request for channel 21
End of enumeration elements list.
EDREQ_22 : Enable asynchronous DMA request in stop mode for channel 22
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 22
#1 : 1
Enable asynchronous DMA request for channel 22
End of enumeration elements list.
EDREQ_23 : Enable asynchronous DMA request in stop mode for channel 23
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 23
#1 : 1
Enable asynchronous DMA request for channel 23
End of enumeration elements list.
EDREQ_24 : Enable asynchronous DMA request in stop mode for channel 24
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 24
#1 : 1
Enable asynchronous DMA request for channel 24
End of enumeration elements list.
EDREQ_25 : Enable asynchronous DMA request in stop mode for channel 25
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 25
#1 : 1
Enable asynchronous DMA request for channel 25
End of enumeration elements list.
EDREQ_26 : Enable asynchronous DMA request in stop mode for channel 26
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 26
#1 : 1
Enable asynchronous DMA request for channel 26
End of enumeration elements list.
EDREQ_27 : Enable asynchronous DMA request in stop mode for channel 27
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 27
#1 : 1
Enable asynchronous DMA request for channel 27
End of enumeration elements list.
EDREQ_28 : Enable asynchronous DMA request in stop mode for channel 28
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 28
#1 : 1
Enable asynchronous DMA request for channel 28
End of enumeration elements list.
EDREQ_29 : Enable asynchronous DMA request in stop mode for channel 29
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 29
#1 : 1
Enable asynchronous DMA request for channel 29
End of enumeration elements list.
EDREQ_30 : Enable asynchronous DMA request in stop mode for channel 30
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 30
#1 : 1
Enable asynchronous DMA request for channel 30
End of enumeration elements list.
EDREQ_31 : Enable asynchronous DMA request in stop mode for channel 31
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable asynchronous DMA request for channel 31
#1 : 1
Enable asynchronous DMA request for channel 31
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x506 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x50C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x50D4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x50DE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x50E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x50E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x50E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x50FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x5110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x5124 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x512E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x512E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x5138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x514C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x5156 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x5156 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x60A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x6140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x6158 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x6164 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x6170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x6170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x6170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x6188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x61A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x61B8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x61C4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x61C4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x61D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x61E8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x61F4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x61F4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x70F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x71E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x71FC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x720A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x7218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x7218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x7218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x7234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x7250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x726C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x727A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x727A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x7288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x72A4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x72B2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x72B2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x815 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x82A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x82C0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x82D0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x82E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x82E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x82E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x8300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x8320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x8340 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x8350 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x8350 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x8360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x8380 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x8390 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x8390 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel n Priority Register
address_offset : 0x91C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0x9380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0x93A4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0x93B6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0x93C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0x93C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0x93C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0x93EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0x9410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0x9434 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x9446 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x9446 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0x9458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0x947C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0x948E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0x948E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel n Priority Register
address_offset : 0xA24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0xA480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0xA4A8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0xA4BC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0xA4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0xA4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0xA4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0xA4F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0xA520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0xA548 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0xA55C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0xA55C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0xA570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0xA598 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0xA5AC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0xA5AC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel n Priority Register
address_offset : 0xB2D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0xB5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0xB5CC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0xB5E2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0xB5F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0xB5F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0xB5F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0xB624 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0xB650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0xB67C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0xB692 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0xB692 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0xB6A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0xB6D4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0xB6EA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0xB6EA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Enable Request Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERQ0 : Enable DMA Request 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ1 : Enable DMA Request 1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ2 : Enable DMA Request 2
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ3 : Enable DMA Request 3
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ4 : Enable DMA Request 4
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ5 : Enable DMA Request 5
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ6 : Enable DMA Request 6
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ7 : Enable DMA Request 7
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ8 : Enable DMA Request 8
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ9 : Enable DMA Request 9
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ10 : Enable DMA Request 10
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ11 : Enable DMA Request 11
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ12 : Enable DMA Request 12
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ13 : Enable DMA Request 13
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ14 : Enable DMA Request 14
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ15 : Enable DMA Request 15
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ16 : Enable DMA Request 16
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ17 : Enable DMA Request 17
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ18 : Enable DMA Request 18
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ19 : Enable DMA Request 19
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ20 : Enable DMA Request 20
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ21 : Enable DMA Request 21
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ22 : Enable DMA Request 22
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ23 : Enable DMA Request 23
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ24 : Enable DMA Request 24
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ25 : Enable DMA Request 25
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ26 : Enable DMA Request 26
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ27 : Enable DMA Request 27
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ28 : Enable DMA Request 28
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ29 : Enable DMA Request 29
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ30 : Enable DMA Request 30
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
ERQ31 : Enable DMA Request 31
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The DMA request signal for the corresponding channel is disabled
#1 : 1
The DMA request signal for the corresponding channel is enabled
End of enumeration elements list.
Channel n Priority Register
address_offset : 0xC37 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0xC6E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0xC710 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0xC728 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0xC740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0xC740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0xC740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0xC770 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0xC7A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0xC7D0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0xC7E8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0xC7E8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0xC800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0xC830 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0xC848 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0xC848 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel n Priority Register
address_offset : 0xD42 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0xD840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0xD874 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0xD88E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0xD8A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0xD8A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0xD8A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0xD8DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0xD910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0xD944 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0xD95E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0xD95E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0xD978 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0xD9AC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0xD9C6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0xD9C6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel n Priority Register
address_offset : 0xE4E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0xE9C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0xE9F8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0xEA14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0xEA30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0xEA30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0xEA30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0xEA68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0xEAA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0xEAD8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0xEAF4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0xEAF4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0xEB10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0xEB48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0xEB64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0xEB64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Channel n Priority Register
address_offset : 0xF5B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPRI : Channel n Arbitration Priority
bits : 0 - 3 (4 bit)
access : read-write
GRPPRI : Channel n Current Group Priority
bits : 4 - 5 (2 bit)
access : read-only
DPA : Disable Preempt Ability.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n can suspend a lower priority channel.
#1 : 1
Channel n cannot suspend any channel, regardless of channel priority.
End of enumeration elements list.
ECP : Enable Channel Preemption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n cannot be suspended by a higher priority channel's service request.
#1 : 1
Channel n can be temporarily suspended by the service request of a higher priority channel.
End of enumeration elements list.
TCD Source Address
address_offset : 0xFB60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : Source Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Source Address Offset
address_offset : 0xFB9C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFF : Source address signed offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Transfer Attributes
address_offset : 0xFBBA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSIZE : Destination data transfer size
bits : 0 - 2 (3 bit)
access : read-write
DMOD : Destination Address Modulo
bits : 3 - 7 (5 bit)
access : read-write
SSIZE : Source data transfer size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
8-bit
#001 : 001
16-bit
#010 : 010
32-bit
#100 : 100
16-byte burst
#101 : 101
32-byte burst
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 11 - 15 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Source address modulo feature is disabled
End of enumeration elements list.
TCD Minor Byte Count (Minor Loop Mapping Disabled)
address_offset : 0xFBD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
address_offset : 0xFBD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 29 (30 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
address_offset : 0xFBD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
NBYTES : Minor Byte Transfer Count
bits : 0 - 9 (10 bit)
access : read-write
MLOFF : If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
bits : 10 - 29 (20 bit)
access : read-write
DMLOE : Destination Minor Loop Offset enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the DADDR
#1 : 1
The minor loop offset is applied to the DADDR
End of enumeration elements list.
SMLOE : Source Minor Loop Offset Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minor loop offset is not applied to the SADDR
#1 : 1
The minor loop offset is applied to the SADDR
End of enumeration elements list.
TCD Last Source Address Adjustment
address_offset : 0xFC14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLAST : Last Source Address Adjustment
bits : 0 - 31 (32 bit)
access : read-write
TCD Destination Address
address_offset : 0xFC50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : Destination Address
bits : 0 - 31 (32 bit)
access : read-write
TCD Signed Destination Address Offset
address_offset : 0xFC8C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOFF : Destination Address Signed Offset
bits : 0 - 15 (16 bit)
access : read-write
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0xFCAA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0xFCAA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
CITER : Current Major Iteration Count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Minor Loop Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enable channel-to-channel linking on minor-loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Last Destination Address Adjustment/Scatter Gather Address
address_offset : 0xFCC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLASTSGA : Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)
bits : 0 - 31 (32 bit)
access : read-write
TCD Control and Status
address_offset : 0xFD04 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Channel Start
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel is not explicitly started.
#1 : 1
The channel is explicitly started via a software initiated service request.
End of enumeration elements list.
INTMAJOR : Enable an interrupt when major iteration count completes.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The end-of-major loop interrupt is disabled.
#1 : 1
The end-of-major loop interrupt is enabled.
End of enumeration elements list.
INTHALF : Enable an interrupt when major counter is half complete.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The half-point interrupt is disabled.
#1 : 1
The half-point interrupt is enabled.
End of enumeration elements list.
DREQ : Disable Request
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel's ERQ bit is not affected.
#1 : 1
The channel's ERQ bit is cleared when the major loop is complete.
End of enumeration elements list.
ESG : Enable Scatter/Gather Processing
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current channel's TCD is normal format.
#1 : 1
The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
End of enumeration elements list.
MAJORELINK : Enable channel-to-channel linking on major loop complete
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled.
#1 : 1
The channel-to-channel linking is enabled.
End of enumeration elements list.
ACTIVE : Channel Active
bits : 6 - 6 (1 bit)
access : read-write
DONE : Channel Done
bits : 7 - 7 (1 bit)
access : read-write
MAJORLINKCH : Major Loop Link Channel Number
bits : 8 - 12 (5 bit)
access : read-write
BWC : Bandwidth Control
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
No eDMA engine stalls.
#10 : 10
eDMA engine stalls for 4 cycles after each R/W.
#11 : 11
eDMA engine stalls for 8 cycles after each R/W.
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
address_offset : 0xFD22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting Major Iteration Count
bits : 0 - 14 (15 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
address_offset : 0xFD22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DMA
reset_Mask : 0x0
BITER : Starting major iteration count
bits : 0 - 8 (9 bit)
access : read-write
LINKCH : Link Channel Number
bits : 9 - 13 (5 bit)
access : read-write
ELINK : Enables channel-to-channel linking on minor loop complete
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel-to-channel linking is disabled
#1 : 1
The channel-to-channel linking is enabled
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.