Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :
Status and Control Register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCH : Input Channel Select
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
#10110 : 10110
Temperature Sensor
#10111 : 10111
Bandgap
#11101 : 11101
VREFH
#11110 : 11110
VREFL
#11111 : 11111
Module disabled Reset FIFO in FIFO mode.
End of enumeration elements list.
ADCO : Continuous Conversion Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
One conversion following a write to the ADC_SC1 when software triggered operation is selected, or one conversion following assertion of ADHWT when hardware triggered operation is selected. When the FIFO function is enabled (AFDEP > 0), a set of conversions are triggered.
#1 : 1
Continuous conversions are initiated following a write to ADC_SC1 when software triggered operation is selected. Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected. When the FIFO function is enabled (AFDEP > 0), a set of conversions are loop triggered.
End of enumeration elements list.
AIEN : Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion complete interrupt disabled.
#1 : 1
Conversion complete interrupt enabled.
End of enumeration elements list.
COCO : Conversion Complete Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Conversion not completed.
#1 : 1
Conversion completed.
End of enumeration elements list.
RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only
Conversion Result Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADR : Conversion Result
bits : 0 - 11 (12 bit)
access : read-only
RESERVED : no description available
bits : 12 - 31 (20 bit)
access : read-only
Compare Value Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CV : Conversion Result[11:0]
bits : 0 - 11 (12 bit)
access : read-write
RESERVED : no description available
bits : 12 - 31 (20 bit)
access : read-only
Pin Control 1 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADPC : ADC Pin Control
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
#0 : 0
ADx pin I/O control enabled.
#1 : 1
ADx pin I/O control disabled.
End of enumeration elements list.
Status and Control Register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFSEL : Voltage Reference Selection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
Default voltage reference pin pair (VREFH/VREFL).
#01 : 01
Analog supply pin pair (VDDA/VSSA).
#11 : 11
Reserved - Selects default voltage reference (VREFH/VREFL) pin pair.
#10 : 10
Reserved.
End of enumeration elements list.
FFULL : Result FIFO full
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Indicates that ADC result FIFO is not full and next conversion data still can be stored into FIFO.
#1 : 1
Indicates that ADC result FIFO is full and next conversion will override old data in case of no read action.
End of enumeration elements list.
FEMPTY : Result FIFO empty
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
Indicates that ADC result FIFO have at least one valid new data.
#1 : 1
Indicates that ADC result FIFO have no valid new data.
End of enumeration elements list.
ACFGT : Compare Function Greater Than Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare triggers when input is less than compare level.
#1 : 1
Compare triggers when input is greater than or equal to compare level.
End of enumeration elements list.
ACFE : Compare Function Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare function disabled.
#1 : 1
Compare function enabled.
End of enumeration elements list.
ADTRG : Conversion Trigger Select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Software trigger selected.
#1 : 1
Hardware trigger selected.
End of enumeration elements list.
ADACT : Conversion Active
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Conversion not in progress.
#1 : 1
Conversion in progress.
End of enumeration elements list.
RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only
Status and Control Register 3
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADICLK : Input Clock Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
Bus clock
#01 : 01
Bus clock divided by 2
#10 : 10
Alternate clock (ALTCLK)
#11 : 11
Asynchronous clock (ADACK)
End of enumeration elements list.
MODE : Conversion Mode Selection
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
8-bit conversion (N = 8)
#01 : 01
10-bit conversion (N = 10)
#10 : 10
12-bit conversion (N = 12)
#11 : 11
Reserved
End of enumeration elements list.
ADLSMP : Long Sample Time Configuration
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Short sample time.
#1 : 1
Long sample time.
End of enumeration elements list.
ADIV : Clock Divide Select
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
#00 : 00
Divide ration = 1, and clock rate = Input clock.
#01 : 01
Divide ration = 2, and clock rate = Input clock * 2.
#10 : 10
Divide ration = 3, and clock rate = Input clock * 4.
#11 : 11
Divide ration = 4, and clock rate = Input clock * 8.
End of enumeration elements list.
ADLPC : Low-Power Configuration
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
High speed configuration.
#1 : 1
Low power configuration:The power is reduced at the expense of maximum clock speed.
End of enumeration elements list.
RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only
Status and Control Register 4
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AFDEP : no description available
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 000
FIFO is disabled.
#001 : 001
2-level FIFO is enabled.
#010 : 010
3-level FIFO is enabled..
#011 : 011
4-level FIFO is enabled.
#100 : 100
5-level FIFO is enabled.
#101 : 101
6-level FIFO is enabled.
#110 : 110
7-level FIFO is enabled.
#111 : 111
8-level FIFO is enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 3 - 4 (2 bit)
access : read-only
ACFSEL : no description available
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
OR all of compare trigger.
#1 : 1
AND all of compare trigger.
End of enumeration elements list.
ASCANE : FIFO Scan Mode Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
FIFO scan mode disabled.
#1 : 1
FIFO scan mode enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 7 - 31 (25 bit)
access : read-only
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