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SPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

Registers

C1

C2

BR

S

D

M


C1

SPI control register 1
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1 C1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LSBFE SSOE CPHA CPOL MSTR SPTIE SPE SPIE

LSBFE : LSB first (shifter direction)
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI serial data transfers start with most significant bit

#1 : 1

SPI serial data transfers start with least significant bit

End of enumeration elements list.

SSOE : Slave select output enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input.

#1 : 1

When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input.

End of enumeration elements list.

CPHA : Clock phase
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

First edge on SPSCK occurs at the middle of the first cycle of a data transfer

#1 : 1

First edge on SPSCK occurs at the start of the first cycle of a data transfer

End of enumeration elements list.

CPOL : Clock polarity
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Active-high SPI clock (idles low)

#1 : 1

Active-low SPI clock (idles high)

End of enumeration elements list.

MSTR : Master/slave mode select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI module configured as a slave SPI device

#1 : 1

SPI module configured as a master SPI device

End of enumeration elements list.

SPTIE : SPI transmit interrupt enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts from SPTEF inhibited (use polling)

#1 : 1

When SPTEF is 1, hardware interrupt requested

End of enumeration elements list.

SPE : SPI system enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI system inactive

#1 : 1

SPI system enabled

End of enumeration elements list.

SPIE : SPI interrupt enable: for SPRF and MODF
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts from SPRF and MODF are inhibited-use polling

#1 : 1

Request a hardware interrupt when SPRF or MODF is 1

End of enumeration elements list.


C2

SPI control register 2
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2 C2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SPC0 SPISWAI RESERVED BIDIROE MODFEN RESERVED RESERVED SPMIE

SPC0 : SPI pin control 0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in.

#1 : 1

SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI.

End of enumeration elements list.

SPISWAI : SPI stop in wait mode
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI clocks continue to operate in wait mode

#1 : 1

SPI clocks stop when the MCU enters wait mode

End of enumeration elements list.

RESERVED : no description available
bits : 2 - 2 (1 bit)
access : read-only

BIDIROE : Bidirectional mode output enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Output driver disabled so SPI data I/O pin acts as an input

#1 : 1

SPI I/O pin enabled as an output

End of enumeration elements list.

MODFEN : Master mode-fault function enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI

#1 : 1

Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output

End of enumeration elements list.

RESERVED : no description available
bits : 5 - 5 (1 bit)
access : read-only

RESERVED : no description available
bits : 6 - 6 (1 bit)
access : read-only

SPMIE : SPI match interrupt enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupts from SPMF inhibited (use polling)

#1 : 1

When SPMF is 1, requests a hardware interrupt

End of enumeration elements list.


BR

SPI baud rate register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BR BR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SPR SPPR RESERVED

SPR : SPI baud rate divisor
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Baud rate divisor is 2

#0001 : 0001

Baud rate divisor is 4

#0010 : 0010

Baud rate divisor is 8

#0011 : 0011

Baud rate divisor is 16

#0100 : 0100

Baud rate divisor is 32

#0101 : 0101

Baud rate divisor is 64

#0110 : 0110

Baud rate divisor is 128

#0111 : 0111

Baud rate divisor is 256

#1000 : 1000

Baud rate divisor is 512

End of enumeration elements list.

SPPR : SPI baud rate prescale divisor
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#000 : 000

Baud rate prescaler divisor is 1

#001 : 001

Baud rate prescaler divisor is 2

#010 : 010

Baud rate prescaler divisor is 3

#011 : 011

Baud rate prescaler divisor is 4

#100 : 100

Baud rate prescaler divisor is 5

#101 : 101

Baud rate prescaler divisor is 6

#110 : 110

Baud rate prescaler divisor is 7

#111 : 111

Baud rate prescaler divisor is 8

End of enumeration elements list.

RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only


S

SPI status register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

S S read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RESERVED MODF SPTEF SPMF SPRF

RESERVED : no description available
bits : 0 - 3 (4 bit)
access : read-only

MODF : Master mode fault flag
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

No mode fault error

#1 : 1

Mode fault error detected

End of enumeration elements list.

SPTEF : SPI transmit buffer empty flag
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

SPI transmit buffer not empty

#1 : 1

SPI transmit buffer empty

End of enumeration elements list.

SPMF : SPI match flag
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Value in the receive data buffer does not match the value in the M register

#1 : 1

Value in the receive data buffer matches the value in the M register

End of enumeration elements list.

SPRF : SPI read buffer full flag
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

No data available in the receive data buffer

#1 : 1

Data available in the receive data buffer

End of enumeration elements list.


D

SPI data register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

D D read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 Bits

Bits : Data (low byte)
bits : 0 - 7 (8 bit)
access : read-write


M

SPI match register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

M M read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 Bits

Bits : Hardware compare value (low byte)
bits : 0 - 7 (8 bit)
access : read-write



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