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address_offset : 0x0 Bytes (0x0)
size : 0xD byte (0x0)
mem_usage : registers
protection : not protected
Flash Clock Divider Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FDIV : Clock Divider Bits
bits : 0 - 5 (6 bit)
access : read-write
FDIVLCK : Clock Divider Locked
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
FDIV field is open for writing.
#1 : 1
FDIV value is locked and cannot be changed. After the lock bit is set high, only reset can clear this bit and restore writability to the FDIV field in user mode.
End of enumeration elements list.
FDIVLD : Clock Divider Loaded
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
FCLKDIV register has not been written since the last reset.
#1 : 1
FCLKDIV register has been written since the last reset.
End of enumeration elements list.
Flash Security Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC : Flash Security Bits
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
#00 : 00
Secured
#01 : 01
Secured
#10 : 10
Unsecured
#11 : 11
Secured
End of enumeration elements list.
KEYEN : Backdoor Key Security Enable Bits
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
#00 : 00
Disabled
#01 : 01
Disabled
#10 : 10
Enabled
#11 : 11
Disabled
End of enumeration elements list.
Flash CCOB Index Register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCOBIX : Common Command Register Index
bits : 0 - 2 (3 bit)
access : read-write
Flash Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSFD : Force Single Bit Fault Detect
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected.
#1 : 1
Flash array read operation will force the SFDIF flag in the FERSTAT register to be set and an interrupt will be generated as long as FERCNFG[SFDIE] is set.
End of enumeration elements list.
FDFD : Force Double Bit Fault Detect
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash array read operations will set the FERSTAT[DFDIF] flag only if a double bit fault is detected.
#1 : 1
Any flash array read operation will force the FERSTAT[DFDIF] flag to be set and an interrupt will be generated as long as FERCNFG[DFDIE] is set.
End of enumeration elements list.
IGNSF : Ignore Single Bit Fault
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
All single-bit faults detected during array reads are reported.
#1 : 1
Single-bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated.
End of enumeration elements list.
CCIE : Command Complete Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Command complete interrupt is disabled.
#1 : 1
An interrupt will be requested whenever the CCIF flag in the FSTAT register is set.
End of enumeration elements list.
Flash Error Configuration Register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFDIE : Single Bit Fault Detect Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SFDIF interrupt is disabled whenever the SFDIF flag is set.
#1 : 1
An interrupt will be requested whenever the SFDIF flag is set.
End of enumeration elements list.
DFDIE : Double Bit Fault Detect Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
DFDIF interrupt is disabled.
#1 : 1
An interrupt will be requested whenever the DFDIF flag is set.
End of enumeration elements list.
Flash Status Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MGSTAT : Memory Controller Command Completion Status Flag
bits : 0 - 1 (2 bit)
access : read-only
MGBUSY : Memory Controller Busy Flag
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
Memory controller is idle.
#1 : 1
Memory controller is busy executing a flash command (CCIF = 0).
End of enumeration elements list.
FPVIOL : Flash Protection Violation Flag
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No protection violation is detected.
#1 : 1
Protection violation is detected.
End of enumeration elements list.
ACCERR : Flash Access Error Flag
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No access error is detected.
#1 : 1
Access error is detected.
End of enumeration elements list.
CCIF : Command Complete Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash command is in progress.
#1 : 1
Flash command has completed.
End of enumeration elements list.
Flash Error Status Register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SFDIF : Single Bit Fault Detect Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No single bit fault detected.
#1 : 1
Single bit fault detected and corrected or a flash array read operation returning invalid data was attempted while command running.
End of enumeration elements list.
DFDIF : Double Bit Fault Detect Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No double bit fault detected.
#1 : 1
Double bit fault detected or a flash array read operation returning invalid data was attempted while command running.
End of enumeration elements list.
Flash Protection Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPLS : Flash Protection Lower Address Size
bits : 0 - 1 (2 bit)
access : read-write
FPLDIS : Flash Protection Lower Address Range Disable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Protection/Unprotection enabled.
#1 : 1
Protection/Unprotection disabled.
End of enumeration elements list.
FPHS : Flash Protection Higher Address Size
bits : 3 - 4 (2 bit)
access : read-write
FPHDIS : Flash Protection Higher Address Range Disable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Protection/Unprotection enabled.
#1 : 1
Protection/Unprotection disabled.
End of enumeration elements list.
RNV6 : Reserved Nonvolatile Bit
bits : 6 - 6 (1 bit)
access : read-only
FPOPEN : Flash Protection Operation Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
When FPOPEN is clear, the FPHDIS and FPLDIS fields define unprotected address ranges as specified by the corresponding FPHS and FPLS fields.
#1 : 1
When FPOPEN is set, the FPHDIS and FPLDIS fields enable protection for the address range specified by the corresponding FPHS and FPLS fields.
End of enumeration elements list.
EEPROM Protection Register
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPS : EEPROM Protection Size
bits : 0 - 2 (3 bit)
access : read-write
DPOPEN : EEPROM Protection Control
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enables EEPROM memory protection from program and erase with protected address range defined by DPS bits.
#1 : 1
Disables EEPROM memory protection from program and erase.
End of enumeration elements list.
Flash Common Command Object Register:High
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCOB : Common Command Object Bit 15:8
bits : 0 - 7 (8 bit)
access : read-write
Flash Common Command Object Register: Low
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCOB : Common Command Object Bit 7:0
bits : 0 - 7 (8 bit)
access : read-write
Flash Option Register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NV : Nonvolatile Bits
bits : 0 - 7 (8 bit)
access : read-only
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