Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
System Reset Status and ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LVD : Low Voltage Detect
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset is not caused by LVD trip or POR.
#1 : 1
Reset is caused by LVD trip or POR.
End of enumeration elements list.
LOC : Internal Clock Source Module Reset
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset is not caused by the ICS module.
#1 : 1
Reset is caused by the ICS module.
End of enumeration elements list.
WDOG : Watchdog (WDOG)
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset is not caused by WDOG timeout.
#1 : 1
Reset is caused by WDOG timeout.
End of enumeration elements list.
PIN : External Reset Pin
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset is not caused by external reset pin.
#1 : 1
Reset came from external reset pin.
End of enumeration elements list.
POR : Power-On Reset
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset not caused by POR.
#1 : 1
POR caused reset.
End of enumeration elements list.
LOCKUP : Core Lockup
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset is not caused by core LOCKUP event.
#1 : 1
Reset is caused by core LOCKUP event.
End of enumeration elements list.
SW : Software
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset is not caused by software setting of SYSRESETREQ bit.
#1 : 1
Reset caused by software setting of SYSRESETREQ bit
End of enumeration elements list.
MDMAP : MDM-AP System Reset Request
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset is not caused by host debugger system setting of the System Reset Request bit.
#1 : 1
Reset is caused by host debugger system setting of the System Reset Request bit.
End of enumeration elements list.
SACKERR : Stop Mode Acknowledge Error Reset
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset is not caused by peripheral failure to acknowledge attempt to enter Stop mode.
#1 : 1
Reset is caused by peripheral failure to acknowledge attempt to enter Stop mode.
End of enumeration elements list.
PINID : Device Pin ID
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
#0000 : 0000
8-pin
#0001 : 0001
16-pin
#0010 : 0010
20-pin
#0011 : 0011
24-pin
#0100 : 0100
32-pin
#0101 : 0101
44-pin
#0110 : 0110
48-pin
#0111 : 0111
64-pin
#1000 : 1000
80-pin
#1010 : 1010
100-pin
End of enumeration elements list.
RevID : Device Revision Number
bits : 20 - 23 (4 bit)
access : read-only
SUBFAMID : Kinetis sub-family ID
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
#0010 : 0010
KEx2 sub-family
End of enumeration elements list.
FAMID : Kinetis family ID
bits : 28 - 31 (4 bit)
access : read-only
Enumeration:
#0000 : 0000
KE0x family.
End of enumeration elements list.
Universally Unique Identifier Low Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : Universally Unique Identifier
bits : 0 - 31 (32 bit)
access : read-only
Universally Unique Identifier High Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : Universally Unique Identifier
bits : 0 - 31 (32 bit)
access : read-only
BUS Clock Divider Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUSDIV : BUS Clock Divider
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock is same as ICSOUTCLK.
#1 : 1
Bus clock is ICSOUTCLK divided by 2.
End of enumeration elements list.
System Options Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMIE : NMI Pin Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PTB4/FTM2_CH4/SPI0_MISO/NMI/ACMP1_IN2 pin functions as PTB4, FTM2_CH4, SPI0_MISO, or ACMP1_IN2.
#1 : 1
PTB4/FTM2_CH4/SPI0_MISO/NMI/ACMP1_IN2 pin functions as NMI.
End of enumeration elements list.
RSTPE : RESET Pin Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PTA5/IRQ/FTM0_CLK/RESET pin functions as PTA5, IRQ, or FTM0_CLK.
#1 : 1
PTA5/IRQ/FTM0_CLK/RESET pin functions as RESET.
End of enumeration elements list.
SWDE : Single Wire Debug Port Pin Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PTA4/ACMP0_OUT/SWD_DIO as PTA4 or ACMP0_OUT function, PTC4/RTCO/FTM1_CH0/ACMP0_IN2/SWD_CLK as PTC4, RTCO, FTM1_CH0, or ACMP0_IN2 function.
#1 : 1
PTA4/ACMP0_OUT/SWD_DIO as SWD_DIO function, PTC4/RTCO/FTM1CH0/ACMP0_IN2/SWD_CLK as SWD_CLK function.
End of enumeration elements list.
ADHWT : ADC Hardware Trigger Source
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
RTC overflow as the ADC hardware trigger
#01 : 01
PIT overflow as the ADC hardware trigger
#10 : 10
FTM2 init trigger with 8-bit programmable delay
#11 : 11
FTM2 match trigger with 8-bit programmable delay
End of enumeration elements list.
RTCC : Real-Time Counter Capture
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC overflow is not connected to FTM1 input channel 1.
#1 : 1
RTC overflow is connected to FTM1 input channel 1.
End of enumeration elements list.
ACIC : Analog Comparator to Input Capture Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP0 output is not connected to FTM1 input channel 0.
#1 : 1
ACMP0 output is connected to FTM1 input channel 0.
End of enumeration elements list.
RXDCE : UART0_RX Capture Select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0_RX input signal is connected to the UART0 module only.
#1 : 1
UART0_RX input signal is connected to the UART0 module and FTM0 channel 1.
End of enumeration elements list.
RXDFE : UART0_RX Filter Select
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0_RX input signal is connected to UART0 module directly.
#1 : 1
UART0_RX input signal is filtered by ACMP, then injected to UART0.
End of enumeration elements list.
FTMSYNC : FTM2 Synchronization Select
bits : 14 - 14 (1 bit)
access : write-only
Enumeration:
#0 : 0
No synchronization triggered.
#1 : 1
Generates a PWM synchronization trigger to the FTM2 modules.
End of enumeration elements list.
TXDME : UART0_TX Modulation Select
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0_TX output is connected to pinout directly.
#1 : 1
UART0_TX output is modulated by FTM0 channel 0 before mapped to pinout.
End of enumeration elements list.
BUSREF : BUS Clock Output select
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 000
Bus
#001 : 001
Bus divided by 2
#010 : 010
Bus divided by 4
#011 : 011
Bus divided by 8
#100 : 100
Bus divided by 16
#101 : 101
Bus divided by 32
#110 : 110
Bus divided by 64
#111 : 111
Bus divided by 128
End of enumeration elements list.
CLKOE : Bus Clock Output Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock output is disabled on PTH2.
#1 : 1
Bus clock output is enabled on PTH2.
End of enumeration elements list.
DLYACT : FTM2 Trigger Delay Active
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
The delay is inactive.
#1 : 1
The delay is active.
End of enumeration elements list.
DELAY : FTM2 Trigger Delay
bits : 24 - 31 (8 bit)
access : read-write
Pin Selection Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTCPS : RTCO Pin Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTCO is mapped on PTC4.
#1 : 1
RTCO is mapped on PTC5.
End of enumeration elements list.
I2C0PS : I2C0 Port Pin Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C0_SCL and I2C0_SDA are mapped on PTA3 and PTA2, respectively.
#1 : 1
I2C0_SCL and I2C0_SDA are mapped on PTB7 and PTB6, respectively.
End of enumeration elements list.
SPI0PS : SPI0 Pin Select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI0_SCK, SPI0_MOSI, SPI0_MISO, and SPI0_PCS0 are mapped on PTB2, PTB3, PTB4, and PTB5.
#1 : 1
SPI0_SCK, SPI0_MOSI, SPI0_MISO, and SPI0_PCS0 are mapped on PTE0, PTE1, PTE2, and PTE3.
End of enumeration elements list.
UART0PS : UART0 Pin Select
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0_RX and UART0_TX are mapped on PTB0 and PTB1.
#1 : 1
UART0_RX and UART0_TX are mapped on PTA2 and PTA3.
End of enumeration elements list.
FTM0PS0 : FTM0_CH0 Port Pin Select
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM0_CH0 channels are mapped on PTA0.
#1 : 1
FTM0_CH0 channels are mapped on PTB2.
End of enumeration elements list.
FTM0PS1 : FTM0_CH1 Port Pin Select
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM0_CH1 channels are mapped on PTA1.
#1 : 1
FTM0_CH1 channels are mapped on PTB3.
End of enumeration elements list.
FTM1PS0 : FTM1_CH0 Port Pin Select
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM1_CH0 channels are mapped on PTC4.
#1 : 1
FTM1_CH0 channels are mapped on PTH2.
End of enumeration elements list.
FTM1PS1 : FTM1_CH1 Port Pin Select
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM1_CH1 channels are mapped on PTC5.
#1 : 1
FTM1_CH1 channels are mapped on PTE7.
End of enumeration elements list.
FTM2PS0 : FTM2_CH0 Port Pin Select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM2_CH0 channels are mapped on PTC0.
#1 : 1
FTM2_CH0 channels are mapped on PTH0.
End of enumeration elements list.
FTM2PS1 : FTM2_CH1 Port Pin Select
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM2_CH1 channels are mapped on PTC1.
#1 : 1
FTM2_CH1 channels are mapped on PTH1.
End of enumeration elements list.
FTM2PS2 : FTM2_CH2 Port Pin Select
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM2_CH2 channels are mapped on PTC2.
#1 : 1
FTM2_CH2 channels are mapped on PTD0.
End of enumeration elements list.
FTM2PS3 : FTM2_CH3 Port Pin Select
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM2_CH3 channels are mapped on PTC3.
#1 : 1
FTM2_CH3 channels are mapped on PTD1.
End of enumeration elements list.
System Clock Gating Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC : RTC Clock Gate Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock to the RTC module is disabled.
#1 : 1
Bus clock to the RTC module is enabled.
End of enumeration elements list.
PIT : PIT Clock Gate Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock to the PIT module is disabled.
#1 : 1
Bus clock to the PIT module is enabled.
End of enumeration elements list.
FTM0 : FTM0 Clock Gate Control
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock to the FTM0 module is disabled.
#1 : 1
Bus clock to the FTM0 module is enabled.
End of enumeration elements list.
FTM1 : FTM1 Clock Gate Control
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock to the FTM1 module is disabled.
#1 : 1
Bus clock to the FTM1 module is enabled.
End of enumeration elements list.
FTM2 : FTM2 Clock Gate Control
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock to the FTM2 module is disabled.
#1 : 1
Bus clock to the FTM2 module is enabled.
End of enumeration elements list.
CRC : CRC Clock Gate Control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock to the CRC module is disabled.
#1 : 1
Bus clock to the CRC module is enabled.
End of enumeration elements list.
FLASH : Flash Clock Gate Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock to the flash module is disabled.
#1 : 1
Bus clock to the flash module is enabled.
End of enumeration elements list.
SWD : SWD (single wire debugger) Clock Gate Control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock to the SWD module is disabled.
#1 : 1
Bus clock to the SWD module is enabled.
End of enumeration elements list.
I2C : I2C Clock Gate Control
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock to the IIC module is disabled.
#1 : 1
Bus clock to the IIC module is enabled.
End of enumeration elements list.
SPI0 : SPI0 Clock Gate Control
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock to the SPI0 module is disabled.
#1 : 1
Bus clock to the SPI0 module is enabled.
End of enumeration elements list.
SPI1 : SPI1 Clock Gate Control
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock to the SPI1 module is disabled.
#1 : 1
Bus clock to the SPI1 module is enabled.
End of enumeration elements list.
UART0 : UART0 Clock Gate Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock to the UART0 module is disabled.
#1 : 1
Bus clock to the UART0 module is enabled.
End of enumeration elements list.
UART1 : UART1 Clock Gate Control
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock to the UART1 module is disabled.
#1 : 1
Bus clock to the UART1 module is enabled.
End of enumeration elements list.
UART2 : UART2 Clock Gate Control
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock to the UART2 module is disabled.
#1 : 1
Bus clock to the UART2 module is enabled.
End of enumeration elements list.
KBI0 : KBI0 Clock Gate Control
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock to the KBI0 module is disabled.
#1 : 1
Bus clock to the KBI0 module is enabled.
End of enumeration elements list.
KBI1 : KBI1 Clock Gate Control
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock to the KBI1 module is disabled.
#1 : 1
Bus clock to the KBI1 module is enabled.
End of enumeration elements list.
IRQ : IRQ Clock Gate Control
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock to the IRQ module is disabled.
#1 : 1
Bus clock to the IRQ module is enabled.
End of enumeration elements list.
ADC : ADC Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock to the ADC module is disabled.
#1 : 1
Bus clock to the ADC module is enabled.
End of enumeration elements list.
ACMP0 : ACMP0 Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock to the ACMP0 module is disabled.
#1 : 1
Bus clock to the ACMP0 module is enabled.
End of enumeration elements list.
ACMP1 : ACMP1 Clock Gate Control
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus clock to the ACMP1 module is disabled.
#1 : 1
Bus clock to the ACMP1 module is enabled.
End of enumeration elements list.
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