\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x0 Bytes (0x0)
size : 0x9C byte (0x0)
mem_usage : registers
protection : not protected
Status And Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Prescale Factor Selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 000
Divide by 1
#001 : 001
Divide by 2
#010 : 010
Divide by 4
#011 : 011
Divide by 8
#100 : 100
Divide by 16
#101 : 101
Divide by 32
#110 : 110
Divide by 64
#111 : 111
Divide by 128
End of enumeration elements list.
CLKS : Clock Source Selection
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 00
No clock selected. This in effect disables the FTM counter.
#01 : 01
System clock
#10 : 10
Fixed frequency clock
#11 : 11
External clock
End of enumeration elements list.
CPWMS : Center-Aligned PWM Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter operates in Up Counting mode.
#1 : 1
FTM counter operates in Up-Down Counting mode.
End of enumeration elements list.
TOIE : Timer Overflow Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable TOF interrupts. Use software polling.
#1 : 1
Enable TOF interrupts. An interrupt is generated when TOF equals one.
End of enumeration elements list.
TOF : Timer Overflow Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter has not overflowed.
#1 : 1
FTM counter has overflowed.
End of enumeration elements list.
Channel (n) Status And Control
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ELSA : Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel interrupts. Use software polling.
#1 : 1
Enable channel interrupts.
End of enumeration elements list.
CHF : Channel Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Status And Control
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ELSA : Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel interrupts. Use software polling.
#1 : 1
Enable channel interrupts.
End of enumeration elements list.
CHF : Channel Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Status And Control
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ELSA : Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel interrupts. Use software polling.
#1 : 1
Enable channel interrupts.
End of enumeration elements list.
CHF : Channel Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Status And Control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ELSA : Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel interrupts. Use software polling.
#1 : 1
Enable channel interrupts.
End of enumeration elements list.
CHF : Channel Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Counter
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Counter Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Status And Control
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ELSA : Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel interrupts. Use software polling.
#1 : 1
Enable channel interrupts.
End of enumeration elements list.
CHF : Channel Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
Counter Initial Value
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : Initial Value Of The FTM Counter
bits : 0 - 15 (16 bit)
access : read-write
Capture And Compare Status
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0F : Channel 0 Flag
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
CH1F : Channel 1 Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
CH2F : Channel 2 Flag
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
CH3F : Channel 3 Flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
CH4F : Channel 4 Flag
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
CH5F : Channel 5 Flag
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
CH6F : Channel 6 Flag
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
CH7F : Channel 7 Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
Features Mode Selection
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTMEN : FTM Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers.
#1 : 1
All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions.
End of enumeration elements list.
INIT : Initialize The Channels Output
bits : 1 - 1 (1 bit)
access : read-write
WPDIS : Write Protection Disable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Write protection is enabled.
#1 : 1
Write protection is disabled.
End of enumeration elements list.
PWMSYNC : PWM Synchronization Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.
#1 : 1
Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.
End of enumeration elements list.
CAPTEST : Capture Test Mode Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture test mode is disabled.
#1 : 1
Capture test mode is enabled.
End of enumeration elements list.
FAULTM : Fault Control Mode
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
#00 : 00
Fault control is disabled for all channels.
#01 : 01
Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
#10 : 10
Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
#11 : 11
Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
End of enumeration elements list.
FAULTIE : Fault Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault control interrupt is disabled.
#1 : 1
Fault control interrupt is enabled.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Synchronization
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTMIN : Minimum Loading Point Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minimum loading point is disabled.
#1 : 1
The minimum loading point is enabled.
End of enumeration elements list.
CNTMAX : Maximum Loading Point Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The maximum loading point is disabled.
#1 : 1
The maximum loading point is enabled.
End of enumeration elements list.
REINIT : FTM Counter Reinitialization By Synchronization (FTM counter synchronization)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter continues to count normally.
#1 : 1
FTM counter is updated with its initial value when the selected trigger is detected.
End of enumeration elements list.
SYNCHOM : Output Mask Synchronization
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.
#1 : 1
OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
End of enumeration elements list.
TRIG0 : PWM Synchronization Hardware Trigger 0
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trigger is disabled.
#1 : 1
Trigger is enabled.
End of enumeration elements list.
TRIG1 : PWM Synchronization Hardware Trigger 1
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trigger is disabled.
#1 : 1
Trigger is enabled.
End of enumeration elements list.
TRIG2 : PWM Synchronization Hardware Trigger 2
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trigger is disabled.
#1 : 1
Trigger is enabled.
End of enumeration elements list.
SWSYNC : PWM Synchronization Software Trigger
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Software trigger is not selected.
#1 : 1
Software trigger is selected.
End of enumeration elements list.
Initial State For Channels Output
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0OI : Channel 0 Output Initialization Value
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
CH1OI : Channel 1 Output Initialization Value
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
CH2OI : Channel 2 Output Initialization Value
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
CH3OI : Channel 3 Output Initialization Value
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
CH4OI : Channel 4 Output Initialization Value
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
CH5OI : Channel 5 Output Initialization Value
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
CH6OI : Channel 6 Output Initialization Value
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
CH7OI : Channel 7 Output Initialization Value
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
End of enumeration elements list.
Output Mask
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0OM : Channel 0 Output Mask
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH1OM : Channel 1 Output Mask
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH2OM : Channel 2 Output Mask
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH3OM : Channel 3 Output Mask
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH4OM : Channel 4 Output Mask
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH5OM : Channel 5 Output Mask
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH6OM : Channel 6 Output Mask
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH7OM : Channel 7 Output Mask
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
Function For Linked Channels
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMBINE0 : Combine Channels For n = 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channels (n) and (n+1) are independent.
#1 : 1
Channels (n) and (n+1) are combined.
End of enumeration elements list.
COMP0 : Complement Of Channel (n) For n = 0
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel (n+1) output is the same as the channel (n) output.
#1 : 1
The channel (n+1) output is the complement of the channel (n) output.
End of enumeration elements list.
DECAPEN0 : Dual Edge Capture Mode Enable For n = 0
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The Dual Edge Capture mode in this pair of channels is disabled.
#1 : 1
The Dual Edge Capture mode in this pair of channels is enabled.
End of enumeration elements list.
DECAP0 : Dual Edge Capture Mode Captures For n = 0
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The dual edge captures are inactive.
#1 : 1
The dual edge captures are active.
End of enumeration elements list.
DTEN0 : Deadtime Enable For n = 0
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The deadtime insertion in this pair of channels is disabled.
#1 : 1
The deadtime insertion in this pair of channels is enabled.
End of enumeration elements list.
SYNCEN0 : Synchronization Enable For n = 0
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWM synchronization in this pair of channels is disabled.
#1 : 1
The PWM synchronization in this pair of channels is enabled.
End of enumeration elements list.
FAULTEN0 : Fault Control Enable For n = 0
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault control in this pair of channels is disabled.
#1 : 1
The fault control in this pair of channels is enabled.
End of enumeration elements list.
COMBINE1 : Combine Channels For n = 2
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channels (n) and (n+1) are independent.
#1 : 1
Channels (n) and (n+1) are combined.
End of enumeration elements list.
COMP1 : Complement Of Channel (n) For n = 2
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel (n+1) output is the same as the channel (n) output.
#1 : 1
The channel (n+1) output is the complement of the channel (n) output.
End of enumeration elements list.
DECAPEN1 : Dual Edge Capture Mode Enable For n = 2
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The Dual Edge Capture mode in this pair of channels is disabled.
#1 : 1
The Dual Edge Capture mode in this pair of channels is enabled.
End of enumeration elements list.
DECAP1 : Dual Edge Capture Mode Captures For n = 2
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The dual edge captures are inactive.
#1 : 1
The dual edge captures are active.
End of enumeration elements list.
DTEN1 : Deadtime Enable For n = 2
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
The deadtime insertion in this pair of channels is disabled.
#1 : 1
The deadtime insertion in this pair of channels is enabled.
End of enumeration elements list.
SYNCEN1 : Synchronization Enable For n = 2
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWM synchronization in this pair of channels is disabled.
#1 : 1
The PWM synchronization in this pair of channels is enabled.
End of enumeration elements list.
FAULTEN1 : Fault Control Enable For n = 2
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault control in this pair of channels is disabled.
#1 : 1
The fault control in this pair of channels is enabled.
End of enumeration elements list.
COMBINE2 : Combine Channels For n = 4
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channels (n) and (n+1) are independent.
#1 : 1
Channels (n) and (n+1) are combined.
End of enumeration elements list.
COMP2 : Complement Of Channel (n) For n = 4
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel (n+1) output is the same as the channel (n) output.
#1 : 1
The channel (n+1) output is the complement of the channel (n) output.
End of enumeration elements list.
DECAPEN2 : Dual Edge Capture Mode Enable For n = 4
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
The Dual Edge Capture mode in this pair of channels is disabled.
#1 : 1
The Dual Edge Capture mode in this pair of channels is enabled.
End of enumeration elements list.
DECAP2 : Dual Edge Capture Mode Captures For n = 4
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
The dual edge captures are inactive.
#1 : 1
The dual edge captures are active.
End of enumeration elements list.
DTEN2 : Deadtime Enable For n = 4
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
The deadtime insertion in this pair of channels is disabled.
#1 : 1
The deadtime insertion in this pair of channels is enabled.
End of enumeration elements list.
SYNCEN2 : Synchronization Enable For n = 4
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWM synchronization in this pair of channels is disabled.
#1 : 1
The PWM synchronization in this pair of channels is enabled.
End of enumeration elements list.
FAULTEN2 : Fault Control Enable For n = 4
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault control in this pair of channels is disabled.
#1 : 1
The fault control in this pair of channels is enabled.
End of enumeration elements list.
COMBINE3 : Combine Channels For n = 6
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channels (n) and (n+1) are independent.
#1 : 1
Channels (n) and (n+1) are combined.
End of enumeration elements list.
COMP3 : Complement Of Channel (n) for n = 6
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel (n+1) output is the same as the channel (n) output.
#1 : 1
The channel (n+1) output is the complement of the channel (n) output.
End of enumeration elements list.
DECAPEN3 : Dual Edge Capture Mode Enable For n = 6
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
The Dual Edge Capture mode in this pair of channels is disabled.
#1 : 1
The Dual Edge Capture mode in this pair of channels is enabled.
End of enumeration elements list.
DECAP3 : Dual Edge Capture Mode Captures For n = 6
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
The dual edge captures are inactive.
#1 : 1
The dual edge captures are active.
End of enumeration elements list.
DTEN3 : Deadtime Enable For n = 6
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
The deadtime insertion in this pair of channels is disabled.
#1 : 1
The deadtime insertion in this pair of channels is enabled.
End of enumeration elements list.
SYNCEN3 : Synchronization Enable For n = 6
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWM synchronization in this pair of channels is disabled.
#1 : 1
The PWM synchronization in this pair of channels is enabled.
End of enumeration elements list.
FAULTEN3 : Fault Control Enable For n = 6
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault control in this pair of channels is disabled.
#1 : 1
The fault control in this pair of channels is enabled.
End of enumeration elements list.
Deadtime Insertion Control
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTVAL : Deadtime Value
bits : 0 - 5 (6 bit)
access : read-write
DTPS : Deadtime Prescaler Value
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#10 : 10
Divide the system clock by 4.
#11 : 11
Divide the system clock by 16.
End of enumeration elements list.
Channel (n) Status And Control
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ELSA : Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel interrupts. Use software polling.
#1 : 1
Enable channel interrupts.
End of enumeration elements list.
CHF : Channel Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
FTM External Trigger
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2TRIG : Channel 2 Trigger Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of the channel trigger is disabled.
#1 : 1
The generation of the channel trigger is enabled.
End of enumeration elements list.
CH3TRIG : Channel 3 Trigger Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of the channel trigger is disabled.
#1 : 1
The generation of the channel trigger is enabled.
End of enumeration elements list.
CH4TRIG : Channel 4 Trigger Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of the channel trigger is disabled.
#1 : 1
The generation of the channel trigger is enabled.
End of enumeration elements list.
CH5TRIG : Channel 5 Trigger Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of the channel trigger is disabled.
#1 : 1
The generation of the channel trigger is enabled.
End of enumeration elements list.
CH0TRIG : Channel 0 Trigger Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of the channel trigger is disabled.
#1 : 1
The generation of the channel trigger is enabled.
End of enumeration elements list.
CH1TRIG : Channel 1 Trigger Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of the channel trigger is disabled.
#1 : 1
The generation of the channel trigger is enabled.
End of enumeration elements list.
INITTRIGEN : Initialization Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of initialization trigger is disabled.
#1 : 1
The generation of initialization trigger is enabled.
End of enumeration elements list.
TRIGF : Channel Trigger Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel trigger was generated.
#1 : 1
A channel trigger was generated.
End of enumeration elements list.
Channels Polarity
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POL0 : Channel 0 Polarity
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
POL1 : Channel 1 Polarity
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
POL2 : Channel 2 Polarity
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
POL3 : Channel 3 Polarity
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
POL4 : Channel 4 Polarity
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
POL5 : Channel 5 Polarity
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
POL6 : Channel 6 Polarity
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
POL7 : Channel 7 Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
Fault Mode Status
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAULTF0 : Fault Detection Flag 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No fault condition was detected at the fault input.
#1 : 1
A fault condition was detected at the fault input.
End of enumeration elements list.
FAULTF1 : Fault Detection Flag 1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No fault condition was detected at the fault input.
#1 : 1
A fault condition was detected at the fault input.
End of enumeration elements list.
FAULTF2 : Fault Detection Flag 2
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No fault condition was detected at the fault input.
#1 : 1
A fault condition was detected at the fault input.
End of enumeration elements list.
FAULTF3 : Fault Detection Flag 3
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No fault condition was detected at the fault input.
#1 : 1
A fault condition was detected at the fault input.
End of enumeration elements list.
FAULTIN : Fault Inputs
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
The logic OR of the enabled fault inputs is 0.
#1 : 1
The logic OR of the enabled fault inputs is 1.
End of enumeration elements list.
WPEN : Write Protection Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Write protection is disabled. Write protected bits can be written.
#1 : 1
Write protection is enabled. Write protected bits cannot be written.
End of enumeration elements list.
FAULTF : Fault Detection Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No fault condition was detected.
#1 : 1
A fault condition was detected.
End of enumeration elements list.
Input Capture Filter Control
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0FVAL : Channel 0 Input Filter
bits : 0 - 3 (4 bit)
access : read-write
CH1FVAL : Channel 1 Input Filter
bits : 4 - 7 (4 bit)
access : read-write
CH2FVAL : Channel 2 Input Filter
bits : 8 - 11 (4 bit)
access : read-write
CH3FVAL : Channel 3 Input Filter
bits : 12 - 15 (4 bit)
access : read-write
Fault Control
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAULT0EN : Fault Input 0 Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input is disabled.
#1 : 1
Fault input is enabled.
End of enumeration elements list.
FAULT1EN : Fault Input 1 Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input is disabled.
#1 : 1
Fault input is enabled.
End of enumeration elements list.
FAULT2EN : Fault Input 2 Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input is disabled.
#1 : 1
Fault input is enabled.
End of enumeration elements list.
FAULT3EN : Fault Input 3 Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input is disabled.
#1 : 1
Fault input is enabled.
End of enumeration elements list.
FFLTR0EN : Fault Input 0 Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input filter is disabled.
#1 : 1
Fault input filter is enabled.
End of enumeration elements list.
FFLTR1EN : Fault Input 1 Filter Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input filter is disabled.
#1 : 1
Fault input filter is enabled.
End of enumeration elements list.
FFLTR2EN : Fault Input 2 Filter Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input filter is disabled.
#1 : 1
Fault input filter is enabled.
End of enumeration elements list.
FFLTR3EN : Fault Input 3 Filter Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input filter is disabled.
#1 : 1
Fault input filter is enabled.
End of enumeration elements list.
FFVAL : Fault Input Filter
bits : 8 - 11 (4 bit)
access : read-write
Modulo
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD : Modulo Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Value
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Configuration
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NUMTOF : TOF Frequency
bits : 0 - 4 (5 bit)
access : read-write
BDMMODE : Debug Mode
bits : 6 - 7 (2 bit)
access : read-write
GTBEEN : Global Time Base Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use of an external global time base is disabled.
#1 : 1
Use of an external global time base is enabled.
End of enumeration elements list.
GTBEOUT : Global Time Base Output
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
A global time base signal generation is disabled.
#1 : 1
A global time base signal generation is enabled.
End of enumeration elements list.
FTM Fault Input Polarity
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLT0POL : Fault Input 0 Polarity
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#1 : 1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
End of enumeration elements list.
FLT1POL : Fault Input 1 Polarity
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#1 : 1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
End of enumeration elements list.
FLT2POL : Fault Input 2 Polarity
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#1 : 1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
End of enumeration elements list.
FLT3POL : Fault Input 3 Polarity
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#1 : 1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
End of enumeration elements list.
Synchronization Configuration
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HWTRIGMODE : Hardware Trigger Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
#1 : 1
FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
End of enumeration elements list.
CNTINC : CNTIN Register Synchronization
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
CNTIN register is updated with its buffer value at all rising edges of system clock.
#1 : 1
CNTIN register is updated with its buffer value by the PWM synchronization.
End of enumeration elements list.
INVC : INVCTRL Register Synchronization
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
INVCTRL register is updated with its buffer value at all rising edges of system clock.
#1 : 1
INVCTRL register is updated with its buffer value by the PWM synchronization.
End of enumeration elements list.
SWOC : SWOCTRL Register Synchronization
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
SWOCTRL register is updated with its buffer value at all rising edges of system clock.
#1 : 1
SWOCTRL register is updated with its buffer value by the PWM synchronization.
End of enumeration elements list.
SYNCMODE : Synchronization Mode
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Legacy PWM synchronization is selected.
#1 : 1
Enhanced PWM synchronization is selected.
End of enumeration elements list.
SWRSTCNT : FTM counter synchronization is activated by the software trigger.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software trigger does not activate the FTM counter synchronization.
#1 : 1
The software trigger activates the FTM counter synchronization.
End of enumeration elements list.
SWWRBUF : MOD, CNTIN, and CV registers synchronization is activated by the software trigger.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software trigger does not activate MOD, CNTIN, and CV registers synchronization.
#1 : 1
The software trigger activates MOD, CNTIN, and CV registers synchronization.
End of enumeration elements list.
SWOM : Output mask synchronization is activated by the software trigger.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software trigger does not activate the OUTMASK register synchronization.
#1 : 1
The software trigger activates the OUTMASK register synchronization.
End of enumeration elements list.
SWINVC : Inverting control synchronization is activated by the software trigger.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software trigger does not activate the INVCTRL register synchronization.
#1 : 1
The software trigger activates the INVCTRL register synchronization.
End of enumeration elements list.
SWSOC : Software output control synchronization is activated by the software trigger.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software trigger does not activate the SWOCTRL register synchronization.
#1 : 1
The software trigger activates the SWOCTRL register synchronization.
End of enumeration elements list.
HWRSTCNT : FTM counter synchronization is activated by a hardware trigger.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
A hardware trigger does not activate the FTM counter synchronization.
#1 : 1
A hardware trigger activates the FTM counter synchronization.
End of enumeration elements list.
HWWRBUF : MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.
#1 : 1
A hardware trigger activates MOD, CNTIN, and CV registers synchronization.
End of enumeration elements list.
HWOM : Output mask synchronization is activated by a hardware trigger.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
A hardware trigger does not activate the OUTMASK register synchronization.
#1 : 1
A hardware trigger activates the OUTMASK register synchronization.
End of enumeration elements list.
HWINVC : Inverting control synchronization is activated by a hardware trigger.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
A hardware trigger does not activate the INVCTRL register synchronization.
#1 : 1
A hardware trigger activates the INVCTRL register synchronization.
End of enumeration elements list.
HWSOC : Software output control synchronization is activated by a hardware trigger.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
A hardware trigger does not activate the SWOCTRL register synchronization.
#1 : 1
A hardware trigger activates the SWOCTRL register synchronization.
End of enumeration elements list.
FTM Inverting Control
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV0EN : Pair Channels 0 Inverting Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverting is disabled.
#1 : 1
Inverting is enabled.
End of enumeration elements list.
INV1EN : Pair Channels 1 Inverting Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverting is disabled.
#1 : 1
Inverting is enabled.
End of enumeration elements list.
INV2EN : Pair Channels 2 Inverting Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverting is disabled.
#1 : 1
Inverting is enabled.
End of enumeration elements list.
INV3EN : Pair Channels 3 Inverting Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverting is disabled.
#1 : 1
Inverting is enabled.
End of enumeration elements list.
FTM Software Output Control
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0OC : Channel 0 Software Output Control Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH1OC : Channel 1 Software Output Control Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH2OC : Channel 2 Software Output Control Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH3OC : Channel 3 Software Output Control Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH4OC : Channel 4 Software Output Control Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH5OC : Channel 5 Software Output Control Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH6OC : Channel 6 Software Output Control Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH7OC : Channel 7 Software Output Control Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
End of enumeration elements list.
CH0OCV : Channel 0 Software Output Control Value
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH1OCV : Channel 1 Software Output Control Value
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH2OCV : Channel 2 Software Output Control Value
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH3OCV : Channel 3 Software Output Control Value
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH4OCV : Channel 4 Software Output Control Value
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH5OCV : Channel 5 Software Output Control Value
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH6OCV : Channel 6 Software Output Control Value
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH7OCV : Channel 7 Software Output Control Value
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
End of enumeration elements list.
Channel (n) Status And Control
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ELSA : Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel interrupts. Use software polling.
#1 : 1
Enable channel interrupts.
End of enumeration elements list.
CHF : Channel Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
FTM PWM Load
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0SEL : Channel 0 Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the channel in the matching process.
#1 : 1
Include the channel in the matching process.
End of enumeration elements list.
CH1SEL : Channel 1 Select
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the channel in the matching process.
#1 : 1
Include the channel in the matching process.
End of enumeration elements list.
CH2SEL : Channel 2 Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the channel in the matching process.
#1 : 1
Include the channel in the matching process.
End of enumeration elements list.
CH3SEL : Channel 3 Select
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the channel in the matching process.
#1 : 1
Include the channel in the matching process.
End of enumeration elements list.
CH4SEL : Channel 4 Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the channel in the matching process.
#1 : 1
Include the channel in the matching process.
End of enumeration elements list.
CH5SEL : Channel 5 Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the channel in the matching process.
#1 : 1
Include the channel in the matching process.
End of enumeration elements list.
CH6SEL : Channel 6 Select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the channel in the matching process.
#1 : 1
Include the channel in the matching process.
End of enumeration elements list.
CH7SEL : Channel 7 Select
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not include the channel in the matching process.
#1 : 1
Include the channel in the matching process.
End of enumeration elements list.
LDOK : Load Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Loading updated values is disabled.
#1 : 1
Loading updated values is enabled.
End of enumeration elements list.
Channel (n) Value
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Status And Control
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ELSA : Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel interrupts. Use software polling.
#1 : 1
Enable channel interrupts.
End of enumeration elements list.
CHF : Channel Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
Channel (n) Value
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
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