\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
SPI Control Register 1
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSBFE : LSB First (shifter direction)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI serial data transfers start with the most significant bit.
#1 : 1
SPI serial data transfers start with the least significant bit.
End of enumeration elements list.
SSOE : Slave Select Output Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input.
#1 : 1
When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input.
End of enumeration elements list.
CPHA : Clock Phase
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
First edge on SPSCK occurs at the middle of the first cycle of a data transfer.
#1 : 1
First edge on SPSCK occurs at the start of the first cycle of a data transfer.
End of enumeration elements list.
CPOL : Clock Polarity
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Active-high SPI clock (idles low)
#1 : 1
Active-low SPI clock (idles high)
End of enumeration elements list.
MSTR : Master/Slave Mode Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI module configured as a slave SPI device
#1 : 1
SPI module configured as a master SPI device
End of enumeration elements list.
SPTIE : SPI Transmit Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts from SPTEF inhibited (use polling)
#1 : 1
When SPTEF is 1, hardware interrupt requested
End of enumeration elements list.
SPE : SPI System Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI system inactive
#1 : 1
SPI system enabled
End of enumeration elements list.
SPIE : SPI Interrupt Enable: for SPRF and MODF
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts from SPRF and MODF are inhibited-use polling
#1 : 1
Request a hardware interrupt when SPRF or MODF is 1
End of enumeration elements list.
SPI Control Register 2
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPC0 : SPI Pin Control 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in.
#1 : 1
SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI.
End of enumeration elements list.
SPISWAI : SPI Stop in Wait Mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI clocks continue to operate in Wait mode.
#1 : 1
SPI clocks stop when the MCU enters Wait mode.
End of enumeration elements list.
BIDIROE : Bidirectional Mode Output Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output driver disabled so SPI data I/O pin acts as an input
#1 : 1
SPI I/O pin enabled as an output
End of enumeration elements list.
MODFEN : Master Mode-Fault Function Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
#1 : 1
Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
End of enumeration elements list.
SPMIE : SPI Match Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts from SPMF inhibited (use polling)
#1 : 1
When SPMF is 1, requests a hardware interrupt
End of enumeration elements list.
SPI Baud Rate Register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPR : SPI Baud Rate Divisor
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Baud rate divisor is 2.
#0001 : 0001
Baud rate divisor is 4.
#0010 : 0010
Baud rate divisor is 8.
#0011 : 0011
Baud rate divisor is 16.
#0100 : 0100
Baud rate divisor is 32.
#0101 : 0101
Baud rate divisor is 64.
#0110 : 0110
Baud rate divisor is 128.
#0111 : 0111
Baud rate divisor is 256.
#1000 : 1000
Baud rate divisor is 512.
End of enumeration elements list.
SPPR : SPI Baud Rate Prescale Divisor
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 000
Baud rate prescaler divisor is 1.
#001 : 001
Baud rate prescaler divisor is 2.
#010 : 010
Baud rate prescaler divisor is 3.
#011 : 011
Baud rate prescaler divisor is 4.
#100 : 100
Baud rate prescaler divisor is 5.
#101 : 101
Baud rate prescaler divisor is 6.
#110 : 110
Baud rate prescaler divisor is 7.
#111 : 111
Baud rate prescaler divisor is 8.
End of enumeration elements list.
SPI Status Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODF : Master Mode Fault Flag
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
No mode fault error
#1 : 1
Mode fault error detected
End of enumeration elements list.
SPTEF : SPI Transmit Buffer Empty Flag
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
SPI transmit buffer not empty
#1 : 1
SPI transmit buffer empty
End of enumeration elements list.
SPMF : SPI Match Flag
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Value in the receive data buffer does not match the value in the M register
#1 : 1
Value in the receive data buffer matches the value in the M register
End of enumeration elements list.
SPRF : SPI Read Buffer Full Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No data available in the receive data buffer
#1 : 1
Data available in the receive data buffer
End of enumeration elements list.
SPI Data Register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Bits : Data (low byte)
bits : 0 - 7 (8 bit)
access : read-write
SPI Match Register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Bits : Hardware compare value (low byte)
bits : 0 - 7 (8 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.