Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
UART Baud Rate Register: High
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBR : Baud Rate Modulo Divisor.
bits : 0 - 4 (5 bit)
access : read-write
SBNS : Stop Bit Number Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
One stop bit.
#1 : 1
Two stop bit.
End of enumeration elements list.
RXEDGIE : RxD Input Active Edge Interrupt Enable (for RXEDGIF)
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling).
#1 : 1
Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1.
End of enumeration elements list.
LBKDIE : LIN Break Detect Interrupt Enable (for LBKDIF)
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware interrupts from UART_S2[LBKDIF] disabled (use polling).
#1 : 1
Hardware interrupt requested when UART_S2[LBKDIF] flag is 1.
End of enumeration elements list.
UART Baud Rate Register: Low
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBR : Baud Rate Modulo Divisor
bits : 0 - 7 (8 bit)
access : read-write
UART Control Register 1
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PT : Parity Type
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Even parity.
#1 : 1
Odd parity.
End of enumeration elements list.
PE : Parity Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No hardware parity generation or checking.
#1 : 1
Parity enabled.
End of enumeration elements list.
ILT : Idle Line Type Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Idle character bit count starts after start bit.
#1 : 1
Idle character bit count starts after stop bit.
End of enumeration elements list.
WAKE : Receiver Wakeup Method Select
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Idle-line wake-up.
#1 : 1
Address-mark wake-up.
End of enumeration elements list.
M : 9-Bit or 8-Bit Mode Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal - start + 8 data bits (lsb first) + stop.
#1 : 1
Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop.
End of enumeration elements list.
RSRC : Receiver Source Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the RxD pins.
#1 : 1
Single-wire UART mode where the TxD pin is connected to the transmitter output and receiver input.
End of enumeration elements list.
UARTSWAI : UART Stops in Wait Mode
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART clocks continue to run in Wait mode so the UART can be the source of an interrupt that wakes up the CPU.
#1 : 1
UART clocks freeze while CPU is in Wait mode.
End of enumeration elements list.
LOOPS : Loop Mode Select
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation - RxD and TxD use separate pins.
#1 : 1
Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by UART.
End of enumeration elements list.
UART Control Register 2
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBK : Send Break
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal transmitter operation.
#1 : 1
Queue break character(s) to be sent.
End of enumeration elements list.
RWU : Receiver Wakeup Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal UART receiver operation.
#1 : 1
UART receiver in standby waiting for wake-up condition.
End of enumeration elements list.
RE : Receiver Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver off.
#1 : 1
Receiver on.
End of enumeration elements list.
TE : Transmitter Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitter off.
#1 : 1
Transmitter on.
End of enumeration elements list.
ILIE : Idle Line Interrupt Enable for IDLE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware interrupts from S1[IDLE] disabled; use polling.
#1 : 1
Hardware interrupt requested when S1[IDLE] flag is 1.
End of enumeration elements list.
RIE : Receiver Interrupt Enable for RDRF
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware interrupts from S1[RDRF] disabled; use polling.
#1 : 1
Hardware interrupt requested when S1[RDRF] flag is 1.
End of enumeration elements list.
TCIE : Transmission Complete Interrupt Enable for TC
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware interrupts from TC disabled; use polling.
#1 : 1
Hardware interrupt requested when TC flag is 1.
End of enumeration elements list.
TIE : Transmit Interrupt Enable for TDRE
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware interrupts from TDRE disabled; use polling.
#1 : 1
Hardware interrupt requested when TDRE flag is 1.
End of enumeration elements list.
UART Status Register 1
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PF : Parity Error Flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
No parity error.
#1 : 1
Parity error.
End of enumeration elements list.
FE : Framing Error Flag
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
No framing error detected. This does not guarantee the framing is correct.
#1 : 1
Framing error.
End of enumeration elements list.
NF : Noise Flag
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
No noise detected.
#1 : 1
Noise detected in the received character in UART_D.
End of enumeration elements list.
OR : Receiver Overrun Flag
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
No overrun.
#1 : 1
Receive overrun (new UART data lost).
End of enumeration elements list.
IDLE : Idle Line Flag
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
No idle line detected.
#1 : 1
Idle line was detected.
End of enumeration elements list.
RDRF : Receive Data Register Full Flag
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive data register empty.
#1 : 1
Receive data register full.
End of enumeration elements list.
TC : Transmission Complete Flag
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmitter active (sending data, a preamble, or a break).
#1 : 1
Transmitter idle (transmission activity complete).
End of enumeration elements list.
TDRE : Transmit Data Register Empty Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit data register (buffer) full.
#1 : 1
Transmit data register (buffer) empty.
End of enumeration elements list.
UART Status Register 2
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAF : Receiver Active Flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
UART receiver idle waiting for a start bit.
#1 : 1
UART receiver active (RxD input not idle).
End of enumeration elements list.
LBKDE : LIN Break Detection Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Break detection is disabled.
#1 : 1
Break detection is enabled (Break character is detected at length 11 bit times (if C1[M] = 0, BDH[SBNS] = 0) or 12 (if C1[M] = 1, BDH[SBNS] = 0 or C1[M] = 0, BDH[SBNS] = 1) or 13 (if C1[M] = 1, BDH[SBNS] = 1)).
End of enumeration elements list.
BRK13 : Break Character Generation Length
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1).
#1 : 1
Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1).
End of enumeration elements list.
RWUID : Receive Wake Up Idle Detect
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
During receive standby state (RWU = 1), S1[IDLE] does not get set upon detection of an idle character.
#1 : 1
During receive standby state (RWU = 1), S1[IDLE] gets set upon detection of an idle character.
End of enumeration elements list.
RXINV : Receive Data Inversion
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive data not inverted.
#1 : 1
Receive data inverted.
End of enumeration elements list.
RXEDGIF : RxD Pin Active Edge Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No active edge on the receive pin has occurred.
#1 : 1
An active edge on the receive pin has occurred.
End of enumeration elements list.
LBKDIF : LIN Break Detect Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No LIN break character has been detected.
#1 : 1
LIN break character has been detected.
End of enumeration elements list.
UART Control Register 3
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEIE : Parity Error Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PF interrupts disabled; use polling).
#1 : 1
Hardware interrupt requested when PF is set.
End of enumeration elements list.
FEIE : Framing Error Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FE interrupts disabled; use polling).
#1 : 1
Hardware interrupt requested when FE is set.
End of enumeration elements list.
NEIE : Noise Error Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
NF interrupts disabled; use polling).
#1 : 1
Hardware interrupt requested when NF is set.
End of enumeration elements list.
ORIE : Overrun Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
OR interrupts disabled; use polling.
#1 : 1
Hardware interrupt requested when OR is set.
End of enumeration elements list.
TXINV : Transmit Data Inversion
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit data not inverted.
#1 : 1
Transmit data inverted.
End of enumeration elements list.
TXDIR : TxD Pin Direction in Single-Wire Mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
TxD pin is an input in single-wire mode.
#1 : 1
TxD pin is an output in single-wire mode.
End of enumeration elements list.
T8 : Ninth Data Bit for Transmitter
bits : 6 - 6 (1 bit)
access : read-write
R8 : Ninth Data Bit for Receiver
bits : 7 - 7 (1 bit)
access : read-only
UART Data Register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R0T0 : Read receive data buffer 0 or write transmit data buffer 0.
bits : 0 - 0 (1 bit)
access : read-write
R1T1 : Read receive data buffer 1 or write transmit data buffer 1.
bits : 1 - 1 (1 bit)
access : read-write
R2T2 : Read receive data buffer 2 or write transmit data buffer 2.
bits : 2 - 2 (1 bit)
access : read-write
R3T3 : Read receive data buffer 3 or write transmit data buffer 3.
bits : 3 - 3 (1 bit)
access : read-write
R4T4 : Read receive data buffer 4 or write transmit data buffer 4.
bits : 4 - 4 (1 bit)
access : read-write
R5T5 : Read receive data buffer 5 or write transmit data buffer 5.
bits : 5 - 5 (1 bit)
access : read-write
R6T6 : Read receive data buffer 6 or write transmit data buffer 6.
bits : 6 - 6 (1 bit)
access : read-write
R7T7 : Read receive data buffer 7 or write transmit data buffer 7.
bits : 7 - 7 (1 bit)
access : read-write
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