Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
CMP Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HYSTCTR : Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
The hard block output has level 0 hysteresis internally.
#01 : 01
The hard block output has level 1 hysteresis internally.
#10 : 10
The hard block output has level 2 hysteresis internally.
#11 : 11
The hard block output has level 3 hysteresis internally.
0 : HYSTCTR_0
The hard block output has level 0 hysteresis internally.
0x1 : HYSTCTR_1
The hard block output has level 1 hysteresis internally.
0x2 : HYSTCTR_2
The hard block output has level 2 hysteresis internally.
0x3 : HYSTCTR_3
The hard block output has level 3 hysteresis internally.
End of enumeration elements list.
OFFSET : Comparator hard block offset control. See chip data sheet to get the actual offset value with each level
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The comparator hard block output has level 0 offset internally.
#1 : 1
The comparator hard block output has level 1 offset internally.
0 : OFFSET_0
The comparator hard block output has level 0 offset internally.
0x1 : OFFSET_1
The comparator hard block output has level 1 offset internally.
End of enumeration elements list.
FILTER_CNT : Filter Sample Count
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 000
Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA.
#001 : 001
1 consecutive sample must agree (comparator output is simply sampled).
#010 : 010
2 consecutive samples must agree.
#011 : 011
3 consecutive samples must agree.
#100 : 100
4 consecutive samples must agree.
#101 : 101
5 consecutive samples must agree.
#110 : 110
6 consecutive samples must agree.
#111 : 111
7 consecutive samples must agree.
0 : FILTER_CNT_0
Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA.
0x1 : FILTER_CNT_1
1 consecutive sample must agree (comparator output is simply sampled).
0x2 : FILTER_CNT_2
2 consecutive samples must agree.
0x3 : FILTER_CNT_3
3 consecutive samples must agree.
0x4 : FILTER_CNT_4
4 consecutive samples must agree.
0x5 : FILTER_CNT_5
5 consecutive samples must agree.
0x6 : FILTER_CNT_6
6 consecutive samples must agree.
0x7 : FILTER_CNT_7
7 consecutive samples must agree.
End of enumeration elements list.
EN : Comparator Module Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog Comparator is disabled.
#1 : 1
Analog Comparator is enabled.
0 : EN_0
Analog Comparator is disabled.
0x1 : EN_1
Analog Comparator is enabled.
End of enumeration elements list.
OPE : Comparator Output Pin Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
When OPE is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin.
#1 : 1
When OPE is 1, and if the software has configured the comparator to own a packaged pin, the comparator is available in a packaged pin.
0 : OPE_0
When OPE is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin.
0x1 : OPE_1
When OPE is 1, and if the software has configured the comparator to own a packaged pin, the comparator is available in a packaged pin.
End of enumeration elements list.
COS : Comparator Output Select
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set CMPO to equal COUT (filtered comparator output).
#1 : 1
Set CMPO to equal COUTA (unfiltered comparator output).
0 : COS_0
Set CMPO to equal COUT (filtered comparator output).
0x1 : COS_1
Set CMPO to equal COUTA (unfiltered comparator output).
End of enumeration elements list.
INVT : Comparator invert
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Does not invert the comparator output.
#1 : 1
Inverts the comparator output.
0 : INVT_0
Does not invert the comparator output.
0x1 : INVT_1
Inverts the comparator output.
End of enumeration elements list.
PMODE : Power Mode Select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low Speed (LS) comparison mode is selected.
#1 : 1
High Speed (HS) comparison mode is selected, in VLPx mode, or Stop mode switched to Low Speed (LS) mode.
0 : PMODE_0
Low Speed (LS) comparison mode is selected.
0x1 : PMODE_1
High Speed (HS) comparison mode is selected, in VLPx mode, or Stop mode switched to Low Speed (LS) mode.
End of enumeration elements list.
WE : Windowing Enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Windowing mode is not selected.
#1 : 1
Windowing mode is selected.
0 : WE_0
Windowing mode is not selected.
0x1 : WE_1
Windowing mode is selected.
End of enumeration elements list.
SE : Sample Enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sampling mode is not selected.
#1 : 1
Sampling mode is selected.
0 : SE_0
Sampling mode is not selected.
0x1 : SE_1
Sampling mode is selected.
End of enumeration elements list.
FPR : Filter Sample Period
bits : 16 - 23 (8 bit)
access : read-write
COUT : Analog Comparator Output
bits : 24 - 24 (1 bit)
access : read-only
CFF : Analog Comparator Flag Falling
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
A falling edge has not been detected on COUT.
#1 : 1
A falling edge on COUT has occurred.
0 : CFF_0
A falling edge has not been detected on COUT.
0x1 : CFF_1
A falling edge on COUT has occurred.
End of enumeration elements list.
CFR : Analog Comparator Flag Rising
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
A rising edge has not been detected on COUT.
#1 : 1
A rising edge on COUT has occurred.
0 : CFR_0
A rising edge has not been detected on COUT.
0x1 : CFR_1
A rising edge on COUT has occurred.
End of enumeration elements list.
IEF : Comparator Interrupt Enable Falling
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt is disabled.
#1 : 1
Interrupt is enabled.
0 : IEF_0
Interrupt is disabled.
0x1 : IEF_1
Interrupt is enabled.
End of enumeration elements list.
IER : Comparator Interrupt Enable Rising
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt is disabled.
#1 : 1
Interrupt is enabled.
0 : IER_0
Interrupt is disabled.
0x1 : IER_1
Interrupt is enabled.
End of enumeration elements list.
DMAEN : DMA Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA is disabled.
#1 : 1
DMA is enabled.
0 : DMAEN_0
DMA is disabled.
0x1 : DMAEN_1
DMA is enabled.
End of enumeration elements list.
CMP Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VOSEL : DAC Output Voltage Select
bits : 0 - 7 (8 bit)
access : read-write
MSEL : Minus Input MUX Control
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
IN0
#001 : 001
IN1
#010 : 010
IN2
#011 : 011
IN3
#100 : 100
IN4
#101 : 101
IN5
#110 : 110
IN6
#111 : 111
IN7
0 : MSEL_0
IN0
0x1 : MSEL_1
IN1
0x2 : MSEL_2
IN2
0x3 : MSEL_3
IN3
0x4 : MSEL_4
IN4
0x5 : MSEL_5
IN5
0x6 : MSEL_6
IN6
0x7 : MSEL_7
IN7
End of enumeration elements list.
PSEL : Plus Input MUX Control
bits : 11 - 13 (3 bit)
access : read-write
Enumeration:
#000 : 000
IN0
#001 : 001
IN1
#010 : 010
IN2
#011 : 011
IN3
#100 : 100
IN4
#101 : 101
IN5
#110 : 110
IN6
#111 : 111
IN7
0 : PSEL_0
IN0
0x1 : PSEL_1
IN1
0x2 : PSEL_2
IN2
0x3 : PSEL_3
IN3
0x4 : PSEL_4
IN4
0x5 : PSEL_5
IN5
0x6 : PSEL_6
IN6
0x7 : PSEL_7
IN7
End of enumeration elements list.
VRSEL : Supply Voltage Reference Source Select
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Vin1 is selected as resistor ladder network supply reference Vin.
#1 : 1
Vin2 is selected as resistor ladder network supply reference Vin.
0 : VRSEL_0
Vin1 is selected as resistor ladder network supply reference Vin.
0x1 : VRSEL_1
Vin2 is selected as resistor ladder network supply reference Vin.
End of enumeration elements list.
DACEN : DAC Enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC is disabled.
#1 : 1
DAC is enabled.
0 : DACEN_0
DAC is disabled.
0x1 : DACEN_1
DAC is enabled.
End of enumeration elements list.
CHN0 : Channel 0 input enable
bits : 16 - 16 (1 bit)
access : read-write
CHN1 : Channel 1 input enable
bits : 17 - 17 (1 bit)
access : read-write
CHN2 : Channel 2 input enable
bits : 18 - 18 (1 bit)
access : read-write
CHN3 : Channel 3 input enable
bits : 19 - 19 (1 bit)
access : read-write
CHN4 : Channel 4 input enable
bits : 20 - 20 (1 bit)
access : read-write
CHN5 : Channel 5 input enable
bits : 21 - 21 (1 bit)
access : read-write
CHN6 : Channel 6 input enable
bits : 22 - 22 (1 bit)
access : read-write
CHN7 : Channel 7 input enable
bits : 23 - 23 (1 bit)
access : read-write
INNSEL : Selection of the input to the negative port of the comparator
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
IN0, from the 8-bit DAC output
#01 : 01
IN1, from the analog 8-1 mux
0 : INNSEL_0
IN0, from the 8-bit DAC output
0x1 : INNSEL_1
IN1, from the analog 8-1 mux
End of enumeration elements list.
INPSEL : Selection of the input to the positive port of the comparator
bits : 27 - 28 (2 bit)
access : read-write
Enumeration:
#00 : 00
IN0, from the 8-bit DAC output
#01 : 01
IN1, from the analog 8-1 mux
0 : INPSEL_0
IN0, from the 8-bit DAC output
0x1 : INPSEL_1
IN1, from the analog 8-1 mux
End of enumeration elements list.
CMP Control Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACOn : The result of the input comparison for channel n
bits : 0 - 7 (8 bit)
access : read-write
INITMOD : Comparator and DAC initialization delay modulus.
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#0 : 000000
The modulus is set to 64(same with 111111).
0 : INITMOD_0
The modulus is set to 64(same with 111111).
End of enumeration elements list.
NSAM : Number of sample clocks
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 00
The comparison result is sampled as soon as the active channel is scanned in one round-robin clock.
#01 : 01
The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock.
#10 : 10
The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock.
#11 : 11
The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock.
0 : NSAM_0
The comparison result is sampled as soon as the active channel is scanned in one round-robin clock.
0x1 : NSAM_1
The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock.
0x2 : NSAM_2
The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock.
0x3 : NSAM_3
The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock.
End of enumeration elements list.
CH0F : Channel 0 input changed flag
bits : 16 - 16 (1 bit)
access : read-write
CH1F : Channel 1 input changed flag
bits : 17 - 17 (1 bit)
access : read-write
CH2F : Channel 2 input changed flag
bits : 18 - 18 (1 bit)
access : read-write
CH3F : Channel 3 input changed flag
bits : 19 - 19 (1 bit)
access : read-write
CH4F : Channel 4 input changed flag
bits : 20 - 20 (1 bit)
access : read-write
CH5F : Channel 5 input changed flag
bits : 21 - 21 (1 bit)
access : read-write
CH6F : Channel 6 input changed flag
bits : 22 - 22 (1 bit)
access : read-write
CH7F : Channel 7 input changed flag
bits : 23 - 23 (1 bit)
access : read-write
FXMXCH : Fixed channel selection
bits : 25 - 27 (3 bit)
access : read-write
Enumeration:
#000 : 000
Channel 0 is selected as the fixed reference input for the fixed mux port.
#001 : 001
Channel 1 is selected as the fixed reference input for the fixed mux port.
#010 : 010
Channel 2 is selected as the fixed reference input for the fixed mux port.
#011 : 011
Channel 3 is selected as the fixed reference input for the fixed mux port.
#100 : 100
Channel 4 is selected as the fixed reference input for the fixed mux port.
#101 : 101
Channel 5 is selected as the fixed reference input for the fixed mux port.
#110 : 110
Channel 6 is selected as the fixed reference input for the fixed mux port.
#111 : 111
Channel 7 is selected as the fixed reference input for the fixed mux port.
0 : FXMXCH_0
Channel 0 is selected as the fixed reference input for the fixed mux port.
0x1 : FXMXCH_1
Channel 1 is selected as the fixed reference input for the fixed mux port.
0x2 : FXMXCH_2
Channel 2 is selected as the fixed reference input for the fixed mux port.
0x3 : FXMXCH_3
Channel 3 is selected as the fixed reference input for the fixed mux port.
0x4 : FXMXCH_4
Channel 4 is selected as the fixed reference input for the fixed mux port.
0x5 : FXMXCH_5
Channel 5 is selected as the fixed reference input for the fixed mux port.
0x6 : FXMXCH_6
Channel 6 is selected as the fixed reference input for the fixed mux port.
0x7 : FXMXCH_7
Channel 7 is selected as the fixed reference input for the fixed mux port.
End of enumeration elements list.
FXMP : Fixed MUX Port
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
The Plus port is fixed. Only the inputs to the Minus port are swept in each round.
#1 : 1
The Minus port is fixed. Only the inputs to the Plus port are swept in each round.
0 : FXMP_0
The Plus port is fixed. Only the inputs to the Minus port are swept in each round.
0x1 : FXMP_1
The Minus port is fixed. Only the inputs to the Plus port are swept in each round.
End of enumeration elements list.
RRIE : Round-Robin interrupt enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The round-robin interrupt is disabled.
#1 : 1
The round-robin interrupt is enabled when a comparison result changes from the last sample.
0 : RRIE_0
The round-robin interrupt is disabled.
0x1 : RRIE_1
The round-robin interrupt is enabled when a comparison result changes from the last sample.
End of enumeration elements list.
RRE : Round-Robin Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Round-robin operation is disabled.
#1 : 1
Round-robin operation is enabled.
0 : RRE_0
Round-robin operation is disabled.
0x1 : RRE_1
Round-robin operation is enabled.
End of enumeration elements list.
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