Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
Channel Configuration register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#1 : 1
TSI_Signal
#10 : 2
LPUART0_Rx_Signal
#11 : 3
LPUART0_Tx_Signal
#100 : 4
LPUART1_Rx_Signal
#101 : 5
LPUART1_Tx_Signal
#110 : 6
LPUART2_Rx_Signal
#111 : 7
LPUART2_Tx_Signal
#1010 : 10
FlexIO_Channel0_Signal
#1011 : 11
FlexIO_Channel1_Signal
#1100 : 12
FlexIO_Channel2_Signal
#1101 : 13
FlexIO_Channel3_Signal
#1110 : 14
LPSPI0_Rx_Signal
#1111 : 15
LPSPI0_Tx_Signal
#10000 : 16
LPSPI1_Rx_Signal
#10001 : 17
LPSPI1_Tx_Signal
#10010 : 18
LPI2C0_Rx_Signal
#10011 : 19
LPI2C0_Tx_Signal
#10100 : 20
FTM0_Channel0_Signal
#10101 : 21
FTM0_Channel1_Signal
#10110 : 22
FTM0_Channel2_Signal
#10111 : 23
FTM0_Channel3_Signal
#11000 : 24
FTM0_Channel4_Signal
#11001 : 25
FTM0_Channel5_Signal
#11010 : 26
FTM0_Channel6_Signal
#11011 : 27
FTM0_Channel7_Signal
#11100 : 28
FTM1_Channel0_Signal
#11101 : 29
FTM1_Channel1_Signal
#11110 : 30
FTM2_Channel0_Signal
#11111 : 31
FTM2_Channel1_Signal
#100000 : 32
LPI2C1_Rx_Signal
#100001 : 33
LPI2C1_Tx_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101011 : 43
CMP0_Signal
#101100 : 44
CMP1_Signal
#101110 : 46
PDB0_Signal
#110001 : 49
PortA_Signal
#110010 : 50
PortB_Signal
#110011 : 51
PortC_Signal
#110100 : 52
PortD_Signal
#110101 : 53
PortE_Signal
#111001 : 57
FTM1_Channel2_Signal
#111010 : 58
FTM2_Channel2_Signal
#111011 : 59
LPTMR0_Signal
#111100 : 60
AlwaysOn60_Signal
#111101 : 61
AlwaysOn61_Signal
#111110 : 62
AlwaysOn62_Signal
#111111 : 63
AlwaysOn63_Signal
0 : Disable_Signal
Disable_Signal
0x1 : TSI_Signal
TSI_Signal
0x2 : LPUART0_Rx_Signal
LPUART0_Rx_Signal
0x3 : LPUART0_Tx_Signal
LPUART0_Tx_Signal
0x4 : LPUART1_Rx_Signal
LPUART1_Rx_Signal
0x5 : LPUART1_Tx_Signal
LPUART1_Tx_Signal
0x6 : LPUART2_Rx_Signal
LPUART2_Rx_Signal
0x7 : LPUART2_Tx_Signal
LPUART2_Tx_Signal
0xA : FlexIO_Channel0_Signal
FlexIO_Channel0_Signal
0xB : FlexIO_Channel1_Signal
FlexIO_Channel1_Signal
0xC : FlexIO_Channel2_Signal
FlexIO_Channel2_Signal
0xD : FlexIO_Channel3_Signal
FlexIO_Channel3_Signal
0xE : LPSPI0_Rx_Signal
LPSPI0_Rx_Signal
0xF : LPSPI0_Tx_Signal
LPSPI0_Tx_Signal
0x10 : LPSPI1_Rx_Signal
LPSPI1_Rx_Signal
0x11 : LPSPI1_Tx_Signal
LPSPI1_Tx_Signal
0x12 : LPI2C0_Rx_Signal
LPI2C0_Rx_Signal
0x13 : LPI2C0_Tx_Signal
LPI2C0_Tx_Signal
0x14 : FTM0_Channel0_Signal
FTM0_Channel0_Signal
0x15 : FTM0_Channel1_Signal
FTM0_Channel1_Signal
0x16 : FTM0_Channel2_Signal
FTM0_Channel2_Signal
0x17 : FTM0_Channel3_Signal
FTM0_Channel3_Signal
0x18 : FTM0_Channel4_Signal
FTM0_Channel4_Signal
0x19 : FTM0_Channel5_Signal
FTM0_Channel5_Signal
0x1A : FTM0_Channel6_Signal
FTM0_Channel6_Signal
0x1B : FTM0_Channel7_Signal
FTM0_Channel7_Signal
0x1C : FTM1_Channel0_Signal
FTM1_Channel0_Signal
0x1D : FTM1_Channel1_Signal
FTM1_Channel1_Signal
0x1E : FTM2_Channel0_Signal
FTM2_Channel0_Signal
0x1F : FTM2_Channel1_Signal
FTM2_Channel1_Signal
0x20 : LPI2C1_Rx_Signal
LPI2C1_Rx_Signal
0x21 : LPI2C1_Tx_Signal
LPI2C1_Tx_Signal
0x28 : ADC0_Signal
ADC0_Signal
0x29 : ADC1_Signal
ADC1_Signal
0x2B : CMP0_Signal
CMP0_Signal
0x2C : CMP1_Signal
CMP1_Signal
0x2E : PDB0_Signal
PDB0_Signal
0x31 : PortA_Signal
PortA_Signal
0x32 : PortB_Signal
PortB_Signal
0x33 : PortC_Signal
PortC_Signal
0x34 : PortD_Signal
PortD_Signal
0x35 : PortE_Signal
PortE_Signal
0x39 : FTM1_Channel2_Signal
FTM1_Channel2_Signal
0x3A : FTM2_Channel2_Signal
FTM2_Channel2_Signal
0x3B : LPTMR0_Signal
LPTMR0_Signal
0x3C : AlwaysOn60_Signal
AlwaysOn60_Signal
0x3D : AlwaysOn61_Signal
AlwaysOn61_Signal
0x3E : AlwaysOn62_Signal
AlwaysOn62_Signal
0x3F : AlwaysOn63_Signal
AlwaysOn63_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
0 : DISABLED
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : ENABLED
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#1 : 1
DMA channel is enabled
0 : DISABLED
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
0x1 : ENABLED
DMA channel is enabled
End of enumeration elements list.
Channel Configuration register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#1 : 1
TSI_Signal
#10 : 2
LPUART0_Rx_Signal
#11 : 3
LPUART0_Tx_Signal
#100 : 4
LPUART1_Rx_Signal
#101 : 5
LPUART1_Tx_Signal
#110 : 6
LPUART2_Rx_Signal
#111 : 7
LPUART2_Tx_Signal
#1010 : 10
FlexIO_Channel0_Signal
#1011 : 11
FlexIO_Channel1_Signal
#1100 : 12
FlexIO_Channel2_Signal
#1101 : 13
FlexIO_Channel3_Signal
#1110 : 14
LPSPI0_Rx_Signal
#1111 : 15
LPSPI0_Tx_Signal
#10000 : 16
LPSPI1_Rx_Signal
#10001 : 17
LPSPI1_Tx_Signal
#10010 : 18
LPI2C0_Rx_Signal
#10011 : 19
LPI2C0_Tx_Signal
#10100 : 20
FTM0_Channel0_Signal
#10101 : 21
FTM0_Channel1_Signal
#10110 : 22
FTM0_Channel2_Signal
#10111 : 23
FTM0_Channel3_Signal
#11000 : 24
FTM0_Channel4_Signal
#11001 : 25
FTM0_Channel5_Signal
#11010 : 26
FTM0_Channel6_Signal
#11011 : 27
FTM0_Channel7_Signal
#11100 : 28
FTM1_Channel0_Signal
#11101 : 29
FTM1_Channel1_Signal
#11110 : 30
FTM2_Channel0_Signal
#11111 : 31
FTM2_Channel1_Signal
#100000 : 32
LPI2C1_Rx_Signal
#100001 : 33
LPI2C1_Tx_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101011 : 43
CMP0_Signal
#101100 : 44
CMP1_Signal
#101110 : 46
PDB0_Signal
#110001 : 49
PortA_Signal
#110010 : 50
PortB_Signal
#110011 : 51
PortC_Signal
#110100 : 52
PortD_Signal
#110101 : 53
PortE_Signal
#111001 : 57
FTM1_Channel2_Signal
#111010 : 58
FTM2_Channel2_Signal
#111011 : 59
LPTMR0_Signal
#111100 : 60
AlwaysOn60_Signal
#111101 : 61
AlwaysOn61_Signal
#111110 : 62
AlwaysOn62_Signal
#111111 : 63
AlwaysOn63_Signal
0 : Disable_Signal
Disable_Signal
0x1 : TSI_Signal
TSI_Signal
0x2 : LPUART0_Rx_Signal
LPUART0_Rx_Signal
0x3 : LPUART0_Tx_Signal
LPUART0_Tx_Signal
0x4 : LPUART1_Rx_Signal
LPUART1_Rx_Signal
0x5 : LPUART1_Tx_Signal
LPUART1_Tx_Signal
0x6 : LPUART2_Rx_Signal
LPUART2_Rx_Signal
0x7 : LPUART2_Tx_Signal
LPUART2_Tx_Signal
0xA : FlexIO_Channel0_Signal
FlexIO_Channel0_Signal
0xB : FlexIO_Channel1_Signal
FlexIO_Channel1_Signal
0xC : FlexIO_Channel2_Signal
FlexIO_Channel2_Signal
0xD : FlexIO_Channel3_Signal
FlexIO_Channel3_Signal
0xE : LPSPI0_Rx_Signal
LPSPI0_Rx_Signal
0xF : LPSPI0_Tx_Signal
LPSPI0_Tx_Signal
0x10 : LPSPI1_Rx_Signal
LPSPI1_Rx_Signal
0x11 : LPSPI1_Tx_Signal
LPSPI1_Tx_Signal
0x12 : LPI2C0_Rx_Signal
LPI2C0_Rx_Signal
0x13 : LPI2C0_Tx_Signal
LPI2C0_Tx_Signal
0x14 : FTM0_Channel0_Signal
FTM0_Channel0_Signal
0x15 : FTM0_Channel1_Signal
FTM0_Channel1_Signal
0x16 : FTM0_Channel2_Signal
FTM0_Channel2_Signal
0x17 : FTM0_Channel3_Signal
FTM0_Channel3_Signal
0x18 : FTM0_Channel4_Signal
FTM0_Channel4_Signal
0x19 : FTM0_Channel5_Signal
FTM0_Channel5_Signal
0x1A : FTM0_Channel6_Signal
FTM0_Channel6_Signal
0x1B : FTM0_Channel7_Signal
FTM0_Channel7_Signal
0x1C : FTM1_Channel0_Signal
FTM1_Channel0_Signal
0x1D : FTM1_Channel1_Signal
FTM1_Channel1_Signal
0x1E : FTM2_Channel0_Signal
FTM2_Channel0_Signal
0x1F : FTM2_Channel1_Signal
FTM2_Channel1_Signal
0x20 : LPI2C1_Rx_Signal
LPI2C1_Rx_Signal
0x21 : LPI2C1_Tx_Signal
LPI2C1_Tx_Signal
0x28 : ADC0_Signal
ADC0_Signal
0x29 : ADC1_Signal
ADC1_Signal
0x2B : CMP0_Signal
CMP0_Signal
0x2C : CMP1_Signal
CMP1_Signal
0x2E : PDB0_Signal
PDB0_Signal
0x31 : PortA_Signal
PortA_Signal
0x32 : PortB_Signal
PortB_Signal
0x33 : PortC_Signal
PortC_Signal
0x34 : PortD_Signal
PortD_Signal
0x35 : PortE_Signal
PortE_Signal
0x39 : FTM1_Channel2_Signal
FTM1_Channel2_Signal
0x3A : FTM2_Channel2_Signal
FTM2_Channel2_Signal
0x3B : LPTMR0_Signal
LPTMR0_Signal
0x3C : AlwaysOn60_Signal
AlwaysOn60_Signal
0x3D : AlwaysOn61_Signal
AlwaysOn61_Signal
0x3E : AlwaysOn62_Signal
AlwaysOn62_Signal
0x3F : AlwaysOn63_Signal
AlwaysOn63_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
0 : DISABLED
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : ENABLED
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#1 : 1
DMA channel is enabled
0 : DISABLED
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
0x1 : ENABLED
DMA channel is enabled
End of enumeration elements list.
Channel Configuration register
address_offset : 0x15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#1 : 1
TSI_Signal
#10 : 2
LPUART0_Rx_Signal
#11 : 3
LPUART0_Tx_Signal
#100 : 4
LPUART1_Rx_Signal
#101 : 5
LPUART1_Tx_Signal
#110 : 6
LPUART2_Rx_Signal
#111 : 7
LPUART2_Tx_Signal
#1010 : 10
FlexIO_Channel0_Signal
#1011 : 11
FlexIO_Channel1_Signal
#1100 : 12
FlexIO_Channel2_Signal
#1101 : 13
FlexIO_Channel3_Signal
#1110 : 14
LPSPI0_Rx_Signal
#1111 : 15
LPSPI0_Tx_Signal
#10000 : 16
LPSPI1_Rx_Signal
#10001 : 17
LPSPI1_Tx_Signal
#10010 : 18
LPI2C0_Rx_Signal
#10011 : 19
LPI2C0_Tx_Signal
#10100 : 20
FTM0_Channel0_Signal
#10101 : 21
FTM0_Channel1_Signal
#10110 : 22
FTM0_Channel2_Signal
#10111 : 23
FTM0_Channel3_Signal
#11000 : 24
FTM0_Channel4_Signal
#11001 : 25
FTM0_Channel5_Signal
#11010 : 26
FTM0_Channel6_Signal
#11011 : 27
FTM0_Channel7_Signal
#11100 : 28
FTM1_Channel0_Signal
#11101 : 29
FTM1_Channel1_Signal
#11110 : 30
FTM2_Channel0_Signal
#11111 : 31
FTM2_Channel1_Signal
#100000 : 32
LPI2C1_Rx_Signal
#100001 : 33
LPI2C1_Tx_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101011 : 43
CMP0_Signal
#101100 : 44
CMP1_Signal
#101110 : 46
PDB0_Signal
#110001 : 49
PortA_Signal
#110010 : 50
PortB_Signal
#110011 : 51
PortC_Signal
#110100 : 52
PortD_Signal
#110101 : 53
PortE_Signal
#111001 : 57
FTM1_Channel2_Signal
#111010 : 58
FTM2_Channel2_Signal
#111011 : 59
LPTMR0_Signal
#111100 : 60
AlwaysOn60_Signal
#111101 : 61
AlwaysOn61_Signal
#111110 : 62
AlwaysOn62_Signal
#111111 : 63
AlwaysOn63_Signal
0 : Disable_Signal
Disable_Signal
0x1 : TSI_Signal
TSI_Signal
0x2 : LPUART0_Rx_Signal
LPUART0_Rx_Signal
0x3 : LPUART0_Tx_Signal
LPUART0_Tx_Signal
0x4 : LPUART1_Rx_Signal
LPUART1_Rx_Signal
0x5 : LPUART1_Tx_Signal
LPUART1_Tx_Signal
0x6 : LPUART2_Rx_Signal
LPUART2_Rx_Signal
0x7 : LPUART2_Tx_Signal
LPUART2_Tx_Signal
0xA : FlexIO_Channel0_Signal
FlexIO_Channel0_Signal
0xB : FlexIO_Channel1_Signal
FlexIO_Channel1_Signal
0xC : FlexIO_Channel2_Signal
FlexIO_Channel2_Signal
0xD : FlexIO_Channel3_Signal
FlexIO_Channel3_Signal
0xE : LPSPI0_Rx_Signal
LPSPI0_Rx_Signal
0xF : LPSPI0_Tx_Signal
LPSPI0_Tx_Signal
0x10 : LPSPI1_Rx_Signal
LPSPI1_Rx_Signal
0x11 : LPSPI1_Tx_Signal
LPSPI1_Tx_Signal
0x12 : LPI2C0_Rx_Signal
LPI2C0_Rx_Signal
0x13 : LPI2C0_Tx_Signal
LPI2C0_Tx_Signal
0x14 : FTM0_Channel0_Signal
FTM0_Channel0_Signal
0x15 : FTM0_Channel1_Signal
FTM0_Channel1_Signal
0x16 : FTM0_Channel2_Signal
FTM0_Channel2_Signal
0x17 : FTM0_Channel3_Signal
FTM0_Channel3_Signal
0x18 : FTM0_Channel4_Signal
FTM0_Channel4_Signal
0x19 : FTM0_Channel5_Signal
FTM0_Channel5_Signal
0x1A : FTM0_Channel6_Signal
FTM0_Channel6_Signal
0x1B : FTM0_Channel7_Signal
FTM0_Channel7_Signal
0x1C : FTM1_Channel0_Signal
FTM1_Channel0_Signal
0x1D : FTM1_Channel1_Signal
FTM1_Channel1_Signal
0x1E : FTM2_Channel0_Signal
FTM2_Channel0_Signal
0x1F : FTM2_Channel1_Signal
FTM2_Channel1_Signal
0x20 : LPI2C1_Rx_Signal
LPI2C1_Rx_Signal
0x21 : LPI2C1_Tx_Signal
LPI2C1_Tx_Signal
0x28 : ADC0_Signal
ADC0_Signal
0x29 : ADC1_Signal
ADC1_Signal
0x2B : CMP0_Signal
CMP0_Signal
0x2C : CMP1_Signal
CMP1_Signal
0x2E : PDB0_Signal
PDB0_Signal
0x31 : PortA_Signal
PortA_Signal
0x32 : PortB_Signal
PortB_Signal
0x33 : PortC_Signal
PortC_Signal
0x34 : PortD_Signal
PortD_Signal
0x35 : PortE_Signal
PortE_Signal
0x39 : FTM1_Channel2_Signal
FTM1_Channel2_Signal
0x3A : FTM2_Channel2_Signal
FTM2_Channel2_Signal
0x3B : LPTMR0_Signal
LPTMR0_Signal
0x3C : AlwaysOn60_Signal
AlwaysOn60_Signal
0x3D : AlwaysOn61_Signal
AlwaysOn61_Signal
0x3E : AlwaysOn62_Signal
AlwaysOn62_Signal
0x3F : AlwaysOn63_Signal
AlwaysOn63_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
0 : DISABLED
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : ENABLED
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#1 : 1
DMA channel is enabled
0 : DISABLED
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
0x1 : ENABLED
DMA channel is enabled
End of enumeration elements list.
Channel Configuration register
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#1 : 1
TSI_Signal
#10 : 2
LPUART0_Rx_Signal
#11 : 3
LPUART0_Tx_Signal
#100 : 4
LPUART1_Rx_Signal
#101 : 5
LPUART1_Tx_Signal
#110 : 6
LPUART2_Rx_Signal
#111 : 7
LPUART2_Tx_Signal
#1010 : 10
FlexIO_Channel0_Signal
#1011 : 11
FlexIO_Channel1_Signal
#1100 : 12
FlexIO_Channel2_Signal
#1101 : 13
FlexIO_Channel3_Signal
#1110 : 14
LPSPI0_Rx_Signal
#1111 : 15
LPSPI0_Tx_Signal
#10000 : 16
LPSPI1_Rx_Signal
#10001 : 17
LPSPI1_Tx_Signal
#10010 : 18
LPI2C0_Rx_Signal
#10011 : 19
LPI2C0_Tx_Signal
#10100 : 20
FTM0_Channel0_Signal
#10101 : 21
FTM0_Channel1_Signal
#10110 : 22
FTM0_Channel2_Signal
#10111 : 23
FTM0_Channel3_Signal
#11000 : 24
FTM0_Channel4_Signal
#11001 : 25
FTM0_Channel5_Signal
#11010 : 26
FTM0_Channel6_Signal
#11011 : 27
FTM0_Channel7_Signal
#11100 : 28
FTM1_Channel0_Signal
#11101 : 29
FTM1_Channel1_Signal
#11110 : 30
FTM2_Channel0_Signal
#11111 : 31
FTM2_Channel1_Signal
#100000 : 32
LPI2C1_Rx_Signal
#100001 : 33
LPI2C1_Tx_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101011 : 43
CMP0_Signal
#101100 : 44
CMP1_Signal
#101110 : 46
PDB0_Signal
#110001 : 49
PortA_Signal
#110010 : 50
PortB_Signal
#110011 : 51
PortC_Signal
#110100 : 52
PortD_Signal
#110101 : 53
PortE_Signal
#111001 : 57
FTM1_Channel2_Signal
#111010 : 58
FTM2_Channel2_Signal
#111011 : 59
LPTMR0_Signal
#111100 : 60
AlwaysOn60_Signal
#111101 : 61
AlwaysOn61_Signal
#111110 : 62
AlwaysOn62_Signal
#111111 : 63
AlwaysOn63_Signal
0 : Disable_Signal
Disable_Signal
0x1 : TSI_Signal
TSI_Signal
0x2 : LPUART0_Rx_Signal
LPUART0_Rx_Signal
0x3 : LPUART0_Tx_Signal
LPUART0_Tx_Signal
0x4 : LPUART1_Rx_Signal
LPUART1_Rx_Signal
0x5 : LPUART1_Tx_Signal
LPUART1_Tx_Signal
0x6 : LPUART2_Rx_Signal
LPUART2_Rx_Signal
0x7 : LPUART2_Tx_Signal
LPUART2_Tx_Signal
0xA : FlexIO_Channel0_Signal
FlexIO_Channel0_Signal
0xB : FlexIO_Channel1_Signal
FlexIO_Channel1_Signal
0xC : FlexIO_Channel2_Signal
FlexIO_Channel2_Signal
0xD : FlexIO_Channel3_Signal
FlexIO_Channel3_Signal
0xE : LPSPI0_Rx_Signal
LPSPI0_Rx_Signal
0xF : LPSPI0_Tx_Signal
LPSPI0_Tx_Signal
0x10 : LPSPI1_Rx_Signal
LPSPI1_Rx_Signal
0x11 : LPSPI1_Tx_Signal
LPSPI1_Tx_Signal
0x12 : LPI2C0_Rx_Signal
LPI2C0_Rx_Signal
0x13 : LPI2C0_Tx_Signal
LPI2C0_Tx_Signal
0x14 : FTM0_Channel0_Signal
FTM0_Channel0_Signal
0x15 : FTM0_Channel1_Signal
FTM0_Channel1_Signal
0x16 : FTM0_Channel2_Signal
FTM0_Channel2_Signal
0x17 : FTM0_Channel3_Signal
FTM0_Channel3_Signal
0x18 : FTM0_Channel4_Signal
FTM0_Channel4_Signal
0x19 : FTM0_Channel5_Signal
FTM0_Channel5_Signal
0x1A : FTM0_Channel6_Signal
FTM0_Channel6_Signal
0x1B : FTM0_Channel7_Signal
FTM0_Channel7_Signal
0x1C : FTM1_Channel0_Signal
FTM1_Channel0_Signal
0x1D : FTM1_Channel1_Signal
FTM1_Channel1_Signal
0x1E : FTM2_Channel0_Signal
FTM2_Channel0_Signal
0x1F : FTM2_Channel1_Signal
FTM2_Channel1_Signal
0x20 : LPI2C1_Rx_Signal
LPI2C1_Rx_Signal
0x21 : LPI2C1_Tx_Signal
LPI2C1_Tx_Signal
0x28 : ADC0_Signal
ADC0_Signal
0x29 : ADC1_Signal
ADC1_Signal
0x2B : CMP0_Signal
CMP0_Signal
0x2C : CMP1_Signal
CMP1_Signal
0x2E : PDB0_Signal
PDB0_Signal
0x31 : PortA_Signal
PortA_Signal
0x32 : PortB_Signal
PortB_Signal
0x33 : PortC_Signal
PortC_Signal
0x34 : PortD_Signal
PortD_Signal
0x35 : PortE_Signal
PortE_Signal
0x39 : FTM1_Channel2_Signal
FTM1_Channel2_Signal
0x3A : FTM2_Channel2_Signal
FTM2_Channel2_Signal
0x3B : LPTMR0_Signal
LPTMR0_Signal
0x3C : AlwaysOn60_Signal
AlwaysOn60_Signal
0x3D : AlwaysOn61_Signal
AlwaysOn61_Signal
0x3E : AlwaysOn62_Signal
AlwaysOn62_Signal
0x3F : AlwaysOn63_Signal
AlwaysOn63_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
0 : DISABLED
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : ENABLED
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#1 : 1
DMA channel is enabled
0 : DISABLED
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
0x1 : ENABLED
DMA channel is enabled
End of enumeration elements list.
Channel Configuration register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#1 : 1
TSI_Signal
#10 : 2
LPUART0_Rx_Signal
#11 : 3
LPUART0_Tx_Signal
#100 : 4
LPUART1_Rx_Signal
#101 : 5
LPUART1_Tx_Signal
#110 : 6
LPUART2_Rx_Signal
#111 : 7
LPUART2_Tx_Signal
#1010 : 10
FlexIO_Channel0_Signal
#1011 : 11
FlexIO_Channel1_Signal
#1100 : 12
FlexIO_Channel2_Signal
#1101 : 13
FlexIO_Channel3_Signal
#1110 : 14
LPSPI0_Rx_Signal
#1111 : 15
LPSPI0_Tx_Signal
#10000 : 16
LPSPI1_Rx_Signal
#10001 : 17
LPSPI1_Tx_Signal
#10010 : 18
LPI2C0_Rx_Signal
#10011 : 19
LPI2C0_Tx_Signal
#10100 : 20
FTM0_Channel0_Signal
#10101 : 21
FTM0_Channel1_Signal
#10110 : 22
FTM0_Channel2_Signal
#10111 : 23
FTM0_Channel3_Signal
#11000 : 24
FTM0_Channel4_Signal
#11001 : 25
FTM0_Channel5_Signal
#11010 : 26
FTM0_Channel6_Signal
#11011 : 27
FTM0_Channel7_Signal
#11100 : 28
FTM1_Channel0_Signal
#11101 : 29
FTM1_Channel1_Signal
#11110 : 30
FTM2_Channel0_Signal
#11111 : 31
FTM2_Channel1_Signal
#100000 : 32
LPI2C1_Rx_Signal
#100001 : 33
LPI2C1_Tx_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101011 : 43
CMP0_Signal
#101100 : 44
CMP1_Signal
#101110 : 46
PDB0_Signal
#110001 : 49
PortA_Signal
#110010 : 50
PortB_Signal
#110011 : 51
PortC_Signal
#110100 : 52
PortD_Signal
#110101 : 53
PortE_Signal
#111001 : 57
FTM1_Channel2_Signal
#111010 : 58
FTM2_Channel2_Signal
#111011 : 59
LPTMR0_Signal
#111100 : 60
AlwaysOn60_Signal
#111101 : 61
AlwaysOn61_Signal
#111110 : 62
AlwaysOn62_Signal
#111111 : 63
AlwaysOn63_Signal
0 : Disable_Signal
Disable_Signal
0x1 : TSI_Signal
TSI_Signal
0x2 : LPUART0_Rx_Signal
LPUART0_Rx_Signal
0x3 : LPUART0_Tx_Signal
LPUART0_Tx_Signal
0x4 : LPUART1_Rx_Signal
LPUART1_Rx_Signal
0x5 : LPUART1_Tx_Signal
LPUART1_Tx_Signal
0x6 : LPUART2_Rx_Signal
LPUART2_Rx_Signal
0x7 : LPUART2_Tx_Signal
LPUART2_Tx_Signal
0xA : FlexIO_Channel0_Signal
FlexIO_Channel0_Signal
0xB : FlexIO_Channel1_Signal
FlexIO_Channel1_Signal
0xC : FlexIO_Channel2_Signal
FlexIO_Channel2_Signal
0xD : FlexIO_Channel3_Signal
FlexIO_Channel3_Signal
0xE : LPSPI0_Rx_Signal
LPSPI0_Rx_Signal
0xF : LPSPI0_Tx_Signal
LPSPI0_Tx_Signal
0x10 : LPSPI1_Rx_Signal
LPSPI1_Rx_Signal
0x11 : LPSPI1_Tx_Signal
LPSPI1_Tx_Signal
0x12 : LPI2C0_Rx_Signal
LPI2C0_Rx_Signal
0x13 : LPI2C0_Tx_Signal
LPI2C0_Tx_Signal
0x14 : FTM0_Channel0_Signal
FTM0_Channel0_Signal
0x15 : FTM0_Channel1_Signal
FTM0_Channel1_Signal
0x16 : FTM0_Channel2_Signal
FTM0_Channel2_Signal
0x17 : FTM0_Channel3_Signal
FTM0_Channel3_Signal
0x18 : FTM0_Channel4_Signal
FTM0_Channel4_Signal
0x19 : FTM0_Channel5_Signal
FTM0_Channel5_Signal
0x1A : FTM0_Channel6_Signal
FTM0_Channel6_Signal
0x1B : FTM0_Channel7_Signal
FTM0_Channel7_Signal
0x1C : FTM1_Channel0_Signal
FTM1_Channel0_Signal
0x1D : FTM1_Channel1_Signal
FTM1_Channel1_Signal
0x1E : FTM2_Channel0_Signal
FTM2_Channel0_Signal
0x1F : FTM2_Channel1_Signal
FTM2_Channel1_Signal
0x20 : LPI2C1_Rx_Signal
LPI2C1_Rx_Signal
0x21 : LPI2C1_Tx_Signal
LPI2C1_Tx_Signal
0x28 : ADC0_Signal
ADC0_Signal
0x29 : ADC1_Signal
ADC1_Signal
0x2B : CMP0_Signal
CMP0_Signal
0x2C : CMP1_Signal
CMP1_Signal
0x2E : PDB0_Signal
PDB0_Signal
0x31 : PortA_Signal
PortA_Signal
0x32 : PortB_Signal
PortB_Signal
0x33 : PortC_Signal
PortC_Signal
0x34 : PortD_Signal
PortD_Signal
0x35 : PortE_Signal
PortE_Signal
0x39 : FTM1_Channel2_Signal
FTM1_Channel2_Signal
0x3A : FTM2_Channel2_Signal
FTM2_Channel2_Signal
0x3B : LPTMR0_Signal
LPTMR0_Signal
0x3C : AlwaysOn60_Signal
AlwaysOn60_Signal
0x3D : AlwaysOn61_Signal
AlwaysOn61_Signal
0x3E : AlwaysOn62_Signal
AlwaysOn62_Signal
0x3F : AlwaysOn63_Signal
AlwaysOn63_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
0 : DISABLED
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : ENABLED
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#1 : 1
DMA channel is enabled
0 : DISABLED
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
0x1 : ENABLED
DMA channel is enabled
End of enumeration elements list.
Channel Configuration register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#1 : 1
TSI_Signal
#10 : 2
LPUART0_Rx_Signal
#11 : 3
LPUART0_Tx_Signal
#100 : 4
LPUART1_Rx_Signal
#101 : 5
LPUART1_Tx_Signal
#110 : 6
LPUART2_Rx_Signal
#111 : 7
LPUART2_Tx_Signal
#1010 : 10
FlexIO_Channel0_Signal
#1011 : 11
FlexIO_Channel1_Signal
#1100 : 12
FlexIO_Channel2_Signal
#1101 : 13
FlexIO_Channel3_Signal
#1110 : 14
LPSPI0_Rx_Signal
#1111 : 15
LPSPI0_Tx_Signal
#10000 : 16
LPSPI1_Rx_Signal
#10001 : 17
LPSPI1_Tx_Signal
#10010 : 18
LPI2C0_Rx_Signal
#10011 : 19
LPI2C0_Tx_Signal
#10100 : 20
FTM0_Channel0_Signal
#10101 : 21
FTM0_Channel1_Signal
#10110 : 22
FTM0_Channel2_Signal
#10111 : 23
FTM0_Channel3_Signal
#11000 : 24
FTM0_Channel4_Signal
#11001 : 25
FTM0_Channel5_Signal
#11010 : 26
FTM0_Channel6_Signal
#11011 : 27
FTM0_Channel7_Signal
#11100 : 28
FTM1_Channel0_Signal
#11101 : 29
FTM1_Channel1_Signal
#11110 : 30
FTM2_Channel0_Signal
#11111 : 31
FTM2_Channel1_Signal
#100000 : 32
LPI2C1_Rx_Signal
#100001 : 33
LPI2C1_Tx_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101011 : 43
CMP0_Signal
#101100 : 44
CMP1_Signal
#101110 : 46
PDB0_Signal
#110001 : 49
PortA_Signal
#110010 : 50
PortB_Signal
#110011 : 51
PortC_Signal
#110100 : 52
PortD_Signal
#110101 : 53
PortE_Signal
#111001 : 57
FTM1_Channel2_Signal
#111010 : 58
FTM2_Channel2_Signal
#111011 : 59
LPTMR0_Signal
#111100 : 60
AlwaysOn60_Signal
#111101 : 61
AlwaysOn61_Signal
#111110 : 62
AlwaysOn62_Signal
#111111 : 63
AlwaysOn63_Signal
0 : Disable_Signal
Disable_Signal
0x1 : TSI_Signal
TSI_Signal
0x2 : LPUART0_Rx_Signal
LPUART0_Rx_Signal
0x3 : LPUART0_Tx_Signal
LPUART0_Tx_Signal
0x4 : LPUART1_Rx_Signal
LPUART1_Rx_Signal
0x5 : LPUART1_Tx_Signal
LPUART1_Tx_Signal
0x6 : LPUART2_Rx_Signal
LPUART2_Rx_Signal
0x7 : LPUART2_Tx_Signal
LPUART2_Tx_Signal
0xA : FlexIO_Channel0_Signal
FlexIO_Channel0_Signal
0xB : FlexIO_Channel1_Signal
FlexIO_Channel1_Signal
0xC : FlexIO_Channel2_Signal
FlexIO_Channel2_Signal
0xD : FlexIO_Channel3_Signal
FlexIO_Channel3_Signal
0xE : LPSPI0_Rx_Signal
LPSPI0_Rx_Signal
0xF : LPSPI0_Tx_Signal
LPSPI0_Tx_Signal
0x10 : LPSPI1_Rx_Signal
LPSPI1_Rx_Signal
0x11 : LPSPI1_Tx_Signal
LPSPI1_Tx_Signal
0x12 : LPI2C0_Rx_Signal
LPI2C0_Rx_Signal
0x13 : LPI2C0_Tx_Signal
LPI2C0_Tx_Signal
0x14 : FTM0_Channel0_Signal
FTM0_Channel0_Signal
0x15 : FTM0_Channel1_Signal
FTM0_Channel1_Signal
0x16 : FTM0_Channel2_Signal
FTM0_Channel2_Signal
0x17 : FTM0_Channel3_Signal
FTM0_Channel3_Signal
0x18 : FTM0_Channel4_Signal
FTM0_Channel4_Signal
0x19 : FTM0_Channel5_Signal
FTM0_Channel5_Signal
0x1A : FTM0_Channel6_Signal
FTM0_Channel6_Signal
0x1B : FTM0_Channel7_Signal
FTM0_Channel7_Signal
0x1C : FTM1_Channel0_Signal
FTM1_Channel0_Signal
0x1D : FTM1_Channel1_Signal
FTM1_Channel1_Signal
0x1E : FTM2_Channel0_Signal
FTM2_Channel0_Signal
0x1F : FTM2_Channel1_Signal
FTM2_Channel1_Signal
0x20 : LPI2C1_Rx_Signal
LPI2C1_Rx_Signal
0x21 : LPI2C1_Tx_Signal
LPI2C1_Tx_Signal
0x28 : ADC0_Signal
ADC0_Signal
0x29 : ADC1_Signal
ADC1_Signal
0x2B : CMP0_Signal
CMP0_Signal
0x2C : CMP1_Signal
CMP1_Signal
0x2E : PDB0_Signal
PDB0_Signal
0x31 : PortA_Signal
PortA_Signal
0x32 : PortB_Signal
PortB_Signal
0x33 : PortC_Signal
PortC_Signal
0x34 : PortD_Signal
PortD_Signal
0x35 : PortE_Signal
PortE_Signal
0x39 : FTM1_Channel2_Signal
FTM1_Channel2_Signal
0x3A : FTM2_Channel2_Signal
FTM2_Channel2_Signal
0x3B : LPTMR0_Signal
LPTMR0_Signal
0x3C : AlwaysOn60_Signal
AlwaysOn60_Signal
0x3D : AlwaysOn61_Signal
AlwaysOn61_Signal
0x3E : AlwaysOn62_Signal
AlwaysOn62_Signal
0x3F : AlwaysOn63_Signal
AlwaysOn63_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
0 : DISABLED
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : ENABLED
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#1 : 1
DMA channel is enabled
0 : DISABLED
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
0x1 : ENABLED
DMA channel is enabled
End of enumeration elements list.
Channel Configuration register
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#1 : 1
TSI_Signal
#10 : 2
LPUART0_Rx_Signal
#11 : 3
LPUART0_Tx_Signal
#100 : 4
LPUART1_Rx_Signal
#101 : 5
LPUART1_Tx_Signal
#110 : 6
LPUART2_Rx_Signal
#111 : 7
LPUART2_Tx_Signal
#1010 : 10
FlexIO_Channel0_Signal
#1011 : 11
FlexIO_Channel1_Signal
#1100 : 12
FlexIO_Channel2_Signal
#1101 : 13
FlexIO_Channel3_Signal
#1110 : 14
LPSPI0_Rx_Signal
#1111 : 15
LPSPI0_Tx_Signal
#10000 : 16
LPSPI1_Rx_Signal
#10001 : 17
LPSPI1_Tx_Signal
#10010 : 18
LPI2C0_Rx_Signal
#10011 : 19
LPI2C0_Tx_Signal
#10100 : 20
FTM0_Channel0_Signal
#10101 : 21
FTM0_Channel1_Signal
#10110 : 22
FTM0_Channel2_Signal
#10111 : 23
FTM0_Channel3_Signal
#11000 : 24
FTM0_Channel4_Signal
#11001 : 25
FTM0_Channel5_Signal
#11010 : 26
FTM0_Channel6_Signal
#11011 : 27
FTM0_Channel7_Signal
#11100 : 28
FTM1_Channel0_Signal
#11101 : 29
FTM1_Channel1_Signal
#11110 : 30
FTM2_Channel0_Signal
#11111 : 31
FTM2_Channel1_Signal
#100000 : 32
LPI2C1_Rx_Signal
#100001 : 33
LPI2C1_Tx_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101011 : 43
CMP0_Signal
#101100 : 44
CMP1_Signal
#101110 : 46
PDB0_Signal
#110001 : 49
PortA_Signal
#110010 : 50
PortB_Signal
#110011 : 51
PortC_Signal
#110100 : 52
PortD_Signal
#110101 : 53
PortE_Signal
#111001 : 57
FTM1_Channel2_Signal
#111010 : 58
FTM2_Channel2_Signal
#111011 : 59
LPTMR0_Signal
#111100 : 60
AlwaysOn60_Signal
#111101 : 61
AlwaysOn61_Signal
#111110 : 62
AlwaysOn62_Signal
#111111 : 63
AlwaysOn63_Signal
0 : Disable_Signal
Disable_Signal
0x1 : TSI_Signal
TSI_Signal
0x2 : LPUART0_Rx_Signal
LPUART0_Rx_Signal
0x3 : LPUART0_Tx_Signal
LPUART0_Tx_Signal
0x4 : LPUART1_Rx_Signal
LPUART1_Rx_Signal
0x5 : LPUART1_Tx_Signal
LPUART1_Tx_Signal
0x6 : LPUART2_Rx_Signal
LPUART2_Rx_Signal
0x7 : LPUART2_Tx_Signal
LPUART2_Tx_Signal
0xA : FlexIO_Channel0_Signal
FlexIO_Channel0_Signal
0xB : FlexIO_Channel1_Signal
FlexIO_Channel1_Signal
0xC : FlexIO_Channel2_Signal
FlexIO_Channel2_Signal
0xD : FlexIO_Channel3_Signal
FlexIO_Channel3_Signal
0xE : LPSPI0_Rx_Signal
LPSPI0_Rx_Signal
0xF : LPSPI0_Tx_Signal
LPSPI0_Tx_Signal
0x10 : LPSPI1_Rx_Signal
LPSPI1_Rx_Signal
0x11 : LPSPI1_Tx_Signal
LPSPI1_Tx_Signal
0x12 : LPI2C0_Rx_Signal
LPI2C0_Rx_Signal
0x13 : LPI2C0_Tx_Signal
LPI2C0_Tx_Signal
0x14 : FTM0_Channel0_Signal
FTM0_Channel0_Signal
0x15 : FTM0_Channel1_Signal
FTM0_Channel1_Signal
0x16 : FTM0_Channel2_Signal
FTM0_Channel2_Signal
0x17 : FTM0_Channel3_Signal
FTM0_Channel3_Signal
0x18 : FTM0_Channel4_Signal
FTM0_Channel4_Signal
0x19 : FTM0_Channel5_Signal
FTM0_Channel5_Signal
0x1A : FTM0_Channel6_Signal
FTM0_Channel6_Signal
0x1B : FTM0_Channel7_Signal
FTM0_Channel7_Signal
0x1C : FTM1_Channel0_Signal
FTM1_Channel0_Signal
0x1D : FTM1_Channel1_Signal
FTM1_Channel1_Signal
0x1E : FTM2_Channel0_Signal
FTM2_Channel0_Signal
0x1F : FTM2_Channel1_Signal
FTM2_Channel1_Signal
0x20 : LPI2C1_Rx_Signal
LPI2C1_Rx_Signal
0x21 : LPI2C1_Tx_Signal
LPI2C1_Tx_Signal
0x28 : ADC0_Signal
ADC0_Signal
0x29 : ADC1_Signal
ADC1_Signal
0x2B : CMP0_Signal
CMP0_Signal
0x2C : CMP1_Signal
CMP1_Signal
0x2E : PDB0_Signal
PDB0_Signal
0x31 : PortA_Signal
PortA_Signal
0x32 : PortB_Signal
PortB_Signal
0x33 : PortC_Signal
PortC_Signal
0x34 : PortD_Signal
PortD_Signal
0x35 : PortE_Signal
PortE_Signal
0x39 : FTM1_Channel2_Signal
FTM1_Channel2_Signal
0x3A : FTM2_Channel2_Signal
FTM2_Channel2_Signal
0x3B : LPTMR0_Signal
LPTMR0_Signal
0x3C : AlwaysOn60_Signal
AlwaysOn60_Signal
0x3D : AlwaysOn61_Signal
AlwaysOn61_Signal
0x3E : AlwaysOn62_Signal
AlwaysOn62_Signal
0x3F : AlwaysOn63_Signal
AlwaysOn63_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
0 : DISABLED
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : ENABLED
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#1 : 1
DMA channel is enabled
0 : DISABLED
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
0x1 : ENABLED
DMA channel is enabled
End of enumeration elements list.
Channel Configuration register
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable_Signal
#1 : 1
TSI_Signal
#10 : 2
LPUART0_Rx_Signal
#11 : 3
LPUART0_Tx_Signal
#100 : 4
LPUART1_Rx_Signal
#101 : 5
LPUART1_Tx_Signal
#110 : 6
LPUART2_Rx_Signal
#111 : 7
LPUART2_Tx_Signal
#1010 : 10
FlexIO_Channel0_Signal
#1011 : 11
FlexIO_Channel1_Signal
#1100 : 12
FlexIO_Channel2_Signal
#1101 : 13
FlexIO_Channel3_Signal
#1110 : 14
LPSPI0_Rx_Signal
#1111 : 15
LPSPI0_Tx_Signal
#10000 : 16
LPSPI1_Rx_Signal
#10001 : 17
LPSPI1_Tx_Signal
#10010 : 18
LPI2C0_Rx_Signal
#10011 : 19
LPI2C0_Tx_Signal
#10100 : 20
FTM0_Channel0_Signal
#10101 : 21
FTM0_Channel1_Signal
#10110 : 22
FTM0_Channel2_Signal
#10111 : 23
FTM0_Channel3_Signal
#11000 : 24
FTM0_Channel4_Signal
#11001 : 25
FTM0_Channel5_Signal
#11010 : 26
FTM0_Channel6_Signal
#11011 : 27
FTM0_Channel7_Signal
#11100 : 28
FTM1_Channel0_Signal
#11101 : 29
FTM1_Channel1_Signal
#11110 : 30
FTM2_Channel0_Signal
#11111 : 31
FTM2_Channel1_Signal
#100000 : 32
LPI2C1_Rx_Signal
#100001 : 33
LPI2C1_Tx_Signal
#101000 : 40
ADC0_Signal
#101001 : 41
ADC1_Signal
#101011 : 43
CMP0_Signal
#101100 : 44
CMP1_Signal
#101110 : 46
PDB0_Signal
#110001 : 49
PortA_Signal
#110010 : 50
PortB_Signal
#110011 : 51
PortC_Signal
#110100 : 52
PortD_Signal
#110101 : 53
PortE_Signal
#111001 : 57
FTM1_Channel2_Signal
#111010 : 58
FTM2_Channel2_Signal
#111011 : 59
LPTMR0_Signal
#111100 : 60
AlwaysOn60_Signal
#111101 : 61
AlwaysOn61_Signal
#111110 : 62
AlwaysOn62_Signal
#111111 : 63
AlwaysOn63_Signal
0 : Disable_Signal
Disable_Signal
0x1 : TSI_Signal
TSI_Signal
0x2 : LPUART0_Rx_Signal
LPUART0_Rx_Signal
0x3 : LPUART0_Tx_Signal
LPUART0_Tx_Signal
0x4 : LPUART1_Rx_Signal
LPUART1_Rx_Signal
0x5 : LPUART1_Tx_Signal
LPUART1_Tx_Signal
0x6 : LPUART2_Rx_Signal
LPUART2_Rx_Signal
0x7 : LPUART2_Tx_Signal
LPUART2_Tx_Signal
0xA : FlexIO_Channel0_Signal
FlexIO_Channel0_Signal
0xB : FlexIO_Channel1_Signal
FlexIO_Channel1_Signal
0xC : FlexIO_Channel2_Signal
FlexIO_Channel2_Signal
0xD : FlexIO_Channel3_Signal
FlexIO_Channel3_Signal
0xE : LPSPI0_Rx_Signal
LPSPI0_Rx_Signal
0xF : LPSPI0_Tx_Signal
LPSPI0_Tx_Signal
0x10 : LPSPI1_Rx_Signal
LPSPI1_Rx_Signal
0x11 : LPSPI1_Tx_Signal
LPSPI1_Tx_Signal
0x12 : LPI2C0_Rx_Signal
LPI2C0_Rx_Signal
0x13 : LPI2C0_Tx_Signal
LPI2C0_Tx_Signal
0x14 : FTM0_Channel0_Signal
FTM0_Channel0_Signal
0x15 : FTM0_Channel1_Signal
FTM0_Channel1_Signal
0x16 : FTM0_Channel2_Signal
FTM0_Channel2_Signal
0x17 : FTM0_Channel3_Signal
FTM0_Channel3_Signal
0x18 : FTM0_Channel4_Signal
FTM0_Channel4_Signal
0x19 : FTM0_Channel5_Signal
FTM0_Channel5_Signal
0x1A : FTM0_Channel6_Signal
FTM0_Channel6_Signal
0x1B : FTM0_Channel7_Signal
FTM0_Channel7_Signal
0x1C : FTM1_Channel0_Signal
FTM1_Channel0_Signal
0x1D : FTM1_Channel1_Signal
FTM1_Channel1_Signal
0x1E : FTM2_Channel0_Signal
FTM2_Channel0_Signal
0x1F : FTM2_Channel1_Signal
FTM2_Channel1_Signal
0x20 : LPI2C1_Rx_Signal
LPI2C1_Rx_Signal
0x21 : LPI2C1_Tx_Signal
LPI2C1_Tx_Signal
0x28 : ADC0_Signal
ADC0_Signal
0x29 : ADC1_Signal
ADC1_Signal
0x2B : CMP0_Signal
CMP0_Signal
0x2C : CMP1_Signal
CMP1_Signal
0x2E : PDB0_Signal
PDB0_Signal
0x31 : PortA_Signal
PortA_Signal
0x32 : PortB_Signal
PortB_Signal
0x33 : PortC_Signal
PortC_Signal
0x34 : PortD_Signal
PortD_Signal
0x35 : PortE_Signal
PortE_Signal
0x39 : FTM1_Channel2_Signal
FTM1_Channel2_Signal
0x3A : FTM2_Channel2_Signal
FTM2_Channel2_Signal
0x3B : LPTMR0_Signal
LPTMR0_Signal
0x3C : AlwaysOn60_Signal
AlwaysOn60_Signal
0x3D : AlwaysOn61_Signal
AlwaysOn61_Signal
0x3E : AlwaysOn62_Signal
AlwaysOn62_Signal
0x3F : AlwaysOn63_Signal
AlwaysOn63_Signal
End of enumeration elements list.
TRIG : DMA Channel Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#1 : 1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
0 : DISABLED
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
0x1 : ENABLED
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#1 : 1
DMA channel is enabled
0 : DISABLED
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
0x1 : ENABLED
DMA channel is enabled
End of enumeration elements list.
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