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FMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x280 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PFAPR

TAGVDW0S0

TAGVDW1S0

TAGVDW2S0

TAGVDW3S0

TAGVDW0S1

TAGVDW1S1

TAGVDW2S1

TAGVDW3S1

PFB0CR

DATAW0S0U

DATAW0S0L

TAGVDW0S2

DATAW1S0U

DATAW1S0L

TAGVDW1S2

DATAW2S0U

DATAW2S0L

TAGVDW2S2

DATAW3S0U

DATAW3S0L

TAGVDW3S2

TAGVDW0S3

TAGVDW1S3

TAGVDW2S3

TAGVDW3S3

DATAW0S1U

DATAW0S1L

DATAW1S1U

DATAW1S1L

DATAW2S1U

DATAW2S1L

DATAW3S1U

DATAW3S1L

PFB1CR

DATAW0S2U

DATAW0S2L

DATAW1S2U

DATAW1S2L

DATAW2S2U

DATAW2S2L

DATAW3S2U

DATAW3S2L

DATAW0S3U

DATAW0S3L

DATAW1S3U

DATAW1S3L

DATAW2S3U

DATAW2S3L

DATAW3S3U

DATAW3S3L


PFAPR

Flash Access Protection Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFAPR PFAPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0AP M1AP M2AP M3AP RESERVED M0PFD M1PFD M2PFD M3PFD RESERVED RESERVED

M0AP : Master 0 Access Protection
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

No access may be performed by this master

#01 : 01

Only read accesses may be performed by this master

#10 : 10

Only write accesses may be performed by this master

#11 : 11

Both read and write accesses may be performed by this master

End of enumeration elements list.

M1AP : Master 1 Access Protection
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

No access may be performed by this master

#01 : 01

Only read accesses may be performed by this master

#10 : 10

Only write accesses may be performed by this master

#11 : 11

Both read and write accesses may be performed by this master

End of enumeration elements list.

M2AP : Master 2 Access Protection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 00

No access may be performed by this master

#01 : 01

Only read accesses may be performed by this master

#10 : 10

Only write accesses may be performed by this master

#11 : 11

Both read and write accesses may be performed by this master

End of enumeration elements list.

M3AP : Master 3 Access Protection
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 00

No access may be performed by this master

#01 : 01

Only read accesses may be performed by this master

#10 : 10

Only write accesses may be performed by this master

#11 : 11

Both read and write accesses may be performed by this master

End of enumeration elements list.

RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only

M0PFD : Master 0 Prefetch Disable
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Prefetching for this master is enabled.

#1 : 1

Prefetching for this master is disabled.

End of enumeration elements list.

M1PFD : Master 1 Prefetch Disable
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Prefetching for this master is enabled.

#1 : 1

Prefetching for this master is disabled.

End of enumeration elements list.

M2PFD : Master 2 Prefetch Disable
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Prefetching for this master is enabled.

#1 : 1

Prefetching for this master is disabled.

End of enumeration elements list.

M3PFD : Master 3 Prefetch Disable
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Prefetching for this master is enabled.

#1 : 1

Prefetching for this master is disabled.

End of enumeration elements list.

RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only

RESERVED : no description available
bits : 20 - 23 (4 bit)
access : read-only


TAGVDW0S0

Cache Tag Storage
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW0S0 TAGVDW0S0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid RESERVED RESERVED tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW1S0

Cache Tag Storage
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW1S0 TAGVDW1S0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid RESERVED RESERVED tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW2S0

Cache Tag Storage
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW2S0 TAGVDW2S0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid RESERVED RESERVED tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW3S0

Cache Tag Storage
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW3S0 TAGVDW3S0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid RESERVED RESERVED tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW0S1

Cache Tag Storage
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW0S1 TAGVDW0S1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid RESERVED RESERVED tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW1S1

Cache Tag Storage
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW1S1 TAGVDW1S1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid RESERVED RESERVED tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW2S1

Cache Tag Storage
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW2S1 TAGVDW2S1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid RESERVED RESERVED tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW3S1

Cache Tag Storage
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW3S1 TAGVDW3S1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid RESERVED RESERVED tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


PFB0CR

Flash Bank 0 Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFB0CR PFB0CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B0SEBE B0IPE B0DPE B0ICE B0DCE CRC RESERVED RESERVED B0MW S_B_INV CINV_WAY CLCK_WAY B0RWSC

B0SEBE : Bank 0 Single Entry Buffer Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Single entry buffer is disabled.

#1 : 1

Single entry buffer is enabled.

End of enumeration elements list.

B0IPE : Bank 0 Instruction Prefetch Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not prefetch in response to instruction fetches.

#1 : 1

Enable prefetches in response to instruction fetches.

End of enumeration elements list.

B0DPE : Bank 0 Data Prefetch Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not prefetch in response to data references.

#1 : 1

Enable prefetches in response to data references.

End of enumeration elements list.

B0ICE : Bank 0 Instruction Cache Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not cache instruction fetches.

#1 : 1

Cache instruction fetches.

End of enumeration elements list.

B0DCE : Bank 0 Data Cache Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Do not cache data references.

#1 : 1

Cache data references.

End of enumeration elements list.

CRC : Cache Replacement Control
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

#000 : 000

LRU replacement algorithm per set across all four ways

#001 : 001

Reserved

#010 : 010

Independent LRU with ways [0-1] for ifetches, [2-3] for data

#011 : 011

Independent LRU with ways [0-2] for ifetches, [3] for data

#1xx : 1xx

Reserved

End of enumeration elements list.

RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only

RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only

B0MW : Bank 0 Memory Width
bits : 17 - 18 (2 bit)
access : read-only

Enumeration:

#00 : 00

32 bits

#01 : 01

64 bits

#1x : 1x

Reserved

End of enumeration elements list.

S_B_INV : Invalidate Prefetch Speculation Buffer
bits : 19 - 19 (1 bit)
access : write-only

Enumeration:

#0 : 0

Speculation buffer and single entry buffer are not affected.

#1 : 1

Invalidate (clear) speculation buffer and single entry buffer.

End of enumeration elements list.

CINV_WAY : Cache Invalidate Way x
bits : 20 - 23 (4 bit)
access : write-only

Enumeration:

#0 : 0

No cache way invalidation for the corresponding cache

#1 : 1

Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected

End of enumeration elements list.

CLCK_WAY : Cache Lock Way x
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

#0 : 0

Cache way is unlocked and may be displaced

#1 : 1

Cache way is locked and its contents are not displaced

End of enumeration elements list.

B0RWSC : Bank 0 Read Wait State Control
bits : 28 - 31 (4 bit)
access : read-only


DATAW0S0U

Cache Data Storage (upper word)
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S0U DATAW0S0U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S0L

Cache Data Storage (lower word)
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S0L DATAW0S0L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW0S2

Cache Tag Storage
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW0S2 TAGVDW0S2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid RESERVED RESERVED tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


DATAW1S0U

Cache Data Storage (upper word)
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S0U DATAW1S0U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S0L

Cache Data Storage (lower word)
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S0L DATAW1S0L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW1S2

Cache Tag Storage
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW1S2 TAGVDW1S2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid RESERVED RESERVED tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


DATAW2S0U

Cache Data Storage (upper word)
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S0U DATAW2S0U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S0L

Cache Data Storage (lower word)
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S0L DATAW2S0L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW2S2

Cache Tag Storage
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW2S2 TAGVDW2S2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid RESERVED RESERVED tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


DATAW3S0U

Cache Data Storage (upper word)
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S0U DATAW3S0U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S0L

Cache Data Storage (lower word)
address_offset : 0x4C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S0L DATAW3S0L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


TAGVDW3S2

Cache Tag Storage
address_offset : 0x4CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW3S2 TAGVDW3S2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid RESERVED RESERVED tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW0S3

Cache Tag Storage
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW0S3 TAGVDW0S3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid RESERVED RESERVED tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW1S3

Cache Tag Storage
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW1S3 TAGVDW1S3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid RESERVED RESERVED tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW2S3

Cache Tag Storage
address_offset : 0x5B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW2S3 TAGVDW2S3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid RESERVED RESERVED tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


TAGVDW3S3

Cache Tag Storage
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAGVDW3S3 TAGVDW3S3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 valid RESERVED RESERVED tag

valid : 1-bit valid for cache entry
bits : 0 - 0 (1 bit)
access : read-write

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

RESERVED : no description available
bits : 1 - 5 (5 bit)
access : read-only

tag : 13-bit tag for cache entry
bits : 6 - 18 (13 bit)
access : read-write


DATAW0S1U

Cache Data Storage (upper word)
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S1U DATAW0S1U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S1L

Cache Data Storage (lower word)
address_offset : 0x614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S1L DATAW0S1L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S1U

Cache Data Storage (upper word)
address_offset : 0x668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S1U DATAW1S1U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S1L

Cache Data Storage (lower word)
address_offset : 0x674 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S1L DATAW1S1L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S1U

Cache Data Storage (upper word)
address_offset : 0x6C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S1U DATAW2S1U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S1L

Cache Data Storage (lower word)
address_offset : 0x6D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S1L DATAW2S1L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S1U

Cache Data Storage (upper word)
address_offset : 0x728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S1U DATAW3S1U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S1L

Cache Data Storage (lower word)
address_offset : 0x734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S1L DATAW3S1L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


PFB1CR

Flash Bank 1 Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PFB1CR PFB1CR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED RESERVED RESERVED RESERVED RESERVED B1MW B1RWSC

RESERVED : no description available
bits : 0 - 4 (5 bit)
access : read-only

RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-only

RESERVED : no description available
bits : 8 - 15 (8 bit)
access : read-only

RESERVED : no description available
bits : 16 - 16 (1 bit)
access : read-only

RESERVED : no description available
bits : 16 - 16 (1 bit)
access : read-only

B1MW : Bank 1 Memory Width
bits : 17 - 18 (2 bit)
access : read-only

Enumeration:

#00 : 00

32 bits

#01 : 01

64 bits

#10 : 10

Reserved

#11 : 11

16 bits

End of enumeration elements list.

B1RWSC : Bank 1 Read Wait State Control
bits : 28 - 31 (4 bit)
access : read-only


DATAW0S2U

Cache Data Storage (upper word)
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S2U DATAW0S2U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S2L

Cache Data Storage (lower word)
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S2L DATAW0S2L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S2U

Cache Data Storage (upper word)
address_offset : 0x898 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S2U DATAW1S2U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S2L

Cache Data Storage (lower word)
address_offset : 0x8A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S2L DATAW1S2L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S2U

Cache Data Storage (upper word)
address_offset : 0x918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S2U DATAW2S2U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S2L

Cache Data Storage (lower word)
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S2L DATAW2S2L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S2U

Cache Data Storage (upper word)
address_offset : 0x998 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S2U DATAW3S2U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S2L

Cache Data Storage (lower word)
address_offset : 0x9A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S2L DATAW3S2L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S3U

Cache Data Storage (upper word)
address_offset : 0xA30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S3U DATAW0S3U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW0S3L

Cache Data Storage (lower word)
address_offset : 0xA44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW0S3L DATAW0S3L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S3U

Cache Data Storage (upper word)
address_offset : 0xAD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S3U DATAW1S3U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW1S3L

Cache Data Storage (lower word)
address_offset : 0xAE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW1S3L DATAW1S3L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S3U

Cache Data Storage (upper word)
address_offset : 0xB70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S3U DATAW2S3U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW2S3L

Cache Data Storage (lower word)
address_offset : 0xB84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW2S3L DATAW2S3L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S3U

Cache Data Storage (upper word)
address_offset : 0xC10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S3U DATAW3S3U read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [63:32] of data entry
bits : 0 - 31 (32 bit)
access : read-write


DATAW3S3L

Cache Data Storage (lower word)
address_offset : 0xC24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAW3S3L DATAW3S3L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data

data : Bits [31:0] of data entry
bits : 0 - 31 (32 bit)
access : read-write



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