Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x410 byte (0x0)
mem_usage : registers
protection : not protected
Processor X Type Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RYPZ : Processor x Revision
bits : 0 - 7 (8 bit)
access : read-only
PERSONALITY : Processor x Personality
bits : 8 - 31 (24 bit)
access : read-only
On-Chip Memory Descriptor Register
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCMC0 : OCMEM Control Field 0
bits : 0 - 3 (4 bit)
access : read-write
OCMC1 : OCMEM Control Field 1
bits : 4 - 7 (4 bit)
access : read-write
OCMC2 : OCMEM Control Field 2
bits : 8 - 11 (4 bit)
access : read-write
OCMPU : OCMEM Memory Protection Unit
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
OCMEMn is not protected by an MPU.
#1 : 1
OCMEMn is protected by an MPU.
0 : OCMPU_0
OCMEMn is not protected by an MPU.
0x1 : OCMPU_1
OCMEMn is protected by an MPU.
End of enumeration elements list.
OCMT : OCMEM Type. This field defines the type of the on-chip memory:
bits : 13 - 15 (3 bit)
access : read-only
Enumeration:
#011 : 011
OCMEMn is a ROM.
#100 : 100
OCMEMn is a program flash.
#101 : 101
OCMEMn is a data flash.
#110 : 110
OCMEMn is an EEE.
0x3 : OCMT_3
OCMEMn is a ROM.
0x4 : OCMT_4
OCMEMn is a program flash.
0x5 : OCMT_5
OCMEMn is a data flash.
0x6 : OCMT_6
OCMEMn is an EEE.
End of enumeration elements list.
RO : Read-Only
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
writes to the OCMDRn[11:0] are allowed
#1 : 1
writes to the OCMDRn[11:0] are ignored
0 : RO_0
writes to the OCMDRn[11:0] are allowed
0x1 : RO_1
writes to the OCMDRn[11:0] are ignored
End of enumeration elements list.
OCMW : OCMEM datapath Width. This read-only field defines the width of the on-chip memory:
bits : 17 - 19 (3 bit)
access : read-only
Enumeration:
#010 : 010
OCMEMn 32-bits wide
#011 : 011
OCMEMn 64-bits wide
#100 : 100
OCMEMn 128-bits wide
#101 : 101
OCMEMn 256-bits wide
0x2 : OCMW_2
OCMEMn 32-bits wide
0x3 : OCMW_3
OCMEMn 64-bits wide
0x4 : OCMW_4
OCMEMn 128-bits wide
0x5 : OCMW_5
OCMEMn 256-bits wide
End of enumeration elements list.
OCMSZ : OCMEM Size
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
#0000 : 0000
no OCMEMn
#0011 : 0011
4KB OCMEMn
#0100 : 0100
8KB OCMEMn
#0101 : 0101
16KB OCMEMn
#0110 : 0110
32KB OCMEMn
#0111 : 0111
64KB OCMEMn
#1000 : 1000
128KB OCMEMn
#1001 : 1001
256KB OCMEMn
#1010 : 1010
512KB OCMEMn
#1011 : 1011
1024KB OCMEMn
#1100 : 1100
2048KB OCMEMn
#1101 : 1101
4096KB OCMEMn
#1110 : 1110
8192KB OCMEMn
#1111 : 1111
16384KB OCMEMn
0 : OCMSZ_0
no OCMEMn
0x3 : OCMSZ_3
4KB OCMEMn
0x4 : OCMSZ_4
8KB OCMEMn
0x5 : OCMSZ_5
16KB OCMEMn
0x6 : OCMSZ_6
32KB OCMEMn
0x7 : OCMSZ_7
64KB OCMEMn
0x8 : OCMSZ_8
128KB OCMEMn
0x9 : OCMSZ_9
256KB OCMEMn
0xA : OCMSZ_10
512KB OCMEMn
0xB : OCMSZ_11
1024KB OCMEMn
0xC : OCMSZ_12
2048KB OCMEMn
0xD : OCMSZ_13
4096KB OCMEMn
0xE : OCMSZ_14
8192KB OCMEMn
0xF : OCMSZ_15
16384KB OCMEMn
End of enumeration elements list.
OCMSZH : OCMEM Size "Hole"
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
#0 : 0
OCMEMn is a power-of-2 capacity.
#1 : 1
OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
0 : OCMSZH_0
OCMEMn is a power-of-2 capacity.
0x1 : OCMSZH_1
OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
End of enumeration elements list.
V : OCMEM Valid bit. This read-only field defines the validity (presence) of the on-chip memory
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
OCMEMn is not present.
#1 : 1
OCMEMn is present.
0 : V_0
OCMEMn is not present.
0x1 : V_1
OCMEMn is present.
End of enumeration elements list.
Processor 0 Configuration Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ICSZ : Level 1 Instruction Cache Size
bits : 24 - 31 (8 bit)
access : read-only
On-Chip Memory Descriptor Register
address_offset : 0x1418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCMC0 : OCMEM Control Field 0
bits : 0 - 3 (4 bit)
access : read-write
OCMC1 : OCMEM Control Field 1
bits : 4 - 7 (4 bit)
access : read-write
OCMC2 : OCMEM Control Field 2
bits : 8 - 11 (4 bit)
access : read-write
OCMPU : OCMEM Memory Protection Unit
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
OCMEMn is not protected by an MPU.
#1 : 1
OCMEMn is protected by an MPU.
0 : OCMPU_0
OCMEMn is not protected by an MPU.
0x1 : OCMPU_1
OCMEMn is protected by an MPU.
End of enumeration elements list.
OCMT : OCMEM Type. This field defines the type of the on-chip memory:
bits : 13 - 15 (3 bit)
access : read-only
Enumeration:
#011 : 011
OCMEMn is a ROM.
#100 : 100
OCMEMn is a program flash.
#101 : 101
OCMEMn is a data flash.
#110 : 110
OCMEMn is an EEE.
0x3 : OCMT_3
OCMEMn is a ROM.
0x4 : OCMT_4
OCMEMn is a program flash.
0x5 : OCMT_5
OCMEMn is a data flash.
0x6 : OCMT_6
OCMEMn is an EEE.
End of enumeration elements list.
RO : Read-Only
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
writes to the OCMDRn[11:0] are allowed
#1 : 1
writes to the OCMDRn[11:0] are ignored
0 : RO_0
writes to the OCMDRn[11:0] are allowed
0x1 : RO_1
writes to the OCMDRn[11:0] are ignored
End of enumeration elements list.
OCMW : OCMEM datapath Width. This read-only field defines the width of the on-chip memory:
bits : 17 - 19 (3 bit)
access : read-only
Enumeration:
#010 : 010
OCMEMn 32-bits wide
#011 : 011
OCMEMn 64-bits wide
#100 : 100
OCMEMn 128-bits wide
#101 : 101
OCMEMn 256-bits wide
0x2 : OCMW_2
OCMEMn 32-bits wide
0x3 : OCMW_3
OCMEMn 64-bits wide
0x4 : OCMW_4
OCMEMn 128-bits wide
0x5 : OCMW_5
OCMEMn 256-bits wide
End of enumeration elements list.
OCMSZ : OCMEM Size
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
#0000 : 0000
no OCMEMn
#0011 : 0011
4KB OCMEMn
#0100 : 0100
8KB OCMEMn
#0101 : 0101
16KB OCMEMn
#0110 : 0110
32KB OCMEMn
#0111 : 0111
64KB OCMEMn
#1000 : 1000
128KB OCMEMn
#1001 : 1001
256KB OCMEMn
#1010 : 1010
512KB OCMEMn
#1011 : 1011
1024KB OCMEMn
#1100 : 1100
2048KB OCMEMn
#1101 : 1101
4096KB OCMEMn
#1110 : 1110
8192KB OCMEMn
#1111 : 1111
16384KB OCMEMn
0 : OCMSZ_0
no OCMEMn
0x3 : OCMSZ_3
4KB OCMEMn
0x4 : OCMSZ_4
8KB OCMEMn
0x5 : OCMSZ_5
16KB OCMEMn
0x6 : OCMSZ_6
32KB OCMEMn
0x7 : OCMSZ_7
64KB OCMEMn
0x8 : OCMSZ_8
128KB OCMEMn
0x9 : OCMSZ_9
256KB OCMEMn
0xA : OCMSZ_10
512KB OCMEMn
0xB : OCMSZ_11
1024KB OCMEMn
0xC : OCMSZ_12
2048KB OCMEMn
0xD : OCMSZ_13
4096KB OCMEMn
0xE : OCMSZ_14
8192KB OCMEMn
0xF : OCMSZ_15
16384KB OCMEMn
End of enumeration elements list.
OCMSZH : OCMEM Size "Hole"
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
#0 : 0
OCMEMn is a power-of-2 capacity.
#1 : 1
OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
0 : OCMSZH_0
OCMEMn is a power-of-2 capacity.
0x1 : OCMSZH_1
OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
End of enumeration elements list.
V : OCMEM Valid bit. This read-only field defines the validity (presence) of the on-chip memory
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
OCMEMn is not present.
#1 : 1
OCMEMn is present.
0 : V_0
OCMEMn is not present.
0x1 : V_1
OCMEMn is present.
End of enumeration elements list.
Processor X Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ICSZ : Level 1 Instruction Cache Size
bits : 24 - 31 (8 bit)
access : read-only
Processor 0 Type Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RYPZ : Processor x Revision
bits : 0 - 7 (8 bit)
access : read-only
PERSONALITY : Processor x Personality
bits : 8 - 31 (24 bit)
access : read-only
Processor 0 Number Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPN : Processor x Number
bits : 0 - 0 (1 bit)
access : read-only
Processor 0 Master Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PPN : Processor x Physical Port Number
bits : 0 - 5 (6 bit)
access : read-only
Processor 0 Count Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PCNT : Processor Count
bits : 0 - 1 (2 bit)
access : read-only
Processor X Configuration Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ICSZ : Level 1 Instruction Cache Size
bits : 24 - 31 (8 bit)
access : read-only
Processor X Number Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPN : Processor x Number
bits : 0 - 0 (1 bit)
access : read-only
Processor X Configuration Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ICSZ : Level 1 Instruction Cache Size
bits : 24 - 31 (8 bit)
access : read-only
Processor 0 Configuration Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ICSZ : Level 1 Instruction Cache Size
bits : 24 - 31 (8 bit)
access : read-only
Processor X Configuration Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ICSZ : Level 1 Instruction Cache Size
bits : 24 - 31 (8 bit)
access : read-only
Processor X Master Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PPN : Processor x Physical Port Number
bits : 0 - 5 (6 bit)
access : read-only
On-Chip Memory Descriptor Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCMC0 : OCMEM Control Field 0
bits : 0 - 3 (4 bit)
access : read-write
OCMC1 : OCMEM Control Field 1
bits : 4 - 7 (4 bit)
access : read-write
OCMC2 : OCMEM Control Field 2
bits : 8 - 11 (4 bit)
access : read-write
OCMPU : OCMEM Memory Protection Unit
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
OCMEMn is not protected by an MPU.
#1 : 1
OCMEMn is protected by an MPU.
0 : OCMPU_0
OCMEMn is not protected by an MPU.
0x1 : OCMPU_1
OCMEMn is protected by an MPU.
End of enumeration elements list.
OCMT : OCMEM Type. This field defines the type of the on-chip memory:
bits : 13 - 15 (3 bit)
access : read-only
Enumeration:
#011 : 011
OCMEMn is a ROM.
#100 : 100
OCMEMn is a program flash.
#101 : 101
OCMEMn is a data flash.
#110 : 110
OCMEMn is an EEE.
0x3 : OCMT_3
OCMEMn is a ROM.
0x4 : OCMT_4
OCMEMn is a program flash.
0x5 : OCMT_5
OCMEMn is a data flash.
0x6 : OCMT_6
OCMEMn is an EEE.
End of enumeration elements list.
RO : Read-Only
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
writes to the OCMDRn[11:0] are allowed
#1 : 1
writes to the OCMDRn[11:0] are ignored
0 : RO_0
writes to the OCMDRn[11:0] are allowed
0x1 : RO_1
writes to the OCMDRn[11:0] are ignored
End of enumeration elements list.
OCMW : OCMEM datapath Width. This read-only field defines the width of the on-chip memory:
bits : 17 - 19 (3 bit)
access : read-only
Enumeration:
#010 : 010
OCMEMn 32-bits wide
#011 : 011
OCMEMn 64-bits wide
#100 : 100
OCMEMn 128-bits wide
#101 : 101
OCMEMn 256-bits wide
0x2 : OCMW_2
OCMEMn 32-bits wide
0x3 : OCMW_3
OCMEMn 64-bits wide
0x4 : OCMW_4
OCMEMn 128-bits wide
0x5 : OCMW_5
OCMEMn 256-bits wide
End of enumeration elements list.
OCMSZ : OCMEM Size
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
#0000 : 0000
no OCMEMn
#0011 : 0011
4KB OCMEMn
#0100 : 0100
8KB OCMEMn
#0101 : 0101
16KB OCMEMn
#0110 : 0110
32KB OCMEMn
#0111 : 0111
64KB OCMEMn
#1000 : 1000
128KB OCMEMn
#1001 : 1001
256KB OCMEMn
#1010 : 1010
512KB OCMEMn
#1011 : 1011
1024KB OCMEMn
#1100 : 1100
2048KB OCMEMn
#1101 : 1101
4096KB OCMEMn
#1110 : 1110
8192KB OCMEMn
#1111 : 1111
16384KB OCMEMn
0 : OCMSZ_0
no OCMEMn
0x3 : OCMSZ_3
4KB OCMEMn
0x4 : OCMSZ_4
8KB OCMEMn
0x5 : OCMSZ_5
16KB OCMEMn
0x6 : OCMSZ_6
32KB OCMEMn
0x7 : OCMSZ_7
64KB OCMEMn
0x8 : OCMSZ_8
128KB OCMEMn
0x9 : OCMSZ_9
256KB OCMEMn
0xA : OCMSZ_10
512KB OCMEMn
0xB : OCMSZ_11
1024KB OCMEMn
0xC : OCMSZ_12
2048KB OCMEMn
0xD : OCMSZ_13
4096KB OCMEMn
0xE : OCMSZ_14
8192KB OCMEMn
0xF : OCMSZ_15
16384KB OCMEMn
End of enumeration elements list.
OCMSZH : OCMEM Size "Hole"
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
#0 : 0
OCMEMn is a power-of-2 capacity.
#1 : 1
OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
0 : OCMSZH_0
OCMEMn is a power-of-2 capacity.
0x1 : OCMSZH_1
OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
End of enumeration elements list.
V : OCMEM Valid bit. This read-only field defines the validity (presence) of the on-chip memory
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
OCMEMn is not present.
#1 : 1
OCMEMn is present.
0 : V_0
OCMEMn is not present.
0x1 : V_1
OCMEMn is present.
End of enumeration elements list.
Processor 0 Configuration Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ICSZ : Level 1 Instruction Cache Size
bits : 24 - 31 (8 bit)
access : read-only
Processor X Count Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PCNT : Processor Count
bits : 0 - 1 (2 bit)
access : read-only
On-Chip Memory Descriptor Register
address_offset : 0xC04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OCMC0 : OCMEM Control Field 0
bits : 0 - 3 (4 bit)
access : read-write
OCMC1 : OCMEM Control Field 1
bits : 4 - 7 (4 bit)
access : read-write
OCMC2 : OCMEM Control Field 2
bits : 8 - 11 (4 bit)
access : read-write
OCMPU : OCMEM Memory Protection Unit
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
OCMEMn is not protected by an MPU.
#1 : 1
OCMEMn is protected by an MPU.
0 : OCMPU_0
OCMEMn is not protected by an MPU.
0x1 : OCMPU_1
OCMEMn is protected by an MPU.
End of enumeration elements list.
OCMT : OCMEM Type. This field defines the type of the on-chip memory:
bits : 13 - 15 (3 bit)
access : read-only
Enumeration:
#011 : 011
OCMEMn is a ROM.
#100 : 100
OCMEMn is a program flash.
#101 : 101
OCMEMn is a data flash.
#110 : 110
OCMEMn is an EEE.
0x3 : OCMT_3
OCMEMn is a ROM.
0x4 : OCMT_4
OCMEMn is a program flash.
0x5 : OCMT_5
OCMEMn is a data flash.
0x6 : OCMT_6
OCMEMn is an EEE.
End of enumeration elements list.
RO : Read-Only
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
writes to the OCMDRn[11:0] are allowed
#1 : 1
writes to the OCMDRn[11:0] are ignored
0 : RO_0
writes to the OCMDRn[11:0] are allowed
0x1 : RO_1
writes to the OCMDRn[11:0] are ignored
End of enumeration elements list.
OCMW : OCMEM datapath Width. This read-only field defines the width of the on-chip memory:
bits : 17 - 19 (3 bit)
access : read-only
Enumeration:
#010 : 010
OCMEMn 32-bits wide
#011 : 011
OCMEMn 64-bits wide
#100 : 100
OCMEMn 128-bits wide
#101 : 101
OCMEMn 256-bits wide
0x2 : OCMW_2
OCMEMn 32-bits wide
0x3 : OCMW_3
OCMEMn 64-bits wide
0x4 : OCMW_4
OCMEMn 128-bits wide
0x5 : OCMW_5
OCMEMn 256-bits wide
End of enumeration elements list.
OCMSZ : OCMEM Size
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
#0000 : 0000
no OCMEMn
#0011 : 0011
4KB OCMEMn
#0100 : 0100
8KB OCMEMn
#0101 : 0101
16KB OCMEMn
#0110 : 0110
32KB OCMEMn
#0111 : 0111
64KB OCMEMn
#1000 : 1000
128KB OCMEMn
#1001 : 1001
256KB OCMEMn
#1010 : 1010
512KB OCMEMn
#1011 : 1011
1024KB OCMEMn
#1100 : 1100
2048KB OCMEMn
#1101 : 1101
4096KB OCMEMn
#1110 : 1110
8192KB OCMEMn
#1111 : 1111
16384KB OCMEMn
0 : OCMSZ_0
no OCMEMn
0x3 : OCMSZ_3
4KB OCMEMn
0x4 : OCMSZ_4
8KB OCMEMn
0x5 : OCMSZ_5
16KB OCMEMn
0x6 : OCMSZ_6
32KB OCMEMn
0x7 : OCMSZ_7
64KB OCMEMn
0x8 : OCMSZ_8
128KB OCMEMn
0x9 : OCMSZ_9
256KB OCMEMn
0xA : OCMSZ_10
512KB OCMEMn
0xB : OCMSZ_11
1024KB OCMEMn
0xC : OCMSZ_12
2048KB OCMEMn
0xD : OCMSZ_13
4096KB OCMEMn
0xE : OCMSZ_14
8192KB OCMEMn
0xF : OCMSZ_15
16384KB OCMEMn
End of enumeration elements list.
OCMSZH : OCMEM Size "Hole"
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
#0 : 0
OCMEMn is a power-of-2 capacity.
#1 : 1
OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
0 : OCMSZH_0
OCMEMn is a power-of-2 capacity.
0x1 : OCMSZH_1
OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ.
End of enumeration elements list.
V : OCMEM Valid bit. This read-only field defines the validity (presence) of the on-chip memory
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
OCMEMn is not present.
#1 : 1
OCMEMn is present.
0 : V_0
OCMEMn is not present.
0x1 : V_1
OCMEMn is present.
End of enumeration elements list.
Processor 0 Configuration Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ICSZ : Level 1 Instruction Cache Size
bits : 24 - 31 (8 bit)
access : read-only
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