Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x0 Bytes (0x0)
size : 0x808 byte (0x0)
mem_usage : registers
protection : not protected
RTC Time Seconds Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSR : Time Seconds Register
bits : 0 - 31 (32 bit)
access : read-write
RTC Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWR : Software Reset
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is cleared by POR and by software explicitly clearing it.
0 : NO_EFFECT
No effect.
0x1 : RESET
Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is cleared by POR and by software explicitly clearing it.
End of enumeration elements list.
WPE : Wakeup Pin Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wakeup pin is disabled.
#1 : 1
Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on.
0 : DISABLED
Wakeup pin is disabled.
0x1 : ENABLED
Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on.
End of enumeration elements list.
SUP : Supervisor Access
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Non-supervisor mode write accesses are not supported and generate a bus error.
#1 : 1
Non-supervisor mode write accesses are supported.
0 : NON_SUPPORTED
Non-supervisor mode write accesses are not supported and generate a bus error.
0x1 : SUPPORTED
Non-supervisor mode write accesses are supported.
End of enumeration elements list.
UM : Update Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Registers cannot be written when locked.
#1 : 1
Registers can be written when locked under limited conditions.
0 : PROTECTED
Registers cannot be written when locked.
0x1 : WRITEABLE
Registers can be written when locked under limited conditions.
End of enumeration elements list.
CPS : Clock Pin Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT.
#1 : 1
The RTC 32kHz crystal clock is output on RTC_CLKOUT.
0 : PRESCALER
The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT.
0x1 : CRYSTAL
The RTC 32kHz crystal clock is output on RTC_CLKOUT.
End of enumeration elements list.
LPOS : LPO Select
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC prescaler increments using 32 kHz crystal.
#1 : 1
RTC prescaler increments using 128 kHz LPO, bits [4:0] of the prescaler are bypassed.
0 : CRYSTAL
RTC prescaler increments using 32 kHz crystal.
0x1 : LPO
RTC prescaler increments using LPO, bits [4:0] of the prescaler are bypassed.
End of enumeration elements list.
OSCE : Oscillator Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
32.768 kHz oscillator is disabled.
#1 : 1
32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.
0 : DISABLED
32.768 kHz oscillator is disabled.
0x1 : ENABLED
32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.
End of enumeration elements list.
CLKO : Clock Output
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The 32 kHz clock is allowed to output on RTC_CLKOUT.
#1 : 1
The 32 kHz clock is not allowed to output on RTC_CLKOUT.
0 : ENABLED
The 32 kHz clock is allowed to output on RTC_CLKOUT.
0x1 : DISABLED
The 32 kHz clock is not allowed to output on RTC_CLKOUT.
End of enumeration elements list.
CPE : Clock Pin Enable
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
RTC_CLKOUT is disabled.
#01 : 01
RTC_CLKOUT is enabled.
0 : DISABLED
RTC_CLKOUT is disabled.
0x1 : RTC_PTE0
RTC_CLKOUT is enabled.
End of enumeration elements list.
RTC Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIF : Time Invalid Flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Time is valid.
#1 : 1
Time is invalid and time counter is read as zero.
0 : VALID
Time is valid.
0x1 : INVALID
Time is invalid and time counter is read as zero.
End of enumeration elements list.
TOF : Time Overflow Flag
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Time overflow has not occurred.
#1 : 1
Time overflow has occurred and time counter is read as zero.
0 : NOT_OCCURED
Time overflow has not occurred.
0x1 : OCCURED
Time overflow has occurred and time counter is read as zero.
End of enumeration elements list.
TAF : Time Alarm Flag
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Time alarm has not occurred.
#1 : 1
Time alarm has occurred.
0 : NOT_OCCURED
Time alarm has not occurred.
0x1 : OCCURED
Time alarm has occurred.
End of enumeration elements list.
TCE : Time Counter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time counter is disabled.
#1 : 1
Time counter is enabled.
0 : DISABLED
Time counter is disabled.
0x1 : ENABLED
Time counter is enabled.
End of enumeration elements list.
RTC Lock Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCL : Time Compensation Lock
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time Compensation Register is locked and writes are ignored.
#1 : 1
Time Compensation Register is not locked and writes complete as normal.
0 : LOCKED
Time Compensation Register is locked and writes are ignored.
0x1 : NORMAL
Time Compensation Register is not locked and writes complete as normal.
End of enumeration elements list.
CRL : Control Register Lock
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Control Register is locked and writes are ignored.
#1 : 1
Control Register is not locked and writes complete as normal.
0 : LOCKED
Control Register is locked and writes are ignored.
0x1 : NORMAL
Control Register is not locked and writes complete as normal.
End of enumeration elements list.
SRL : Status Register Lock
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Status Register is locked and writes are ignored.
#1 : 1
Status Register is not locked and writes complete as normal.
0 : LOCKED
Status Register is locked and writes are ignored.
0x1 : NORMAL
Status Register is not locked and writes complete as normal.
End of enumeration elements list.
LRL : Lock Register Lock
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Lock Register is locked and writes are ignored.
#1 : 1
Lock Register is not locked and writes complete as normal.
0 : LOCKED
Lock Register is locked and writes are ignored.
0x1 : NORMAL
Lock Register is not locked and writes complete as normal.
End of enumeration elements list.
RTC Interrupt Enable Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIIE : Time Invalid Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time invalid flag does not generate an interrupt.
#1 : 1
Time invalid flag does generate an interrupt.
0 : DISABLED
Time invalid flag does not generate an interrupt.
0x1 : ENABLED
Time invalid flag does generate an interrupt.
End of enumeration elements list.
TOIE : Time Overflow Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time overflow flag does not generate an interrupt.
#1 : 1
Time overflow flag does generate an interrupt.
0 : DISABLED
Time overflow flag does not generate an interrupt.
0x1 : ENABLED
Time overflow flag does generate an interrupt.
End of enumeration elements list.
TAIE : Time Alarm Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time alarm flag does not generate an interrupt.
#1 : 1
Time alarm flag does generate an interrupt.
0 : DISABLED
Time alarm flag does not generate an interrupt.
0x1 : ENABLED
Time alarm flag does generate an interrupt.
End of enumeration elements list.
TSIE : Time Seconds Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Seconds interrupt is disabled.
#1 : 1
Seconds interrupt is enabled.
0 : DISABLED
Seconds interrupt is disabled.
0x1 : ENABLED
Seconds interrupt is enabled.
End of enumeration elements list.
WPON : Wakeup Pin On
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
If the wakeup pin is enabled, then the wakeup pin will assert.
0 : NO_EFFECT
No effect.
0x1 : ON
If the wakeup pin is enabled, then the wakeup pin will assert.
End of enumeration elements list.
TSIC : Timer Seconds Interrupt Configuration
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 000
1 Hz.
#001 : 001
2 Hz.
#010 : 010
4 Hz.
#011 : 011
8 Hz.
#100 : 100
16 Hz.
#101 : 101
32 Hz.
#110 : 110
64 Hz.
#111 : 111
128 Hz.
0 : F1HZ
1 Hz.
0x1 : F2HZ
2 Hz.
0x2 : F4HZ
4 Hz.
0x3 : F8HZ
8 Hz.
0x4 : F16HZ
16 Hz.
0x5 : F32HZ
32 Hz.
0x6 : F64HZ
64 Hz.
0x7 : F128HZ
128 Hz.
End of enumeration elements list.
RTC Time Prescaler Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPR : Time Prescaler Register
bits : 0 - 15 (16 bit)
access : read-write
RTC Time Alarm Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TAR : Time Alarm Register
bits : 0 - 31 (32 bit)
access : read-write
RTC Write Access Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSRW : Time Seconds Register Write
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writes to the Time Seconds Register are ignored.
#1 : 1
Writes to the Time Seconds Register complete as normal.
0 : IGNORED
Writes to the Time Seconds Register are ignored.
0x1 : NORMAL
Writes to the Time Seconds Register complete as normal.
End of enumeration elements list.
TPRW : Time Prescaler Register Write
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writes to the Time Prescaler Register are ignored.
#1 : 1
Writes to the Time Prescaler Register complete as normal.
0 : IGNORED
Writes to the Time Prescaler Register are ignored.
0x1 : NORMAL
Writes to the Time Prescaler Register complete as normal.
End of enumeration elements list.
TARW : Time Alarm Register Write
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writes to the Time Alarm Register are ignored.
#1 : 1
Writes to the Time Alarm Register complete as normal.
0 : IGNORED
Writes to the Time Alarm Register are ignored.
0x1 : NORMAL
Writes to the Time Alarm Register complete as normal.
End of enumeration elements list.
TCRW : Time Compensation Register Write
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writes to the Time Compensation Register are ignored.
#1 : 1
Writes to the Time Compensation Register complete as normal.
0 : IGNORED
Writes to the Time Compensation Register are ignored.
0x1 : NORMAL
Writes to the Time Compensation Register complete as normal.
End of enumeration elements list.
CRW : Control Register Write
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writes to the Control Register are ignored.
#1 : 1
Writes to the Control Register complete as normal.
0 : IGNORED
Writes to the Control Register are ignored.
0x1 : NORMAL
Writes to the Control Register complete as normal.
End of enumeration elements list.
SRW : Status Register Write
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writes to the Status Register are ignored.
#1 : 1
Writes to the Status Register complete as normal.
0 : IGNORED
Writes to the Status Register are ignored.
0x1 : NORMAL
Writes to the Status Register complete as normal.
End of enumeration elements list.
LRW : Lock Register Write
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writes to the Lock Register are ignored.
#1 : 1
Writes to the Lock Register complete as normal.
0 : IGNORED
Writes to the Lock Register are ignored.
0x1 : NORMAL
Writes to the Lock Register complete as normal.
End of enumeration elements list.
IERW : Interrupt Enable Register Write
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writes to the Interupt Enable Register are ignored.
#1 : 1
Writes to the Interrupt Enable Register complete as normal.
0 : IGNORED
Writes to the Interupt Enable Register are ignored.
0x1 : NORMAL
Writes to the Interrupt Enable Register complete as normal.
End of enumeration elements list.
RTC Read Access Register
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSRR : Time Seconds Register Read
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reads to the Time Seconds Register are ignored.
#1 : 1
Reads to the Time Seconds Register complete as normal.
0 : IGNORED
Reads to the Time Seconds Register are ignored.
0x1 : NORMAL
Reads to the Time Seconds Register complete as normal.
End of enumeration elements list.
TPRR : Time Prescaler Register Read
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reads to the Time Pprescaler Register are ignored.
#1 : 1
Reads to the Time Prescaler Register complete as normal.
0 : IGNORED
Reads to the Time Pprescaler Register are ignored.
0x1 : NORMAL
Reads to the Time Prescaler Register complete as normal.
End of enumeration elements list.
TARR : Time Alarm Register Read
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reads to the Time Alarm Register are ignored.
#1 : 1
Reads to the Time Alarm Register complete as normal.
0 : IGNORED
Reads to the Time Alarm Register are ignored.
0x1 : NORMAL
Reads to the Time Alarm Register complete as normal.
End of enumeration elements list.
TCRR : Time Compensation Register Read
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reads to the Time Compensation Register are ignored.
#1 : 1
Reads to the Time Compensation Register complete as normal.
0 : IGNORED
Reads to the Time Compensation Register are ignored.
0x1 : NORMAL
Reads to the Time Compensation Register complete as normal.
End of enumeration elements list.
CRR : Control Register Read
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reads to the Control Register are ignored.
#1 : 1
Reads to the Control Register complete as normal.
0 : IGNORED
Reads to the Control Register are ignored.
0x1 : NORMAL
Reads to the Control Register complete as normal.
End of enumeration elements list.
SRR : Status Register Read
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reads to the Status Register are ignored.
#1 : 1
Reads to the Status Register complete as normal.
0 : IGNORED
Reads to the Status Register are ignored.
0x1 : NORMAL
Reads to the Status Register complete as normal.
End of enumeration elements list.
LRR : Lock Register Read
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reads to the Lock Register are ignored.
#1 : 1
Reads to the Lock Register complete as normal.
0 : IGNORED
Reads to the Lock Register are ignored.
0x1 : NORMAL
Reads to the Lock Register complete as normal.
End of enumeration elements list.
IERR : Interrupt Enable Register Read
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reads to the Interrupt Enable Register are ignored.
#1 : 1
Reads to the Interrupt Enable Register complete as normal.
0 : IGNORED
Reads to the Interrupt Enable Register are ignored.
0x1 : NORMAL
Reads to the Interrupt Enable Register complete as normal.
End of enumeration elements list.
RTC Time Compensation Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCR : Time Compensation Register
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
#10000000 : 10000000
Time Prescaler Register overflows every 32896 clock cycles.
#11111111 : 11111111
Time Prescaler Register overflows every 32769 clock cycles.
#0 : 0
Time Prescaler Register overflows every 32768 clock cycles.
#1 : 1
Time Prescaler Register overflows every 32767 clock cycles.
#1111111 : 1111111
Time Prescaler Register overflows every 32641 clock cycles.
0 : TCR_0
Time Prescaler Register overflows every 32768 clock cycles.
0x1 : TCR_1
Time Prescaler Register overflows every 32767 clock cycles.
0x7F : TCR_127
Time Prescaler Register overflows every 32641 clock cycles.
0x80 : TCR_128
Time Prescaler Register overflows every 32896 clock cycles.
0xFF : TCR_255
Time Prescaler Register overflows every 32769 clock cycles.
End of enumeration elements list.
CIR : Compensation Interval Register
bits : 8 - 15 (8 bit)
access : read-write
TCV : Time Compensation Value
bits : 16 - 23 (8 bit)
access : read-only
CIC : Compensation Interval Counter
bits : 24 - 31 (8 bit)
access : read-only
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