Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x5 byte (0x0)
mem_usage : registers
protection : not protected
Low Voltage Detect Status and Control 1 Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVDRE : Low Voltage Detect Reset Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No system resets on low voltage detect events.
#1 : 1
If the supply voltage falls below VLVD, a system reset will be generated.
0 : LVDRE_0
No system resets on low voltage detect events.
0x1 : LVDRE_1
If the supply voltage falls below VLVD, a system reset will be generated.
End of enumeration elements list.
LVDIE : Low Voltage Detect Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware interrupt disabled (use polling)
#1 : 1
Request a hardware interrupt when LVDF = 1
0 : LVDIE_0
Hardware interrupt disabled (use polling)
0x1 : LVDIE_1
Request a hardware interrupt when LVDF = 1
End of enumeration elements list.
LVDACK : Low Voltage Detect Acknowledge
bits : 6 - 6 (1 bit)
access : write-only
LVDF : Low Voltage Detect Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Low-voltage event not detected
#1 : 1
Low-voltage event detected
0 : LVDF_0
Low-voltage event not detected
0x1 : LVDF_1
Low-voltage event detected
End of enumeration elements list.
Low Voltage Detect Status and Control 2 Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVWIE : Low-Voltage Warning Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware interrupt disabled (use polling)
#1 : 1
Request a hardware interrupt when LVWF=1
0 : LVWIE_0
Hardware interrupt disabled (use polling)
0x1 : LVWIE_1
Request a hardware interrupt when LVWF=1
End of enumeration elements list.
LVWACK : Low-Voltage Warning Acknowledge
bits : 6 - 6 (1 bit)
access : write-only
LVWF : Low-Voltage Warning Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Low-voltage warning event not detected
#1 : 1
Low-voltage warning event detected
0 : LVWF_0
Low-voltage warning event not detected
0x1 : LVWF_1
Low-voltage warning event detected
End of enumeration elements list.
Regulator Status and Control Register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BIASEN : Bias Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Biasing disabled, core logic can run in full performance
#1 : 1
Biasing enabled, core logic is slower and there are restrictions in allowed system clock speed (see Data Sheet for details)
0 : BIASEN_0
Biasing disabled, core logic can run in full performance
0x1 : BIASEN_1
Biasing enabled, core logic is slower and there are restrictions in allowed system clock speed (see Data Sheet for details)
End of enumeration elements list.
CLKBIASDIS : Clock Bias Disable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
In STOP or VLPS mode the bias currents and reference voltages for the following clock modules are disabled: SIRC, FIRC, PLL. (if available on device)
0 : CLKBIASDIS_0
No effect
0x1 : CLKBIASDIS_1
In STOP or VLPS mode the bias currents and reference voltages for the following clock modules are disabled: SIRC, FIRC, PLL. (if available on device)
End of enumeration elements list.
REGFPM : Regulator in Full Performance Mode Status Bit
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Regulator is in low power mode or transition to/from
#1 : 1
Regulator is in full performance mode
0 : REGFPM_0
Regulator is in low power mode or transition to/from
0x1 : REGFPM_1
Regulator is in full performance mode
End of enumeration elements list.
LPOSTAT : LPO Status Bit
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Low power oscillator in low phase
#1 : 1
Low power oscillator in high phase
0 : LPOSTAT_0
Low power oscillator in low phase
0x1 : LPOSTAT_1
Low power oscillator in high phase
End of enumeration elements list.
LPODIS : LPO Disable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low power oscillator enabled
#1 : 1
Low power oscillator disabled
0 : LPODIS_0
Low power oscillator enabled
0x1 : LPODIS_1
Low power oscillator disabled
End of enumeration elements list.
Low Power Oscillator Trim Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPOTRIM : LPO trimming bits
bits : 0 - 4 (5 bit)
access : read-write
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