Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xA0 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x0 Bytes (0x0)
size : 0x224 byte (0x0)
mem_usage : registers
protection : not protected
Status And Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Prescale Factor Selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 000
Divide by 1
#001 : 001
Divide by 2
#010 : 010
Divide by 4
#011 : 011
Divide by 8
#100 : 100
Divide by 16
#101 : 101
Divide by 32
#110 : 110
Divide by 64
#111 : 111
Divide by 128
0 : PS_0
Divide by 1
0x1 : PS_1
Divide by 2
0x2 : PS_2
Divide by 4
0x3 : PS_3
Divide by 8
0x4 : PS_4
Divide by 16
0x5 : PS_5
Divide by 32
0x6 : PS_6
Divide by 64
0x7 : PS_7
Divide by 128
End of enumeration elements list.
CLKS : Clock Source Selection
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 00
No clock selected. This in effect disables the FTM counter.
#01 : 01
FTM input clock
#10 : 10
Fixed frequency clock
#11 : 11
External clock
0 : CLKS_0
No clock selected. This in effect disables the FTM counter.
0x1 : CLKS_1
FTM input clock
0x2 : CLKS_2
Fixed frequency clock
0x3 : CLKS_3
External clock
End of enumeration elements list.
CPWMS : Center-Aligned PWM Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter operates in Up Counting mode.
#1 : 1
FTM counter operates in Up-Down Counting mode.
0 : CPWMS_0
FTM counter operates in Up Counting mode.
0x1 : CPWMS_1
FTM counter operates in Up-Down Counting mode.
End of enumeration elements list.
RIE : Reload Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reload interrupt is disabled.
#1 : 1
Reload interrupt is enabled.
0 : RIE_0
Reload interrupt is disabled.
0x1 : RIE_1
Reload interrupt is enabled.
End of enumeration elements list.
RF : Reload Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter did not reach a reload point.
#1 : 1
FTM counter reached a reload point.
0 : RF_0
FTM counter did not reach a reload point.
0x1 : RF_1
FTM counter reached a reload point.
End of enumeration elements list.
TOIE : Timer Overflow Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable TOF interrupts. Use software polling.
#1 : 1
Enable TOF interrupts. An interrupt is generated when TOF equals one.
0 : TOIE_0
Disable TOF interrupts. Use software polling.
0x1 : TOIE_1
Enable TOF interrupts. An interrupt is generated when TOF equals one.
End of enumeration elements list.
TOF : Timer Overflow Flag
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter has not overflowed.
#1 : 1
FTM counter has overflowed.
0 : TOF_0
FTM counter has not overflowed.
0x1 : TOF_1
FTM counter has overflowed.
End of enumeration elements list.
PWMEN0 : Channel 0 PWM enable bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output port is disabled
#1 : 1
Channel output port is enabled
0 : PWMEN0_0
Channel output port is disabled
0x1 : PWMEN0_1
Channel output port is enabled
End of enumeration elements list.
PWMEN1 : Channel 1 PWM enable bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output port is disabled
#1 : 1
Channel output port is enabled
0 : PWMEN1_0
Channel output port is disabled
0x1 : PWMEN1_1
Channel output port is enabled
End of enumeration elements list.
PWMEN2 : Channel 2 PWM enable bit
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output port is disabled
#1 : 1
Channel output port is enabled
0 : PWMEN2_0
Channel output port is disabled
0x1 : PWMEN2_1
Channel output port is enabled
End of enumeration elements list.
PWMEN3 : Channel 3 PWM enable bit
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output port is disabled
#1 : 1
Channel output port is enabled
0 : PWMEN3_0
Channel output port is disabled
0x1 : PWMEN3_1
Channel output port is enabled
End of enumeration elements list.
PWMEN4 : Channel 4 PWM enable bit
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output port is disabled
#1 : 1
Channel output port is enabled
0 : PWMEN4_0
Channel output port is disabled
0x1 : PWMEN4_1
Channel output port is enabled
End of enumeration elements list.
PWMEN5 : Channel 5 PWM enable bit
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output port is disabled
#1 : 1
Channel output port is enabled
0 : PWMEN5_0
Channel output port is disabled
0x1 : PWMEN5_1
Channel output port is enabled
End of enumeration elements list.
PWMEN6 : Channel 6 PWM enable bit
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output port is disabled
#1 : 1
Channel output port is enabled
0 : PWMEN6_0
Channel output port is disabled
0x1 : PWMEN6_1
Channel output port is enabled
End of enumeration elements list.
PWMEN7 : Channel 7 PWM enable bit
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output port is disabled
#1 : 1
Channel output port is enabled
0 : PWMEN7_0
Channel output port is disabled
0x1 : PWMEN7_1
Channel output port is enabled
End of enumeration elements list.
FLTPS : Filter Prescaler
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide by 1
#0001 : 0001
Divide by 2
#0010 : 0010
Divide by 3
#0011 : 0011
Divide by 4
#0100 : 0100
Divide by 5
#0101 : 0101
Divide by 6
#0110 : 0110
Divide by 7
#0111 : 0111
Divide by 8
#1000 : 1000
Divide by 9
#1001 : 1001
Divide by 10
#1010 : 1010
Divide by 11
#1011 : 1011
Divide by 12
#1100 : 1100
Divide by 13
#1101 : 1101
Divide by 14
#1110 : 1110
Divide by 15
#1111 : 1111
Divide by 16
0 : FLTPS_0
Divide by 1
0x1 : FLTPS_1
Divide by 2
0x2 : FLTPS_2
Divide by 3
0x3 : FLTPS_3
Divide by 4
0x4 : FLTPS_4
Divide by 5
0x5 : FLTPS_5
Divide by 6
0x6 : FLTPS_6
Divide by 7
0x7 : FLTPS_7
Divide by 8
0x8 : FLTPS_8
Divide by 9
0x9 : FLTPS_9
Divide by 10
0xA : FLTPS_10
Divide by 11
0xB : FLTPS_11
Divide by 12
0xC : FLTPS_12
Divide by 13
0xD : FLTPS_13
Divide by 14
0xE : FLTPS_14
Divide by 15
0xF : FLTPS_15
Divide by 16
End of enumeration elements list.
Mirror of Channel (n) Match Value
address_offset : 0x1074 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL : Channel (n) Match Fractional Value
bits : 11 - 15 (5 bit)
access : read-write
VAL : Mirror of the Channel (n) Match Integer Value
bits : 16 - 31 (16 bit)
access : read-write
Channel (n) Status And Control
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DMA transfers.
#1 : 1
Enable DMA transfers.
0 : DMA_0
Disable DMA transfers.
0x1 : DMA_1
Enable DMA transfers.
End of enumeration elements list.
ICRST : FTM counter reset by the selected input capture event.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter is not reset when the selected channel (n) input event is detected.
#1 : 1
FTM counter is reset when the selected channel (n) input event is detected.
0 : ICRST_0
FTM counter is not reset when the selected channel (n) input event is detected.
0x1 : ICRST_1
FTM counter is reset when the selected channel (n) input event is detected.
End of enumeration elements list.
ELSA : Channel (n) Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Channel (n) Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel (n) Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel (n) Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel (n) Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel (n) interrupt. Use software polling.
#1 : 1
Enable channel (n) interrupt.
0 : CHIE_0
Disable channel (n) interrupt. Use software polling.
0x1 : CHIE_1
Enable channel (n) interrupt.
End of enumeration elements list.
CHF : Channel (n) Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel (n) event has occurred.
#1 : 1
A channel (n) event has occurred.
0 : CHF_0
No channel (n) event has occurred.
0x1 : CHF_1
A channel (n) event has occurred.
End of enumeration elements list.
TRIGMODE : Trigger mode control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel outputs will generate the normal PWM outputs without generating a pulse.
#1 : 1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
0 : TRIGMODE_0
Channel outputs will generate the normal PWM outputs without generating a pulse.
0x1 : TRIGMODE_1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
End of enumeration elements list.
CHIS : Channel (n) Input State
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) input is zero.
#1 : 1
The channel (n) input is one.
0 : CHIS_0
The channel (n) input is zero.
0x1 : CHIS_1
The channel (n) input is one.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Mirror of Channel (n) Match Value
address_offset : 0x1294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL : Channel (n) Match Fractional Value
bits : 11 - 15 (5 bit)
access : read-write
VAL : Mirror of the Channel (n) Match Integer Value
bits : 16 - 31 (16 bit)
access : read-write
Channel (n) Status And Control
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DMA transfers.
#1 : 1
Enable DMA transfers.
0 : DMA_0
Disable DMA transfers.
0x1 : DMA_1
Enable DMA transfers.
End of enumeration elements list.
ICRST : FTM counter reset by the selected input capture event.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter is not reset when the selected channel (n) input event is detected.
#1 : 1
FTM counter is reset when the selected channel (n) input event is detected.
0 : ICRST_0
FTM counter is not reset when the selected channel (n) input event is detected.
0x1 : ICRST_1
FTM counter is reset when the selected channel (n) input event is detected.
End of enumeration elements list.
ELSA : Channel (n) Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Channel (n) Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel (n) Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel (n) Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel (n) Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel (n) interrupt. Use software polling.
#1 : 1
Enable channel (n) interrupt.
0 : CHIE_0
Disable channel (n) interrupt. Use software polling.
0x1 : CHIE_1
Enable channel (n) interrupt.
End of enumeration elements list.
CHF : Channel (n) Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel (n) event has occurred.
#1 : 1
A channel (n) event has occurred.
0 : CHF_0
No channel (n) event has occurred.
0x1 : CHF_1
A channel (n) event has occurred.
End of enumeration elements list.
TRIGMODE : Trigger mode control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel outputs will generate the normal PWM outputs without generating a pulse.
#1 : 1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
0 : TRIGMODE_0
Channel outputs will generate the normal PWM outputs without generating a pulse.
0x1 : TRIGMODE_1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
End of enumeration elements list.
CHIS : Channel (n) Input State
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) input is zero.
#1 : 1
The channel (n) input is one.
0 : CHIS_0
The channel (n) input is zero.
0x1 : CHIS_1
The channel (n) input is one.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Status And Control
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DMA transfers.
#1 : 1
Enable DMA transfers.
0 : DMA_0
Disable DMA transfers.
0x1 : DMA_1
Enable DMA transfers.
End of enumeration elements list.
ICRST : FTM counter reset by the selected input capture event.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter is not reset when the selected channel (n) input event is detected.
#1 : 1
FTM counter is reset when the selected channel (n) input event is detected.
0 : ICRST_0
FTM counter is not reset when the selected channel (n) input event is detected.
0x1 : ICRST_1
FTM counter is reset when the selected channel (n) input event is detected.
End of enumeration elements list.
ELSA : Channel (n) Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Channel (n) Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel (n) Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel (n) Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel (n) Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel (n) interrupt. Use software polling.
#1 : 1
Enable channel (n) interrupt.
0 : CHIE_0
Disable channel (n) interrupt. Use software polling.
0x1 : CHIE_1
Enable channel (n) interrupt.
End of enumeration elements list.
CHF : Channel (n) Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel (n) event has occurred.
#1 : 1
A channel (n) event has occurred.
0 : CHF_0
No channel (n) event has occurred.
0x1 : CHF_1
A channel (n) event has occurred.
End of enumeration elements list.
TRIGMODE : Trigger mode control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel outputs will generate the normal PWM outputs without generating a pulse.
#1 : 1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
0 : TRIGMODE_0
Channel outputs will generate the normal PWM outputs without generating a pulse.
0x1 : TRIGMODE_1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
End of enumeration elements list.
CHIS : Channel (n) Input State
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) input is zero.
#1 : 1
The channel (n) input is one.
0 : CHIS_0
The channel (n) input is zero.
0x1 : CHIS_1
The channel (n) input is one.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Mirror of Modulo Value
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACMOD : Modulo Fractional Value
bits : 11 - 15 (5 bit)
access : read-write
MOD : Mirror of the Modulo Integer Value
bits : 16 - 31 (16 bit)
access : read-write
Channel (n) Status And Control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DMA transfers.
#1 : 1
Enable DMA transfers.
0 : DMA_0
Disable DMA transfers.
0x1 : DMA_1
Enable DMA transfers.
End of enumeration elements list.
ICRST : FTM counter reset by the selected input capture event.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter is not reset when the selected channel (n) input event is detected.
#1 : 1
FTM counter is reset when the selected channel (n) input event is detected.
0 : ICRST_0
FTM counter is not reset when the selected channel (n) input event is detected.
0x1 : ICRST_1
FTM counter is reset when the selected channel (n) input event is detected.
End of enumeration elements list.
ELSA : Channel (n) Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Channel (n) Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel (n) Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel (n) Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel (n) Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel (n) interrupt. Use software polling.
#1 : 1
Enable channel (n) interrupt.
0 : CHIE_0
Disable channel (n) interrupt. Use software polling.
0x1 : CHIE_1
Enable channel (n) interrupt.
End of enumeration elements list.
CHF : Channel (n) Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel (n) event has occurred.
#1 : 1
A channel (n) event has occurred.
0 : CHF_0
No channel (n) event has occurred.
0x1 : CHF_1
A channel (n) event has occurred.
End of enumeration elements list.
TRIGMODE : Trigger mode control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel outputs will generate the normal PWM outputs without generating a pulse.
#1 : 1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
0 : TRIGMODE_0
Channel outputs will generate the normal PWM outputs without generating a pulse.
0x1 : TRIGMODE_1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
End of enumeration elements list.
CHIS : Channel (n) Input State
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) input is zero.
#1 : 1
The channel (n) input is one.
0 : CHIS_0
The channel (n) input is zero.
0x1 : CHIS_1
The channel (n) input is one.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Counter
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Counter Value
bits : 0 - 15 (16 bit)
access : read-write
Mirror of Channel (n) Match Value
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL : Channel (n) Match Fractional Value
bits : 11 - 15 (5 bit)
access : read-write
VAL : Mirror of the Channel (n) Match Integer Value
bits : 16 - 31 (16 bit)
access : read-write
Channel (n) Status And Control
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DMA transfers.
#1 : 1
Enable DMA transfers.
0 : DMA_0
Disable DMA transfers.
0x1 : DMA_1
Enable DMA transfers.
End of enumeration elements list.
ICRST : FTM counter reset by the selected input capture event.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter is not reset when the selected channel (n) input event is detected.
#1 : 1
FTM counter is reset when the selected channel (n) input event is detected.
0 : ICRST_0
FTM counter is not reset when the selected channel (n) input event is detected.
0x1 : ICRST_1
FTM counter is reset when the selected channel (n) input event is detected.
End of enumeration elements list.
ELSA : Channel (n) Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Channel (n) Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel (n) Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel (n) Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel (n) Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel (n) interrupt. Use software polling.
#1 : 1
Enable channel (n) interrupt.
0 : CHIE_0
Disable channel (n) interrupt. Use software polling.
0x1 : CHIE_1
Enable channel (n) interrupt.
End of enumeration elements list.
CHF : Channel (n) Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel (n) event has occurred.
#1 : 1
A channel (n) event has occurred.
0 : CHF_0
No channel (n) event has occurred.
0x1 : CHF_1
A channel (n) event has occurred.
End of enumeration elements list.
TRIGMODE : Trigger mode control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel outputs will generate the normal PWM outputs without generating a pulse.
#1 : 1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
0 : TRIGMODE_0
Channel outputs will generate the normal PWM outputs without generating a pulse.
0x1 : TRIGMODE_1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
End of enumeration elements list.
CHIS : Channel (n) Input State
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) input is zero.
#1 : 1
The channel (n) input is one.
0 : CHIS_0
The channel (n) input is zero.
0x1 : CHIS_1
The channel (n) input is one.
End of enumeration elements list.
Counter Initial Value
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : Initial Value Of The FTM Counter
bits : 0 - 15 (16 bit)
access : read-write
Capture And Compare Status
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0F : Channel 0 Flag
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
0 : CH0F_0
No channel event has occurred.
0x1 : CH0F_1
A channel event has occurred.
End of enumeration elements list.
CH1F : Channel 1 Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
0 : CH1F_0
No channel event has occurred.
0x1 : CH1F_1
A channel event has occurred.
End of enumeration elements list.
CH2F : Channel 2 Flag
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
0 : CH2F_0
No channel event has occurred.
0x1 : CH2F_1
A channel event has occurred.
End of enumeration elements list.
CH3F : Channel 3 Flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
0 : CH3F_0
No channel event has occurred.
0x1 : CH3F_1
A channel event has occurred.
End of enumeration elements list.
CH4F : Channel 4 Flag
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
0 : CH4F_0
No channel event has occurred.
0x1 : CH4F_1
A channel event has occurred.
End of enumeration elements list.
CH5F : Channel 5 Flag
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
0 : CH5F_0
No channel event has occurred.
0x1 : CH5F_1
A channel event has occurred.
End of enumeration elements list.
CH6F : Channel 6 Flag
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
0 : CH6F_0
No channel event has occurred.
0x1 : CH6F_1
A channel event has occurred.
End of enumeration elements list.
CH7F : Channel 7 Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
0 : CH7F_0
No channel event has occurred.
0x1 : CH7F_1
A channel event has occurred.
End of enumeration elements list.
Features Mode Selection
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTMEN : FTM Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
TPM compatibility. Free running counter and synchronization compatible with TPM.
#1 : 1
Free running counter and synchronization are different from TPM behavior.
0 : FTMEN_0
TPM compatibility. Free running counter and synchronization compatible with TPM.
0x1 : FTMEN_1
Free running counter and synchronization are different from TPM behavior.
End of enumeration elements list.
INIT : Initialize The Channels Output
bits : 1 - 1 (1 bit)
access : read-write
WPDIS : Write Protection Disable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Write protection is enabled.
#1 : 1
Write protection is disabled.
0 : WPDIS_0
Write protection is enabled.
0x1 : WPDIS_1
Write protection is disabled.
End of enumeration elements list.
PWMSYNC : PWM Synchronization Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.
#1 : 1
Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.
0 : PWMSYNC_0
No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.
0x1 : PWMSYNC_1
Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.
End of enumeration elements list.
CAPTEST : Capture Test Mode Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture test mode is disabled.
#1 : 1
Capture test mode is enabled.
0 : CAPTEST_0
Capture test mode is disabled.
0x1 : CAPTEST_1
Capture test mode is enabled.
End of enumeration elements list.
FAULTM : Fault Control Mode
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
#00 : 00
Fault control is disabled for all channels.
#01 : 01
Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
#10 : 10
Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
#11 : 11
Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
0 : FAULTM_0
Fault control is disabled for all channels.
0x1 : FAULTM_1
Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
0x2 : FAULTM_2
Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
0x3 : FAULTM_3
Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
End of enumeration elements list.
FAULTIE : Fault Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault control interrupt is disabled.
#1 : 1
Fault control interrupt is enabled.
0 : FAULTIE_0
Fault control interrupt is disabled.
0x1 : FAULTIE_1
Fault control interrupt is enabled.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Synchronization
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTMIN : Minimum Loading Point Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The minimum loading point is disabled.
#1 : 1
The minimum loading point is enabled.
0 : CNTMIN_0
The minimum loading point is disabled.
0x1 : CNTMIN_1
The minimum loading point is enabled.
End of enumeration elements list.
CNTMAX : Maximum Loading Point Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The maximum loading point is disabled.
#1 : 1
The maximum loading point is enabled.
0 : CNTMAX_0
The maximum loading point is disabled.
0x1 : CNTMAX_1
The maximum loading point is enabled.
End of enumeration elements list.
REINIT : FTM Counter Reinitialization By Synchronization (FTM counter synchronization)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter continues to count normally.
#1 : 1
FTM counter is updated with its initial value when the selected trigger is detected.
0 : REINIT_0
FTM counter continues to count normally.
0x1 : REINIT_1
FTM counter is updated with its initial value when the selected trigger is detected.
End of enumeration elements list.
SYNCHOM : Output Mask Synchronization
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
OUTMASK register is updated with the value of its buffer in all rising edges of the FTM input clock.
#1 : 1
OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
0 : SYNCHOM_0
OUTMASK register is updated with the value of its buffer in all rising edges of the FTM input clock.
0x1 : SYNCHOM_1
OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
End of enumeration elements list.
TRIG0 : PWM Synchronization Hardware Trigger 0
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trigger is disabled.
#1 : 1
Trigger is enabled.
0 : TRIG0_0
Trigger is disabled.
0x1 : TRIG0_1
Trigger is enabled.
End of enumeration elements list.
TRIG1 : PWM Synchronization Hardware Trigger 1
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trigger is disabled.
#1 : 1
Trigger is enabled.
0 : TRIG1_0
Trigger is disabled.
0x1 : TRIG1_1
Trigger is enabled.
End of enumeration elements list.
TRIG2 : PWM Synchronization Hardware Trigger 2
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trigger is disabled.
#1 : 1
Trigger is enabled.
0 : TRIG2_0
Trigger is disabled.
0x1 : TRIG2_1
Trigger is enabled.
End of enumeration elements list.
SWSYNC : PWM Synchronization Software Trigger
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Software trigger is not selected.
#1 : 1
Software trigger is selected.
0 : SWSYNC_0
Software trigger is not selected.
0x1 : SWSYNC_1
Software trigger is selected.
End of enumeration elements list.
Initial State For Channels Output
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0OI : Channel 0 Output Initialization Value
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
0 : CH0OI_0
The initialization value is 0.
0x1 : CH0OI_1
The initialization value is 1.
End of enumeration elements list.
CH1OI : Channel 1 Output Initialization Value
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
0 : CH1OI_0
The initialization value is 0.
0x1 : CH1OI_1
The initialization value is 1.
End of enumeration elements list.
CH2OI : Channel 2 Output Initialization Value
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
0 : CH2OI_0
The initialization value is 0.
0x1 : CH2OI_1
The initialization value is 1.
End of enumeration elements list.
CH3OI : Channel 3 Output Initialization Value
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
0 : CH3OI_0
The initialization value is 0.
0x1 : CH3OI_1
The initialization value is 1.
End of enumeration elements list.
CH4OI : Channel 4 Output Initialization Value
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
0 : CH4OI_0
The initialization value is 0.
0x1 : CH4OI_1
The initialization value is 1.
End of enumeration elements list.
CH5OI : Channel 5 Output Initialization Value
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
0 : CH5OI_0
The initialization value is 0.
0x1 : CH5OI_1
The initialization value is 1.
End of enumeration elements list.
CH6OI : Channel 6 Output Initialization Value
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
0 : CH6OI_0
The initialization value is 0.
0x1 : CH6OI_1
The initialization value is 1.
End of enumeration elements list.
CH7OI : Channel 7 Output Initialization Value
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The initialization value is 0.
#1 : 1
The initialization value is 1.
0 : CH7OI_0
The initialization value is 0.
0x1 : CH7OI_1
The initialization value is 1.
End of enumeration elements list.
Output Mask
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0OM : Channel 0 Output Mask
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
0 : CH0OM_0
Channel output is not masked. It continues to operate normally.
0x1 : CH0OM_1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH1OM : Channel 1 Output Mask
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
0 : CH1OM_0
Channel output is not masked. It continues to operate normally.
0x1 : CH1OM_1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH2OM : Channel 2 Output Mask
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
0 : CH2OM_0
Channel output is not masked. It continues to operate normally.
0x1 : CH2OM_1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH3OM : Channel 3 Output Mask
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
0 : CH3OM_0
Channel output is not masked. It continues to operate normally.
0x1 : CH3OM_1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH4OM : Channel 4 Output Mask
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
0 : CH4OM_0
Channel output is not masked. It continues to operate normally.
0x1 : CH4OM_1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH5OM : Channel 5 Output Mask
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
0 : CH5OM_0
Channel output is not masked. It continues to operate normally.
0x1 : CH5OM_1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH6OM : Channel 6 Output Mask
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
0 : CH6OM_0
Channel output is not masked. It continues to operate normally.
0x1 : CH6OM_1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
CH7OM : Channel 7 Output Mask
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel output is not masked. It continues to operate normally.
#1 : 1
Channel output is masked. It is forced to its inactive state.
0 : CH7OM_0
Channel output is not masked. It continues to operate normally.
0x1 : CH7OM_1
Channel output is masked. It is forced to its inactive state.
End of enumeration elements list.
Mirror of Channel (n) Match Value
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL : Channel (n) Match Fractional Value
bits : 11 - 15 (5 bit)
access : read-write
VAL : Mirror of the Channel (n) Match Integer Value
bits : 16 - 31 (16 bit)
access : read-write
Function For Linked Channels
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMBINE0 : Combine Channels For n = 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channels (n) and (n+1) are independent.
#1 : 1
Channels (n) and (n+1) are combined.
End of enumeration elements list.
COMP0 : Complement Of Channel (n) For n = 0
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel (n+1) output is the same as the channel (n) output.
#1 : 1
The channel (n+1) output is the complement of the channel (n) output.
0 : COMP0_0
The channel (n+1) output is the same as the channel (n) output.
0x1 : COMP0_1
The channel (n+1) output is the complement of the channel (n) output.
End of enumeration elements list.
DECAPEN0 : Dual Edge Capture Mode Enable For n = 0
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The Dual Edge Capture mode in this pair of channels is disabled.
#1 : 1
The Dual Edge Capture mode in this pair of channels is enabled.
End of enumeration elements list.
DECAP0 : Dual Edge Capture Mode Captures For n = 0
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The dual edge captures are inactive.
#1 : 1
The dual edge captures are active.
0 : DECAP0_0
The dual edge captures are inactive.
0x1 : DECAP0_1
The dual edge captures are active.
End of enumeration elements list.
DTEN0 : Deadtime Enable For n = 0
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The deadtime insertion in this pair of channels is disabled.
#1 : 1
The deadtime insertion in this pair of channels is enabled.
0 : DTEN0_0
The deadtime insertion in this pair of channels is disabled.
0x1 : DTEN0_1
The deadtime insertion in this pair of channels is enabled.
End of enumeration elements list.
SYNCEN0 : Synchronization Enable For n = 0
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWM synchronization in this pair of channels is disabled.
#1 : 1
The PWM synchronization in this pair of channels is enabled.
0 : SYNCEN0_0
The PWM synchronization in this pair of channels is disabled.
0x1 : SYNCEN0_1
The PWM synchronization in this pair of channels is enabled.
End of enumeration elements list.
FAULTEN0 : Fault Control Enable For n = 0
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault control in this pair of channels is disabled.
#1 : 1
The fault control in this pair of channels is enabled.
0 : FAULTEN0_0
The fault control in this pair of channels is disabled.
0x1 : FAULTEN0_1
The fault control in this pair of channels is enabled.
End of enumeration elements list.
COMBINE1 : Combine Channels For n = 2
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channels (n) and (n+1) are independent.
#1 : 1
Channels (n) and (n+1) are combined.
End of enumeration elements list.
COMP1 : Complement Of Channel (n) For n = 2
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel (n+1) output is the same as the channel (n) output.
#1 : 1
The channel (n+1) output is the complement of the channel (n) output.
0 : COMP1_0
The channel (n+1) output is the same as the channel (n) output.
0x1 : COMP1_1
The channel (n+1) output is the complement of the channel (n) output.
End of enumeration elements list.
DECAPEN1 : Dual Edge Capture Mode Enable For n = 2
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The Dual Edge Capture mode in this pair of channels is disabled.
#1 : 1
The Dual Edge Capture mode in this pair of channels is enabled.
End of enumeration elements list.
DECAP1 : Dual Edge Capture Mode Captures For n = 2
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The dual edge captures are inactive.
#1 : 1
The dual edge captures are active.
0 : DECAP1_0
The dual edge captures are inactive.
0x1 : DECAP1_1
The dual edge captures are active.
End of enumeration elements list.
DTEN1 : Deadtime Enable For n = 2
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
The deadtime insertion in this pair of channels is disabled.
#1 : 1
The deadtime insertion in this pair of channels is enabled.
0 : DTEN1_0
The deadtime insertion in this pair of channels is disabled.
0x1 : DTEN1_1
The deadtime insertion in this pair of channels is enabled.
End of enumeration elements list.
SYNCEN1 : Synchronization Enable For n = 2
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWM synchronization in this pair of channels is disabled.
#1 : 1
The PWM synchronization in this pair of channels is enabled.
0 : SYNCEN1_0
The PWM synchronization in this pair of channels is disabled.
0x1 : SYNCEN1_1
The PWM synchronization in this pair of channels is enabled.
End of enumeration elements list.
FAULTEN1 : Fault Control Enable For n = 2
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault control in this pair of channels is disabled.
#1 : 1
The fault control in this pair of channels is enabled.
0 : FAULTEN1_0
The fault control in this pair of channels is disabled.
0x1 : FAULTEN1_1
The fault control in this pair of channels is enabled.
End of enumeration elements list.
COMBINE2 : Combine Channels For n = 4
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channels (n) and (n+1) are independent.
#1 : 1
Channels (n) and (n+1) are combined.
End of enumeration elements list.
COMP2 : Complement Of Channel (n) For n = 4
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel (n+1) output is the same as the channel (n) output.
#1 : 1
The channel (n+1) output is the complement of the channel (n) output.
0 : COMP2_0
The channel (n+1) output is the same as the channel (n) output.
0x1 : COMP2_1
The channel (n+1) output is the complement of the channel (n) output.
End of enumeration elements list.
DECAPEN2 : Dual Edge Capture Mode Enable For n = 4
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
The Dual Edge Capture mode in this pair of channels is disabled.
#1 : 1
The Dual Edge Capture mode in this pair of channels is enabled.
End of enumeration elements list.
DECAP2 : Dual Edge Capture Mode Captures For n = 4
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
The dual edge captures are inactive.
#1 : 1
The dual edge captures are active.
0 : DECAP2_0
The dual edge captures are inactive.
0x1 : DECAP2_1
The dual edge captures are active.
End of enumeration elements list.
DTEN2 : Deadtime Enable For n = 4
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
The deadtime insertion in this pair of channels is disabled.
#1 : 1
The deadtime insertion in this pair of channels is enabled.
0 : DTEN2_0
The deadtime insertion in this pair of channels is disabled.
0x1 : DTEN2_1
The deadtime insertion in this pair of channels is enabled.
End of enumeration elements list.
SYNCEN2 : Synchronization Enable For n = 4
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWM synchronization in this pair of channels is disabled.
#1 : 1
The PWM synchronization in this pair of channels is enabled.
0 : SYNCEN2_0
The PWM synchronization in this pair of channels is disabled.
0x1 : SYNCEN2_1
The PWM synchronization in this pair of channels is enabled.
End of enumeration elements list.
FAULTEN2 : Fault Control Enable For n = 4
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault control in this pair of channels is disabled.
#1 : 1
The fault control in this pair of channels is enabled.
0 : FAULTEN2_0
The fault control in this pair of channels is disabled.
0x1 : FAULTEN2_1
The fault control in this pair of channels is enabled.
End of enumeration elements list.
COMBINE3 : Combine Channels For n = 6
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channels (n) and (n+1) are independent.
#1 : 1
Channels (n) and (n+1) are combined.
End of enumeration elements list.
COMP3 : Complement Of Channel (n) for n = 6
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel (n+1) output is the same as the channel (n) output.
#1 : 1
The channel (n+1) output is the complement of the channel (n) output.
0 : COMP3_0
The channel (n+1) output is the same as the channel (n) output.
0x1 : COMP3_1
The channel (n+1) output is the complement of the channel (n) output.
End of enumeration elements list.
DECAPEN3 : Dual Edge Capture Mode Enable For n = 6
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
The Dual Edge Capture mode in this pair of channels is disabled.
#1 : 1
The Dual Edge Capture mode in this pair of channels is enabled.
End of enumeration elements list.
DECAP3 : Dual Edge Capture Mode Captures For n = 6
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
The dual edge captures are inactive.
#1 : 1
The dual edge captures are active.
0 : DECAP3_0
The dual edge captures are inactive.
0x1 : DECAP3_1
The dual edge captures are active.
End of enumeration elements list.
DTEN3 : Deadtime Enable For n = 6
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
The deadtime insertion in this pair of channels is disabled.
#1 : 1
The deadtime insertion in this pair of channels is enabled.
0 : DTEN3_0
The deadtime insertion in this pair of channels is disabled.
0x1 : DTEN3_1
The deadtime insertion in this pair of channels is enabled.
End of enumeration elements list.
SYNCEN3 : Synchronization Enable For n = 6
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWM synchronization in this pair of channels is disabled.
#1 : 1
The PWM synchronization in this pair of channels is enabled.
0 : SYNCEN3_0
The PWM synchronization in this pair of channels is disabled.
0x1 : SYNCEN3_1
The PWM synchronization in this pair of channels is enabled.
End of enumeration elements list.
FAULTEN3 : Fault Control Enable For n = 6
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault control in this pair of channels is disabled.
#1 : 1
The fault control in this pair of channels is enabled.
0 : FAULTEN3_0
The fault control in this pair of channels is disabled.
0x1 : FAULTEN3_1
The fault control in this pair of channels is enabled.
End of enumeration elements list.
Deadtime Configuration
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTVAL : Deadtime Value
bits : 0 - 5 (6 bit)
access : read-write
DTPS : Deadtime Prescaler Value
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#0x : 0x
Divide the FTM input clock by 1.
#10 : 10
Divide the FTM input clock by 4.
#11 : 11
Divide the FTM input clock by 16.
#0x : DTPS_0
Divide the FTM input clock by 1.
0x2 : DTPS_2
Divide the FTM input clock by 4.
0x3 : DTPS_3
Divide the FTM input clock by 16.
End of enumeration elements list.
DTVALEX : Extended Deadtime Value
bits : 16 - 19 (4 bit)
access : read-write
Channel (n) Status And Control
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DMA transfers.
#1 : 1
Enable DMA transfers.
0 : DMA_0
Disable DMA transfers.
0x1 : DMA_1
Enable DMA transfers.
End of enumeration elements list.
ICRST : FTM counter reset by the selected input capture event.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter is not reset when the selected channel (n) input event is detected.
#1 : 1
FTM counter is reset when the selected channel (n) input event is detected.
0 : ICRST_0
FTM counter is not reset when the selected channel (n) input event is detected.
0x1 : ICRST_1
FTM counter is reset when the selected channel (n) input event is detected.
End of enumeration elements list.
ELSA : Channel (n) Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Channel (n) Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel (n) Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel (n) Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel (n) Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel (n) interrupt. Use software polling.
#1 : 1
Enable channel (n) interrupt.
0 : CHIE_0
Disable channel (n) interrupt. Use software polling.
0x1 : CHIE_1
Enable channel (n) interrupt.
End of enumeration elements list.
CHF : Channel (n) Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel (n) event has occurred.
#1 : 1
A channel (n) event has occurred.
0 : CHF_0
No channel (n) event has occurred.
0x1 : CHF_1
A channel (n) event has occurred.
End of enumeration elements list.
TRIGMODE : Trigger mode control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel outputs will generate the normal PWM outputs without generating a pulse.
#1 : 1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
0 : TRIGMODE_0
Channel outputs will generate the normal PWM outputs without generating a pulse.
0x1 : TRIGMODE_1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
End of enumeration elements list.
CHIS : Channel (n) Input State
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) input is zero.
#1 : 1
The channel (n) input is one.
0 : CHIS_0
The channel (n) input is zero.
0x1 : CHIS_1
The channel (n) input is one.
End of enumeration elements list.
FTM External Trigger
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2TRIG : Channel 2 Trigger Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of the channel trigger is disabled.
#1 : 1
The generation of the channel trigger is enabled.
0 : CH2TRIG_0
The generation of the channel trigger is disabled.
0x1 : CH2TRIG_1
The generation of the channel trigger is enabled.
End of enumeration elements list.
CH3TRIG : Channel 3 Trigger Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of the channel trigger is disabled.
#1 : 1
The generation of the channel trigger is enabled.
0 : CH3TRIG_0
The generation of the channel trigger is disabled.
0x1 : CH3TRIG_1
The generation of the channel trigger is enabled.
End of enumeration elements list.
CH4TRIG : Channel 4 Trigger Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of the channel trigger is disabled.
#1 : 1
The generation of the channel trigger is enabled.
0 : CH4TRIG_0
The generation of the channel trigger is disabled.
0x1 : CH4TRIG_1
The generation of the channel trigger is enabled.
End of enumeration elements list.
CH5TRIG : Channel 5 Trigger Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of the channel trigger is disabled.
#1 : 1
The generation of the channel trigger is enabled.
0 : CH5TRIG_0
The generation of the channel trigger is disabled.
0x1 : CH5TRIG_1
The generation of the channel trigger is enabled.
End of enumeration elements list.
CH0TRIG : Channel 0 Trigger Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of the channel trigger is disabled.
#1 : 1
The generation of the channel trigger is enabled.
0 : CH0TRIG_0
The generation of the channel trigger is disabled.
0x1 : CH0TRIG_1
The generation of the channel trigger is enabled.
End of enumeration elements list.
CH1TRIG : Channel 1 Trigger Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of the channel trigger is disabled.
#1 : 1
The generation of the channel trigger is enabled.
0 : CH1TRIG_0
The generation of the channel trigger is disabled.
0x1 : CH1TRIG_1
The generation of the channel trigger is enabled.
End of enumeration elements list.
INITTRIGEN : Initialization Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of initialization trigger is disabled.
#1 : 1
The generation of initialization trigger is enabled.
0 : INITTRIGEN_0
The generation of initialization trigger is disabled.
0x1 : INITTRIGEN_1
The generation of initialization trigger is enabled.
End of enumeration elements list.
TRIGF : Channel Trigger Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel trigger was generated.
#1 : 1
A channel trigger was generated.
0 : TRIGF_0
No channel trigger was generated.
0x1 : TRIGF_1
A channel trigger was generated.
End of enumeration elements list.
CH6TRIG : Channel 6 Trigger Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of the channel trigger is disabled.
#1 : 1
The generation of the channel trigger is enabled.
0 : CH6TRIG_0
The generation of the channel trigger is disabled.
0x1 : CH6TRIG_1
The generation of the channel trigger is enabled.
End of enumeration elements list.
CH7TRIG : Channel 7 Trigger Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The generation of the channel trigger is disabled.
#1 : 1
The generation of the channel trigger is enabled.
0 : CH7TRIG_0
The generation of the channel trigger is disabled.
0x1 : CH7TRIG_1
The generation of the channel trigger is enabled.
End of enumeration elements list.
Channels Polarity
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POL0 : Channel 0 Polarity
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
0 : POL0_0
The channel polarity is active high.
0x1 : POL0_1
The channel polarity is active low.
End of enumeration elements list.
POL1 : Channel 1 Polarity
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
0 : POL1_0
The channel polarity is active high.
0x1 : POL1_1
The channel polarity is active low.
End of enumeration elements list.
POL2 : Channel 2 Polarity
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
0 : POL2_0
The channel polarity is active high.
0x1 : POL2_1
The channel polarity is active low.
End of enumeration elements list.
POL3 : Channel 3 Polarity
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
0 : POL3_0
The channel polarity is active high.
0x1 : POL3_1
The channel polarity is active low.
End of enumeration elements list.
POL4 : Channel 4 Polarity
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
0 : POL4_0
The channel polarity is active high.
0x1 : POL4_1
The channel polarity is active low.
End of enumeration elements list.
POL5 : Channel 5 Polarity
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
0 : POL5_0
The channel polarity is active high.
0x1 : POL5_1
The channel polarity is active low.
End of enumeration elements list.
POL6 : Channel 6 Polarity
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
0 : POL6_0
The channel polarity is active high.
0x1 : POL6_1
The channel polarity is active low.
End of enumeration elements list.
POL7 : Channel 7 Polarity
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
0 : POL7_0
The channel polarity is active high.
0x1 : POL7_1
The channel polarity is active low.
End of enumeration elements list.
Fault Mode Status
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAULTF0 : Fault Detection Flag 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No fault condition was detected at the fault input.
#1 : 1
A fault condition was detected at the fault input.
0 : FAULTF0_0
No fault condition was detected at the fault input.
0x1 : FAULTF0_1
A fault condition was detected at the fault input.
End of enumeration elements list.
FAULTF1 : Fault Detection Flag 1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No fault condition was detected at the fault input.
#1 : 1
A fault condition was detected at the fault input.
0 : FAULTF1_0
No fault condition was detected at the fault input.
0x1 : FAULTF1_1
A fault condition was detected at the fault input.
End of enumeration elements list.
FAULTF2 : Fault Detection Flag 2
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No fault condition was detected at the fault input.
#1 : 1
A fault condition was detected at the fault input.
0 : FAULTF2_0
No fault condition was detected at the fault input.
0x1 : FAULTF2_1
A fault condition was detected at the fault input.
End of enumeration elements list.
FAULTF3 : Fault Detection Flag 3
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No fault condition was detected at the fault input.
#1 : 1
A fault condition was detected at the fault input.
0 : FAULTF3_0
No fault condition was detected at the fault input.
0x1 : FAULTF3_1
A fault condition was detected at the fault input.
End of enumeration elements list.
FAULTIN : Fault Inputs
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
The logic OR of the enabled fault inputs is 0.
#1 : 1
The logic OR of the enabled fault inputs is 1.
0 : FAULTIN_0
The logic OR of the enabled fault inputs is 0.
0x1 : FAULTIN_1
The logic OR of the enabled fault inputs is 1.
End of enumeration elements list.
WPEN : Write Protection Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Write protection is disabled. Write protected bits can be written.
#1 : 1
Write protection is enabled. Write protected bits cannot be written.
0 : WPEN_0
Write protection is disabled. Write protected bits can be written.
0x1 : WPEN_1
Write protection is enabled. Write protected bits cannot be written.
End of enumeration elements list.
FAULTF : Fault Detection Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No fault condition was detected.
#1 : 1
A fault condition was detected.
0 : FAULTF_0
No fault condition was detected.
0x1 : FAULTF_1
A fault condition was detected.
End of enumeration elements list.
Input Capture Filter Control
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0FVAL : Channel 0 Input Filter
bits : 0 - 3 (4 bit)
access : read-write
CH1FVAL : Channel 1 Input Filter
bits : 4 - 7 (4 bit)
access : read-write
CH2FVAL : Channel 2 Input Filter
bits : 8 - 11 (4 bit)
access : read-write
CH3FVAL : Channel 3 Input Filter
bits : 12 - 15 (4 bit)
access : read-write
Fault Control
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAULT0EN : Fault Input 0 Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input is disabled.
#1 : 1
Fault input is enabled.
0 : FAULT0EN_0
Fault input is disabled.
0x1 : FAULT0EN_1
Fault input is enabled.
End of enumeration elements list.
FAULT1EN : Fault Input 1 Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input is disabled.
#1 : 1
Fault input is enabled.
0 : FAULT1EN_0
Fault input is disabled.
0x1 : FAULT1EN_1
Fault input is enabled.
End of enumeration elements list.
FAULT2EN : Fault Input 2 Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input is disabled.
#1 : 1
Fault input is enabled.
0 : FAULT2EN_0
Fault input is disabled.
0x1 : FAULT2EN_1
Fault input is enabled.
End of enumeration elements list.
FAULT3EN : Fault Input 3 Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input is disabled.
#1 : 1
Fault input is enabled.
0 : FAULT3EN_0
Fault input is disabled.
0x1 : FAULT3EN_1
Fault input is enabled.
End of enumeration elements list.
FFLTR0EN : Fault Input 0 Filter Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input filter is disabled.
#1 : 1
Fault input filter is enabled.
0 : FFLTR0EN_0
Fault input filter is disabled.
0x1 : FFLTR0EN_1
Fault input filter is enabled.
End of enumeration elements list.
FFLTR1EN : Fault Input 1 Filter Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input filter is disabled.
#1 : 1
Fault input filter is enabled.
0 : FFLTR1EN_0
Fault input filter is disabled.
0x1 : FFLTR1EN_1
Fault input filter is enabled.
End of enumeration elements list.
FFLTR2EN : Fault Input 2 Filter Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input filter is disabled.
#1 : 1
Fault input filter is enabled.
0 : FFLTR2EN_0
Fault input filter is disabled.
0x1 : FFLTR2EN_1
Fault input filter is enabled.
End of enumeration elements list.
FFLTR3EN : Fault Input 3 Filter Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault input filter is disabled.
#1 : 1
Fault input filter is enabled.
0 : FFLTR3EN_0
Fault input filter is disabled.
0x1 : FFLTR3EN_1
Fault input filter is enabled.
End of enumeration elements list.
FFVAL : Fault Input Filter
bits : 8 - 11 (4 bit)
access : read-write
FSTATE : Fault output state
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits).
#1 : 1
FTM outputs will be tri-stated when fault event is ongoing
0 : FSTATE_0
FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits).
0x1 : FSTATE_1
FTM outputs will be tri-stated when fault event is ongoing
End of enumeration elements list.
Modulo
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD : Modulo Value
bits : 0 - 15 (16 bit)
access : read-write
Channel (n) Value
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Quadrature Decoder Control And Status
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QUADEN : Quadrature Decoder Mode Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Quadrature Decoder mode is disabled.
#1 : 1
Quadrature Decoder mode is enabled.
0 : QUADEN_0
Quadrature Decoder mode is disabled.
0x1 : QUADEN_1
Quadrature Decoder mode is enabled.
End of enumeration elements list.
TOFDIR : Timer Overflow Direction In Quadrature Decoder Mode
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).
#1 : 1
TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).
0 : TOFDIR_0
TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).
0x1 : TOFDIR_1
TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).
End of enumeration elements list.
QUADIR : FTM Counter Direction In Quadrature Decoder Mode
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Counting direction is decreasing (FTM counter decrement).
#1 : 1
Counting direction is increasing (FTM counter increment).
0 : QUADIR_0
Counting direction is decreasing (FTM counter decrement).
0x1 : QUADIR_1
Counting direction is increasing (FTM counter increment).
End of enumeration elements list.
QUADMODE : Quadrature Decoder Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Phase A and phase B encoding mode.
#1 : 1
Count and direction encoding mode.
0 : QUADMODE_0
Phase A and phase B encoding mode.
0x1 : QUADMODE_1
Count and direction encoding mode.
End of enumeration elements list.
PHBPOL : Phase B Input Polarity
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.
#1 : 1
Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.
0 : PHBPOL_0
Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.
0x1 : PHBPOL_1
Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.
End of enumeration elements list.
PHAPOL : Phase A Input Polarity
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.
#1 : 1
Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.
0 : PHAPOL_0
Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.
0x1 : PHAPOL_1
Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.
End of enumeration elements list.
PHBFLTREN : Phase B Input Filter Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Phase B input filter is disabled.
#1 : 1
Phase B input filter is enabled.
0 : PHBFLTREN_0
Phase B input filter is disabled.
0x1 : PHBFLTREN_1
Phase B input filter is enabled.
End of enumeration elements list.
PHAFLTREN : Phase A Input Filter Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Phase A input filter is disabled.
#1 : 1
Phase A input filter is enabled.
0 : PHAFLTREN_0
Phase A input filter is disabled.
0x1 : PHAFLTREN_1
Phase A input filter is enabled.
End of enumeration elements list.
Mirror of Channel (n) Match Value
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL : Channel (n) Match Fractional Value
bits : 11 - 15 (5 bit)
access : read-write
VAL : Mirror of the Channel (n) Match Integer Value
bits : 16 - 31 (16 bit)
access : read-write
Configuration
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LDFQ : Load Frequency
bits : 0 - 4 (5 bit)
access : read-write
BDMMODE : Debug Mode
bits : 6 - 7 (2 bit)
access : read-write
GTBEEN : Global Time Base Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Use of an external global time base is disabled.
#1 : 1
Use of an external global time base is enabled.
0 : GTBEEN_0
Use of an external global time base is disabled.
0x1 : GTBEEN_1
Use of an external global time base is enabled.
End of enumeration elements list.
GTBEOUT : Global Time Base Output
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
A global time base signal generation is disabled.
#1 : 1
A global time base signal generation is enabled.
0 : GTBEOUT_0
A global time base signal generation is disabled.
0x1 : GTBEOUT_1
A global time base signal generation is enabled.
End of enumeration elements list.
ITRIGR : Initialization trigger on Reload Point
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Initialization trigger is generated on counter wrap events.
#1 : 1
Initialization trigger is generated when a reload point is reached.
0 : ITRIGR_0
Initialization trigger is generated on counter wrap events.
0x1 : ITRIGR_1
Initialization trigger is generated when a reload point is reached.
End of enumeration elements list.
FTM Fault Input Polarity
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLT0POL : Fault Input 0 Polarity
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#1 : 1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
0 : FLT0POL_0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
0x1 : FLT0POL_1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
End of enumeration elements list.
FLT1POL : Fault Input 1 Polarity
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#1 : 1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
0 : FLT1POL_0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
0x1 : FLT1POL_1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
End of enumeration elements list.
FLT2POL : Fault Input 2 Polarity
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#1 : 1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
0 : FLT2POL_0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
0x1 : FLT2POL_1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
End of enumeration elements list.
FLT3POL : Fault Input 3 Polarity
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
#1 : 1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
0 : FLT3POL_0
The fault input polarity is active high. A 1 at the fault input indicates a fault.
0x1 : FLT3POL_1
The fault input polarity is active low. A 0 at the fault input indicates a fault.
End of enumeration elements list.
Synchronization Configuration
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HWTRIGMODE : Hardware Trigger Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
#1 : 1
FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
0 : HWTRIGMODE_0
FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
0x1 : HWTRIGMODE_1
FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
End of enumeration elements list.
CNTINC : CNTIN Register Synchronization
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
CNTIN register is updated with its buffer value at all rising edges of FTM input clock.
#1 : 1
CNTIN register is updated with its buffer value by the PWM synchronization.
0 : CNTINC_0
CNTIN register is updated with its buffer value at all rising edges of FTM input clock.
0x1 : CNTINC_1
CNTIN register is updated with its buffer value by the PWM synchronization.
End of enumeration elements list.
INVC : INVCTRL Register Synchronization
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
INVCTRL register is updated with its buffer value at all rising edges of FTM input clock.
#1 : 1
INVCTRL register is updated with its buffer value by the PWM synchronization.
0 : INVC_0
INVCTRL register is updated with its buffer value at all rising edges of FTM input clock.
0x1 : INVC_1
INVCTRL register is updated with its buffer value by the PWM synchronization.
End of enumeration elements list.
SWOC : SWOCTRL Register Synchronization
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock.
#1 : 1
SWOCTRL register is updated with its buffer value by the PWM synchronization.
0 : SWOC_0
SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock.
0x1 : SWOC_1
SWOCTRL register is updated with its buffer value by the PWM synchronization.
End of enumeration elements list.
SYNCMODE : Synchronization Mode
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Legacy PWM synchronization is selected.
#1 : 1
Enhanced PWM synchronization is selected.
0 : SYNCMODE_0
Legacy PWM synchronization is selected.
0x1 : SYNCMODE_1
Enhanced PWM synchronization is selected.
End of enumeration elements list.
SWRSTCNT : FTM counter synchronization is activated by the software trigger.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software trigger does not activate the FTM counter synchronization.
#1 : 1
The software trigger activates the FTM counter synchronization.
0 : SWRSTCNT_0
The software trigger does not activate the FTM counter synchronization.
0x1 : SWRSTCNT_1
The software trigger activates the FTM counter synchronization.
End of enumeration elements list.
SWWRBUF : MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization.
#1 : 1
The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization.
0 : SWWRBUF_0
The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization.
0x1 : SWWRBUF_1
The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization.
End of enumeration elements list.
SWOM : Output mask synchronization is activated by the software trigger.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software trigger does not activate the OUTMASK register synchronization.
#1 : 1
The software trigger activates the OUTMASK register synchronization.
0 : SWOM_0
The software trigger does not activate the OUTMASK register synchronization.
0x1 : SWOM_1
The software trigger activates the OUTMASK register synchronization.
End of enumeration elements list.
SWINVC : Inverting control synchronization is activated by the software trigger.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software trigger does not activate the INVCTRL register synchronization.
#1 : 1
The software trigger activates the INVCTRL register synchronization.
0 : SWINVC_0
The software trigger does not activate the INVCTRL register synchronization.
0x1 : SWINVC_1
The software trigger activates the INVCTRL register synchronization.
End of enumeration elements list.
SWSOC : Software output control synchronization is activated by the software trigger.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software trigger does not activate the SWOCTRL register synchronization.
#1 : 1
The software trigger activates the SWOCTRL register synchronization.
0 : SWSOC_0
The software trigger does not activate the SWOCTRL register synchronization.
0x1 : SWSOC_1
The software trigger activates the SWOCTRL register synchronization.
End of enumeration elements list.
HWRSTCNT : FTM counter synchronization is activated by a hardware trigger.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
A hardware trigger does not activate the FTM counter synchronization.
#1 : 1
A hardware trigger activates the FTM counter synchronization.
0 : HWRSTCNT_0
A hardware trigger does not activate the FTM counter synchronization.
0x1 : HWRSTCNT_1
A hardware trigger activates the FTM counter synchronization.
End of enumeration elements list.
HWWRBUF : MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization.
#1 : 1
A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization.
0 : HWWRBUF_0
A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization.
0x1 : HWWRBUF_1
A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization.
End of enumeration elements list.
HWOM : Output mask synchronization is activated by a hardware trigger.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
A hardware trigger does not activate the OUTMASK register synchronization.
#1 : 1
A hardware trigger activates the OUTMASK register synchronization.
0 : HWOM_0
A hardware trigger does not activate the OUTMASK register synchronization.
0x1 : HWOM_1
A hardware trigger activates the OUTMASK register synchronization.
End of enumeration elements list.
HWINVC : Inverting control synchronization is activated by a hardware trigger.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
A hardware trigger does not activate the INVCTRL register synchronization.
#1 : 1
A hardware trigger activates the INVCTRL register synchronization.
0 : HWINVC_0
A hardware trigger does not activate the INVCTRL register synchronization.
0x1 : HWINVC_1
A hardware trigger activates the INVCTRL register synchronization.
End of enumeration elements list.
HWSOC : Software output control synchronization is activated by a hardware trigger.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
A hardware trigger does not activate the SWOCTRL register synchronization.
#1 : 1
A hardware trigger activates the SWOCTRL register synchronization.
0 : HWSOC_0
A hardware trigger does not activate the SWOCTRL register synchronization.
0x1 : HWSOC_1
A hardware trigger activates the SWOCTRL register synchronization.
End of enumeration elements list.
FTM Inverting Control
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV0EN : Pair Channels 0 Inverting Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverting is disabled.
#1 : 1
Inverting is enabled.
0 : INV0EN_0
Inverting is disabled.
0x1 : INV0EN_1
Inverting is enabled.
End of enumeration elements list.
INV1EN : Pair Channels 1 Inverting Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverting is disabled.
#1 : 1
Inverting is enabled.
0 : INV1EN_0
Inverting is disabled.
0x1 : INV1EN_1
Inverting is enabled.
End of enumeration elements list.
INV2EN : Pair Channels 2 Inverting Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverting is disabled.
#1 : 1
Inverting is enabled.
0 : INV2EN_0
Inverting is disabled.
0x1 : INV2EN_1
Inverting is enabled.
End of enumeration elements list.
INV3EN : Pair Channels 3 Inverting Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inverting is disabled.
#1 : 1
Inverting is enabled.
0 : INV3EN_0
Inverting is disabled.
0x1 : INV3EN_1
Inverting is enabled.
End of enumeration elements list.
FTM Software Output Control
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0OC : Channel 0 Software Output Control Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
0 : CH0OC_0
The channel output is not affected by software output control.
0x1 : CH0OC_1
The channel output is affected by software output control.
End of enumeration elements list.
CH1OC : Channel 1 Software Output Control Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
0 : CH1OC_0
The channel output is not affected by software output control.
0x1 : CH1OC_1
The channel output is affected by software output control.
End of enumeration elements list.
CH2OC : Channel 2 Software Output Control Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
0 : CH2OC_0
The channel output is not affected by software output control.
0x1 : CH2OC_1
The channel output is affected by software output control.
End of enumeration elements list.
CH3OC : Channel 3 Software Output Control Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
0 : CH3OC_0
The channel output is not affected by software output control.
0x1 : CH3OC_1
The channel output is affected by software output control.
End of enumeration elements list.
CH4OC : Channel 4 Software Output Control Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
0 : CH4OC_0
The channel output is not affected by software output control.
0x1 : CH4OC_1
The channel output is affected by software output control.
End of enumeration elements list.
CH5OC : Channel 5 Software Output Control Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
0 : CH5OC_0
The channel output is not affected by software output control.
0x1 : CH5OC_1
The channel output is affected by software output control.
End of enumeration elements list.
CH6OC : Channel 6 Software Output Control Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
0 : CH6OC_0
The channel output is not affected by software output control.
0x1 : CH6OC_1
The channel output is affected by software output control.
End of enumeration elements list.
CH7OC : Channel 7 Software Output Control Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel output is not affected by software output control.
#1 : 1
The channel output is affected by software output control.
0 : CH7OC_0
The channel output is not affected by software output control.
0x1 : CH7OC_1
The channel output is affected by software output control.
End of enumeration elements list.
CH0OCV : Channel 0 Software Output Control Value
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
0 : CH0OCV_0
The software output control forces 0 to the channel output.
0x1 : CH0OCV_1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH1OCV : Channel 1 Software Output Control Value
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
0 : CH1OCV_0
The software output control forces 0 to the channel output.
0x1 : CH1OCV_1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH2OCV : Channel 2 Software Output Control Value
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
0 : CH2OCV_0
The software output control forces 0 to the channel output.
0x1 : CH2OCV_1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH3OCV : Channel 3 Software Output Control Value
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
0 : CH3OCV_0
The software output control forces 0 to the channel output.
0x1 : CH3OCV_1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH4OCV : Channel 4 Software Output Control Value
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
0 : CH4OCV_0
The software output control forces 0 to the channel output.
0x1 : CH4OCV_1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH5OCV : Channel 5 Software Output Control Value
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
0 : CH5OCV_0
The software output control forces 0 to the channel output.
0x1 : CH5OCV_1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH6OCV : Channel 6 Software Output Control Value
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
0 : CH6OCV_0
The software output control forces 0 to the channel output.
0x1 : CH6OCV_1
The software output control forces 1 to the channel output.
End of enumeration elements list.
CH7OCV : Channel 7 Software Output Control Value
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The software output control forces 0 to the channel output.
#1 : 1
The software output control forces 1 to the channel output.
0 : CH7OCV_0
The software output control forces 0 to the channel output.
0x1 : CH7OCV_1
The software output control forces 1 to the channel output.
End of enumeration elements list.
Channel (n) Status And Control
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DMA transfers.
#1 : 1
Enable DMA transfers.
0 : DMA_0
Disable DMA transfers.
0x1 : DMA_1
Enable DMA transfers.
End of enumeration elements list.
ICRST : FTM counter reset by the selected input capture event.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter is not reset when the selected channel (n) input event is detected.
#1 : 1
FTM counter is reset when the selected channel (n) input event is detected.
0 : ICRST_0
FTM counter is not reset when the selected channel (n) input event is detected.
0x1 : ICRST_1
FTM counter is reset when the selected channel (n) input event is detected.
End of enumeration elements list.
ELSA : Channel (n) Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Channel (n) Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel (n) Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel (n) Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel (n) Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel (n) interrupt. Use software polling.
#1 : 1
Enable channel (n) interrupt.
0 : CHIE_0
Disable channel (n) interrupt. Use software polling.
0x1 : CHIE_1
Enable channel (n) interrupt.
End of enumeration elements list.
CHF : Channel (n) Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel (n) event has occurred.
#1 : 1
A channel (n) event has occurred.
0 : CHF_0
No channel (n) event has occurred.
0x1 : CHF_1
A channel (n) event has occurred.
End of enumeration elements list.
TRIGMODE : Trigger mode control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel outputs will generate the normal PWM outputs without generating a pulse.
#1 : 1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
0 : TRIGMODE_0
Channel outputs will generate the normal PWM outputs without generating a pulse.
0x1 : TRIGMODE_1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
End of enumeration elements list.
CHIS : Channel (n) Input State
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) input is zero.
#1 : 1
The channel (n) input is one.
0 : CHIS_0
The channel (n) input is zero.
0x1 : CHIS_1
The channel (n) input is one.
End of enumeration elements list.
FTM PWM Load
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0SEL : Channel 0 Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel match is not included as a reload opportunity.
#1 : 1
Channel match is included as a reload opportunity.
0 : CH0SEL_0
Channel match is not included as a reload opportunity.
0x1 : CH0SEL_1
Channel match is included as a reload opportunity.
End of enumeration elements list.
CH1SEL : Channel 1 Select
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel match is not included as a reload opportunity.
#1 : 1
Channel match is included as a reload opportunity.
0 : CH1SEL_0
Channel match is not included as a reload opportunity.
0x1 : CH1SEL_1
Channel match is included as a reload opportunity.
End of enumeration elements list.
CH2SEL : Channel 2 Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel match is not included as a reload opportunity.
#1 : 1
Channel match is included as a reload opportunity.
0 : CH2SEL_0
Channel match is not included as a reload opportunity.
0x1 : CH2SEL_1
Channel match is included as a reload opportunity.
End of enumeration elements list.
CH3SEL : Channel 3 Select
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel match is not included as a reload opportunity.
#1 : 1
Channel match is included as a reload opportunity.
0 : CH3SEL_0
Channel match is not included as a reload opportunity.
0x1 : CH3SEL_1
Channel match is included as a reload opportunity.
End of enumeration elements list.
CH4SEL : Channel 4 Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel match is not included as a reload opportunity.
#1 : 1
Channel match is included as a reload opportunity.
0 : CH4SEL_0
Channel match is not included as a reload opportunity.
0x1 : CH4SEL_1
Channel match is included as a reload opportunity.
End of enumeration elements list.
CH5SEL : Channel 5 Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel match is not included as a reload opportunity.
#1 : 1
Channel match is included as a reload opportunity.
0 : CH5SEL_0
Channel match is not included as a reload opportunity.
0x1 : CH5SEL_1
Channel match is included as a reload opportunity.
End of enumeration elements list.
CH6SEL : Channel 6 Select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel match is not included as a reload opportunity.
#1 : 1
Channel match is included as a reload opportunity.
0 : CH6SEL_0
Channel match is not included as a reload opportunity.
0x1 : CH6SEL_1
Channel match is included as a reload opportunity.
End of enumeration elements list.
CH7SEL : Channel 7 Select
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel match is not included as a reload opportunity.
#1 : 1
Channel match is included as a reload opportunity.
0 : CH7SEL_0
Channel match is not included as a reload opportunity.
0x1 : CH7SEL_1
Channel match is included as a reload opportunity.
End of enumeration elements list.
HCSEL : Half Cycle Select
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Half cycle reload is disabled and it is not considered as a reload opportunity.
#1 : 1
Half cycle reload is enabled and it is considered as a reload opportunity.
0 : HCSEL_0
Half cycle reload is disabled and it is not considered as a reload opportunity.
0x1 : HCSEL_1
Half cycle reload is enabled and it is considered as a reload opportunity.
End of enumeration elements list.
LDOK : Load Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Loading updated values is disabled.
#1 : 1
Loading updated values is enabled.
0 : LDOK_0
Loading updated values is disabled.
0x1 : LDOK_1
Loading updated values is enabled.
End of enumeration elements list.
GLEN : Global Load Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Global Load Ok disabled.
#1 : 1
Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit.
0 : GLEN_0
Global Load Ok disabled.
0x1 : GLEN_1
Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit.
End of enumeration elements list.
GLDOK : Global Load OK
bits : 11 - 11 (1 bit)
access : write-only
Enumeration:
#0 : 0
No action.
#1 : 1
LDOK bit is set.
0 : GLDOK_0
No action.
0x1 : GLDOK_1
LDOK bit is set.
End of enumeration elements list.
Half Cycle Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCVAL : Half Cycle Value
bits : 0 - 15 (16 bit)
access : read-write
Mirror of Channel (n) Match Value
address_offset : 0xA2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL : Channel (n) Match Fractional Value
bits : 11 - 15 (5 bit)
access : read-write
VAL : Mirror of the Channel (n) Match Integer Value
bits : 16 - 31 (16 bit)
access : read-write
Channel (n) Value
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Mirror of Channel (n) Match Value
address_offset : 0xC40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL : Channel (n) Match Fractional Value
bits : 11 - 15 (5 bit)
access : read-write
VAL : Mirror of the Channel (n) Match Integer Value
bits : 16 - 31 (16 bit)
access : read-write
Channel (n) Status And Control
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DMA transfers.
#1 : 1
Enable DMA transfers.
0 : DMA_0
Disable DMA transfers.
0x1 : DMA_1
Enable DMA transfers.
End of enumeration elements list.
ICRST : FTM counter reset by the selected input capture event.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FTM counter is not reset when the selected channel (n) input event is detected.
#1 : 1
FTM counter is reset when the selected channel (n) input event is detected.
0 : ICRST_0
FTM counter is not reset when the selected channel (n) input event is detected.
0x1 : ICRST_1
FTM counter is reset when the selected channel (n) input event is detected.
End of enumeration elements list.
ELSA : Channel (n) Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Channel (n) Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel (n) Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel (n) Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel (n) Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel (n) interrupt. Use software polling.
#1 : 1
Enable channel (n) interrupt.
0 : CHIE_0
Disable channel (n) interrupt. Use software polling.
0x1 : CHIE_1
Enable channel (n) interrupt.
End of enumeration elements list.
CHF : Channel (n) Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel (n) event has occurred.
#1 : 1
A channel (n) event has occurred.
0 : CHF_0
No channel (n) event has occurred.
0x1 : CHF_1
A channel (n) event has occurred.
End of enumeration elements list.
TRIGMODE : Trigger mode control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel outputs will generate the normal PWM outputs without generating a pulse.
#1 : 1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
0 : TRIGMODE_0
Channel outputs will generate the normal PWM outputs without generating a pulse.
0x1 : TRIGMODE_1
If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
End of enumeration elements list.
CHIS : Channel (n) Input State
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
The channel (n) input is zero.
#1 : 1
The channel (n) input is one.
0 : CHIS_0
The channel (n) input is zero.
0x1 : CHIS_1
The channel (n) input is one.
End of enumeration elements list.
Mirror of Channel (n) Match Value
address_offset : 0xE58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACVAL : Channel (n) Match Fractional Value
bits : 11 - 15 (5 bit)
access : read-write
VAL : Mirror of the Channel (n) Match Integer Value
bits : 16 - 31 (16 bit)
access : read-write
Channel (n) Value
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
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