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RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TSR

CR

SR

LR

IER

TPR

TAR

TCR


TSR

RTC Time Seconds Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSR TSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSR

TSR : Time Seconds Register
bits : 0 - 31 (32 bit)
access : read-write


CR

RTC Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWR WPE SUP UM RESERVED OSCE CLKO SC16P SC8P SC4P SC2P RESERVED RESERVED

SWR : Software Reset
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect.

#1 : 1

Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it.

End of enumeration elements list.

WPE : Wakeup Pin Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Wakeup pin is disabled.

#1 : 1

Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on.

End of enumeration elements list.

SUP : Supervisor Access
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Non-supervisor mode write accesses are not supported and generate a bus error.

#1 : 1

Non-supervisor mode write accesses are supported.

End of enumeration elements list.

UM : Update Mode
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Registers cannot be written when locked.

#1 : 1

Registers can be written when locked under limited conditions.

End of enumeration elements list.

RESERVED : no description available
bits : 4 - 7 (4 bit)
access : read-only

OSCE : Oscillator Enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

32.768 kHz oscillator is disabled.

#1 : 1

32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.

End of enumeration elements list.

CLKO : Clock Output
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

The 32 kHz clock is output to other peripherals.

#1 : 1

The 32 kHz clock is not output to other peripherals.

End of enumeration elements list.

SC16P : Oscillator 16pF Load Configure
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the load.

#1 : 1

Enable the additional load.

End of enumeration elements list.

SC8P : Oscillator 8pF Load Configure
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the load.

#1 : 1

Enable the additional load.

End of enumeration elements list.

SC4P : Oscillator 4pF Load Configure
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the load.

#1 : 1

Enable the additional load.

End of enumeration elements list.

SC2P : Oscillator 2pF Load Configure
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the load.

#1 : 1

Enable the additional load.

End of enumeration elements list.

RESERVED : no description available
bits : 14 - 14 (1 bit)
access : read-only

RESERVED : no description available
bits : 15 - 31 (17 bit)
access : read-only


SR

RTC Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIF TOF TAF RESERVED TCE RESERVED

TIF : Time Invalid Flag
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Time is valid.

#1 : 1

Time is invalid and time counter is read as zero.

End of enumeration elements list.

TOF : Time Overflow Flag
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Time overflow has not occurred.

#1 : 1

Time overflow has occurred and time counter is read as zero.

End of enumeration elements list.

TAF : Time Alarm Flag
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Time alarm has not occurred.

#1 : 1

Time alarm has occurred.

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-only

TCE : Time Counter Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Time counter is disabled.

#1 : 1

Time counter is enabled.

End of enumeration elements list.

RESERVED : no description available
bits : 5 - 31 (27 bit)
access : read-only


LR

RTC Lock Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LR LR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED TCL CRL SRL LRL RESERVED RESERVED

RESERVED : no description available
bits : 0 - 2 (3 bit)
access : read-only

TCL : Time Compensation Lock
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Time Compensation Register is locked and writes are ignored.

#1 : 1

Time Compensation Register is not locked and writes complete as normal.

End of enumeration elements list.

CRL : Control Register Lock
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Control Register is locked and writes are ignored.

#1 : 1

Control Register is not locked and writes complete as normal.

End of enumeration elements list.

SRL : Status Register Lock
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Status Register is locked and writes are ignored.

#1 : 1

Status Register is not locked and writes complete as normal.

End of enumeration elements list.

LRL : Lock Register Lock
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Lock Register is locked and writes are ignored.

#1 : 1

Lock Register is not locked and writes complete as normal.

End of enumeration elements list.

RESERVED : no description available
bits : 7 - 7 (1 bit)
access : read-only

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only


IER

RTC Interrupt Enable Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIIE TOIE TAIE RESERVED TSIE RESERVED WPON RESERVED

TIIE : Time Invalid Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Time invalid flag does not generate an interrupt.

#1 : 1

Time invalid flag does generate an interrupt.

End of enumeration elements list.

TOIE : Time Overflow Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Time overflow flag does not generate an interrupt.

#1 : 1

Time overflow flag does generate an interrupt.

End of enumeration elements list.

TAIE : Time Alarm Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Time alarm flag does not generate an interrupt.

#1 : 1

Time alarm flag does generate an interrupt.

End of enumeration elements list.

RESERVED : no description available
bits : 3 - 3 (1 bit)
access : read-write

TSIE : Time Seconds Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Seconds interrupt is disabled.

#1 : 1

Seconds interrupt is enabled.

End of enumeration elements list.

RESERVED : no description available
bits : 5 - 6 (2 bit)
access : read-write

WPON : Wakeup Pin On
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect.

#1 : 1

If the wakeup pin is enabled, then the wakeup pin will assert.

End of enumeration elements list.

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only


TPR

RTC Time Prescaler Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPR TPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPR RESERVED

TPR : Time Prescaler Register
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only


TAR

RTC Time Alarm Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TAR TAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAR

TAR : Time Alarm Register
bits : 0 - 31 (32 bit)
access : read-write


TCR

RTC Time Compensation Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCR CIR TCV CIC

TCR : Time Compensation Register
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

#10000000 : 10000000

Time Prescaler Register overflows every 32896 clock cycles.

#11111111 : 11111111

Time Prescaler Register overflows every 32769 clock cycles.

#0 : 0

Time Prescaler Register overflows every 32768 clock cycles.

#1 : 1

Time Prescaler Register overflows every 32767 clock cycles.

#1111111 : 1111111

Time Prescaler Register overflows every 32641 clock cycles.

End of enumeration elements list.

CIR : Compensation Interval Register
bits : 8 - 15 (8 bit)
access : read-write

TCV : Time Compensation Value
bits : 16 - 23 (8 bit)
access : read-only

CIC : Compensation Interval Counter
bits : 24 - 31 (8 bit)
access : read-only



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