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FLEXIO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x510 byte (0x0)
mem_usage : registers
protection : not protected

Registers

VERID

SHIFTSTAT

SHIFTCTL0

TIMCTL2

SHIFTBUFBBS3

TIMCFG2

SHIFTERR

TIMCMP2

TIMCTL3

TIMCFG3

TIMSTAT

SHIFTCTL1

TIMCMP3

SHIFTSIEN

SHIFTCFG0

SHIFTCTL2

SHIFTEIEN

TIMIEN

SHIFTCTL3

SHIFTSDEN

SHIFTCFG1

PARAM

SHIFTBUF0

SHIFTCFG2

SHIFTBUFBIS0

SHIFTCFG3

SHIFTBUFBYS0

SHIFTBUF1

SHIFTBUFBBS0

SHIFTBUFBIS1

CTRL

TIMCTL0

SHIFTBUF2

TIMCFG0

SHIFTBUFBYS1

TIMCMP0

SHIFTBUFBIS2

SHIFTBUF3

SHIFTBUFBBS1

TIMCTL1

SHIFTBUFBYS2

SHIFTBUFBIS3

TIMCFG1

SHIFTBUFBBS2

TIMCMP1

SHIFTBUFBYS3


VERID

Version ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERID VERID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FEATURE MINOR MAJOR

FEATURE : Feature Specification Number
bits : 0 - 15 (16 bit)
access : read-only

Enumeration:

#0 : 0

Standard features implemented.

#1 : 1

Supports state, logic and parallel modes.

End of enumeration elements list.

MINOR : Minor Version Number
bits : 16 - 23 (8 bit)
access : read-only

MAJOR : Major Version Number
bits : 24 - 31 (8 bit)
access : read-only


SHIFTSTAT

Shifter Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTSTAT SHIFTSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSF

SSF : Shifter Status Flag
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0

Status flag is clear

#0001 : 1

Status flag is set

End of enumeration elements list.


SHIFTCTL0

Shifter Control N Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTCTL0 SHIFTCTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMOD PINPOL PINSEL PINCFG TIMPOL TIMSEL

SMOD : Shifter Mode
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

Disabled.

#001 : 001

Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.

#010 : 010

Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.

#100 : 100

Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.

#101 : 101

Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.

End of enumeration elements list.

PINPOL : Shifter Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin is active high

#1 : 1

Pin is active low

End of enumeration elements list.

PINSEL : Shifter Pin Select
bits : 8 - 10 (3 bit)
access : read-write

PINCFG : Shifter Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 00

Shifter pin output disabled

#01 : 01

Shifter pin open drain or bidirectional output enable

#10 : 10

Shifter pin bidirectional output data

#11 : 11

Shifter pin output

End of enumeration elements list.

TIMPOL : Timer Polarity
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Shift on posedge of Shift clock

#1 : 1

Shift on negedge of Shift clock

End of enumeration elements list.

TIMSEL : Timer Select
bits : 24 - 25 (2 bit)
access : read-write


TIMCTL2

Timer Control N Register
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMCTL2 TIMCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMOD PINPOL PINSEL PINCFG TRGSRC TRGPOL TRGSEL

TIMOD : Timer Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

Timer Disabled.

#01 : 01

Dual 8-bit counters baud/bit mode.

#10 : 10

Dual 8-bit counters PWM mode.

#11 : 11

Single 16-bit counter mode.

End of enumeration elements list.

PINPOL : Timer Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin is active high

#1 : 1

Pin is active low

End of enumeration elements list.

PINSEL : Timer Pin Select
bits : 8 - 10 (3 bit)
access : read-write

PINCFG : Timer Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 00

Timer pin output disabled

#01 : 01

Timer pin open drain or bidirectional output enable

#10 : 10

Timer pin bidirectional output data

#11 : 11

Timer pin output

End of enumeration elements list.

TRGSRC : Trigger Source
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

External trigger selected

#1 : 1

Internal trigger selected

End of enumeration elements list.

TRGPOL : Trigger Polarity
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Trigger active high

#1 : 1

Trigger active low

End of enumeration elements list.

TRGSEL : Trigger Select
bits : 24 - 27 (4 bit)
access : read-write


SHIFTBUFBBS3

Shifter Buffer N Bit Byte Swapped Register
address_offset : 0x1198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTBUFBBS3 SHIFTBUFBBS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHIFTBUFBBS

SHIFTBUFBBS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write


TIMCFG2

Timer Configuration N Register
address_offset : 0x120C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMCFG2 TIMCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSTART TSTOP TIMENA TIMDIS TIMRST TIMDEC TIMOUT

TSTART : Timer Start Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Start bit disabled

#1 : 1

Start bit enabled

End of enumeration elements list.

TSTOP : Timer Stop Bit
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 00

Stop bit disabled

#01 : 01

Stop bit is enabled on timer compare

#10 : 10

Stop bit is enabled on timer disable

#11 : 11

Stop bit is enabled on timer compare and timer disable

End of enumeration elements list.

TIMENA : Timer Enable
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Timer always enabled

#001 : 001

Timer enabled on Timer N-1 enable

#010 : 010

Timer enabled on Trigger high

#011 : 011

Timer enabled on Trigger high and Pin high

#100 : 100

Timer enabled on Pin rising edge

#101 : 101

Timer enabled on Pin rising edge and Trigger high

#110 : 110

Timer enabled on Trigger rising edge

#111 : 111

Timer enabled on Trigger rising or falling edge

End of enumeration elements list.

TIMDIS : Timer Disable
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 000

Timer never disabled

#001 : 001

Timer disabled on Timer N-1 disable

#010 : 010

Timer disabled on Timer compare

#011 : 011

Timer disabled on Timer compare and Trigger Low

#100 : 100

Timer disabled on Pin rising or falling edge

#101 : 101

Timer disabled on Pin rising or falling edge provided Trigger is high

#110 : 110

Timer disabled on Trigger falling edge

End of enumeration elements list.

TIMRST : Timer Reset
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 000

Timer never reset

#010 : 010

Timer reset on Timer Pin equal to Timer Output

#011 : 011

Timer reset on Timer Trigger equal to Timer Output

#100 : 100

Timer reset on Timer Pin rising edge

#110 : 110

Timer reset on Trigger rising edge

#111 : 111

Timer reset on Trigger rising or falling edge

End of enumeration elements list.

TIMDEC : Timer Decrement
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 00

Decrement counter on FlexIO clock, Shift clock equals Timer output.

#01 : 01

Decrement counter on Trigger input (both edges), Shift clock equals Timer output.

#10 : 10

Decrement counter on Pin input (both edges), Shift clock equals Pin input.

#11 : 11

Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.

End of enumeration elements list.

TIMOUT : Timer Output
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 00

Timer output is logic one when enabled and is not affected by timer reset

#01 : 01

Timer output is logic zero when enabled and is not affected by timer reset

#10 : 10

Timer output is logic one when enabled and on timer reset

#11 : 11

Timer output is logic zero when enabled and on timer reset

End of enumeration elements list.


SHIFTERR

Shifter Error Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTERR SHIFTERR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEF

SEF : Shifter Error Flags
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0

Shifter Error Flag is clear

#0001 : 1

Shifter Error Flag is set

End of enumeration elements list.


TIMCMP2

Timer Compare N Register
address_offset : 0x140C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMCMP2 TIMCMP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP

CMP : Timer Compare Value
bits : 0 - 15 (16 bit)
access : read-write


TIMCTL3

Timer Control N Register
address_offset : 0x1418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMCTL3 TIMCTL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMOD PINPOL PINSEL PINCFG TRGSRC TRGPOL TRGSEL

TIMOD : Timer Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

Timer Disabled.

#01 : 01

Dual 8-bit counters baud/bit mode.

#10 : 10

Dual 8-bit counters PWM mode.

#11 : 11

Single 16-bit counter mode.

End of enumeration elements list.

PINPOL : Timer Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin is active high

#1 : 1

Pin is active low

End of enumeration elements list.

PINSEL : Timer Pin Select
bits : 8 - 10 (3 bit)
access : read-write

PINCFG : Timer Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 00

Timer pin output disabled

#01 : 01

Timer pin open drain or bidirectional output enable

#10 : 10

Timer pin bidirectional output data

#11 : 11

Timer pin output

End of enumeration elements list.

TRGSRC : Trigger Source
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

External trigger selected

#1 : 1

Internal trigger selected

End of enumeration elements list.

TRGPOL : Trigger Polarity
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Trigger active high

#1 : 1

Trigger active low

End of enumeration elements list.

TRGSEL : Trigger Select
bits : 24 - 27 (4 bit)
access : read-write


TIMCFG3

Timer Configuration N Register
address_offset : 0x1698 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMCFG3 TIMCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSTART TSTOP TIMENA TIMDIS TIMRST TIMDEC TIMOUT

TSTART : Timer Start Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Start bit disabled

#1 : 1

Start bit enabled

End of enumeration elements list.

TSTOP : Timer Stop Bit
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 00

Stop bit disabled

#01 : 01

Stop bit is enabled on timer compare

#10 : 10

Stop bit is enabled on timer disable

#11 : 11

Stop bit is enabled on timer compare and timer disable

End of enumeration elements list.

TIMENA : Timer Enable
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Timer always enabled

#001 : 001

Timer enabled on Timer N-1 enable

#010 : 010

Timer enabled on Trigger high

#011 : 011

Timer enabled on Trigger high and Pin high

#100 : 100

Timer enabled on Pin rising edge

#101 : 101

Timer enabled on Pin rising edge and Trigger high

#110 : 110

Timer enabled on Trigger rising edge

#111 : 111

Timer enabled on Trigger rising or falling edge

End of enumeration elements list.

TIMDIS : Timer Disable
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 000

Timer never disabled

#001 : 001

Timer disabled on Timer N-1 disable

#010 : 010

Timer disabled on Timer compare

#011 : 011

Timer disabled on Timer compare and Trigger Low

#100 : 100

Timer disabled on Pin rising or falling edge

#101 : 101

Timer disabled on Pin rising or falling edge provided Trigger is high

#110 : 110

Timer disabled on Trigger falling edge

End of enumeration elements list.

TIMRST : Timer Reset
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 000

Timer never reset

#010 : 010

Timer reset on Timer Pin equal to Timer Output

#011 : 011

Timer reset on Timer Trigger equal to Timer Output

#100 : 100

Timer reset on Timer Pin rising edge

#110 : 110

Timer reset on Trigger rising edge

#111 : 111

Timer reset on Trigger rising or falling edge

End of enumeration elements list.

TIMDEC : Timer Decrement
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 00

Decrement counter on FlexIO clock, Shift clock equals Timer output.

#01 : 01

Decrement counter on Trigger input (both edges), Shift clock equals Timer output.

#10 : 10

Decrement counter on Pin input (both edges), Shift clock equals Pin input.

#11 : 11

Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.

End of enumeration elements list.

TIMOUT : Timer Output
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 00

Timer output is logic one when enabled and is not affected by timer reset

#01 : 01

Timer output is logic zero when enabled and is not affected by timer reset

#10 : 10

Timer output is logic one when enabled and on timer reset

#11 : 11

Timer output is logic zero when enabled and on timer reset

End of enumeration elements list.


TIMSTAT

Timer Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMSTAT TIMSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSF

TSF : Timer Status Flags
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0

Timer Status Flag is clear

#0001 : 1

Timer Status Flag is set

End of enumeration elements list.


SHIFTCTL1

Shifter Control N Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTCTL1 SHIFTCTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMOD PINPOL PINSEL PINCFG TIMPOL TIMSEL

SMOD : Shifter Mode
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

Disabled.

#001 : 001

Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.

#010 : 010

Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.

#100 : 100

Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.

#101 : 101

Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.

End of enumeration elements list.

PINPOL : Shifter Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin is active high

#1 : 1

Pin is active low

End of enumeration elements list.

PINSEL : Shifter Pin Select
bits : 8 - 10 (3 bit)
access : read-write

PINCFG : Shifter Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 00

Shifter pin output disabled

#01 : 01

Shifter pin open drain or bidirectional output enable

#10 : 10

Shifter pin bidirectional output data

#11 : 11

Shifter pin output

End of enumeration elements list.

TIMPOL : Timer Polarity
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Shift on posedge of Shift clock

#1 : 1

Shift on negedge of Shift clock

End of enumeration elements list.

TIMSEL : Timer Select
bits : 24 - 25 (2 bit)
access : read-write


TIMCMP3

Timer Compare N Register
address_offset : 0x1918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMCMP3 TIMCMP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP

CMP : Timer Compare Value
bits : 0 - 15 (16 bit)
access : read-write


SHIFTSIEN

Shifter Status Interrupt Enable
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTSIEN SHIFTSIEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSIE

SSIE : Shifter Status Interrupt Enable
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0

Shifter Status Flag interrupt disabled

#0001 : 1

Shifter Status Flag interrupt enabled

End of enumeration elements list.


SHIFTCFG0

Shifter Configuration N Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTCFG0 SHIFTCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSTART SSTOP INSRC

SSTART : Shifter Start bit
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable

#01 : 01

Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift

#10 : 10

Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0

#11 : 11

Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1

End of enumeration elements list.

SSTOP : Shifter Stop bit
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 00

Stop bit disabled for transmitter/receiver/match store

#01 : 01

Reserved for transmitter/receiver/match store

#10 : 10

Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0

#11 : 11

Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1

End of enumeration elements list.

INSRC : Input Source
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin

#1 : 1

Shifter N+1 Output

End of enumeration elements list.


SHIFTCTL2

Shifter Control N Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTCTL2 SHIFTCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMOD PINPOL PINSEL PINCFG TIMPOL TIMSEL

SMOD : Shifter Mode
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

Disabled.

#001 : 001

Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.

#010 : 010

Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.

#100 : 100

Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.

#101 : 101

Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.

End of enumeration elements list.

PINPOL : Shifter Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin is active high

#1 : 1

Pin is active low

End of enumeration elements list.

PINSEL : Shifter Pin Select
bits : 8 - 10 (3 bit)
access : read-write

PINCFG : Shifter Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 00

Shifter pin output disabled

#01 : 01

Shifter pin open drain or bidirectional output enable

#10 : 10

Shifter pin bidirectional output data

#11 : 11

Shifter pin output

End of enumeration elements list.

TIMPOL : Timer Polarity
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Shift on posedge of Shift clock

#1 : 1

Shift on negedge of Shift clock

End of enumeration elements list.

TIMSEL : Timer Select
bits : 24 - 25 (2 bit)
access : read-write


SHIFTEIEN

Shifter Error Interrupt Enable
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTEIEN SHIFTEIEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEIE

SEIE : Shifter Error Interrupt Enable
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0

Shifter Error Flag interrupt disabled

#0001 : 1

Shifter Error Flag interrupt enabled

End of enumeration elements list.


TIMIEN

Timer Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMIEN TIMIEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEIE

TEIE : Timer Status Interrupt Enable
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0

Timer Status Flag interrupt is disabled

#0001 : 1

Timer Status Flag interrupt is enabled

End of enumeration elements list.


SHIFTCTL3

Shifter Control N Register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTCTL3 SHIFTCTL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMOD PINPOL PINSEL PINCFG TIMPOL TIMSEL

SMOD : Shifter Mode
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

Disabled.

#001 : 001

Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.

#010 : 010

Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.

#100 : 100

Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.

#101 : 101

Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.

End of enumeration elements list.

PINPOL : Shifter Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin is active high

#1 : 1

Pin is active low

End of enumeration elements list.

PINSEL : Shifter Pin Select
bits : 8 - 10 (3 bit)
access : read-write

PINCFG : Shifter Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 00

Shifter pin output disabled

#01 : 01

Shifter pin open drain or bidirectional output enable

#10 : 10

Shifter pin bidirectional output data

#11 : 11

Shifter pin output

End of enumeration elements list.

TIMPOL : Timer Polarity
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Shift on posedge of Shift clock

#1 : 1

Shift on negedge of Shift clock

End of enumeration elements list.

TIMSEL : Timer Select
bits : 24 - 25 (2 bit)
access : read-write


SHIFTSDEN

Shifter Status DMA Enable
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTSDEN SHIFTSDEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSDE

SSDE : Shifter Status DMA Enable
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0

Shifter Status Flag DMA request is disabled

#0001 : 1

Shifter Status Flag DMA request is enabled

End of enumeration elements list.


SHIFTCFG1

Shifter Configuration N Register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTCFG1 SHIFTCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSTART SSTOP INSRC

SSTART : Shifter Start bit
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable

#01 : 01

Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift

#10 : 10

Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0

#11 : 11

Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1

End of enumeration elements list.

SSTOP : Shifter Stop bit
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 00

Stop bit disabled for transmitter/receiver/match store

#01 : 01

Reserved for transmitter/receiver/match store

#10 : 10

Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0

#11 : 11

Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1

End of enumeration elements list.

INSRC : Input Source
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin

#1 : 1

Shifter N+1 Output

End of enumeration elements list.


PARAM

Parameter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PARAM PARAM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHIFTER TIMER PIN TRIGGER

SHIFTER : Shifter Number
bits : 0 - 7 (8 bit)
access : read-only

TIMER : Timer Number
bits : 8 - 15 (8 bit)
access : read-only

PIN : Pin Number
bits : 16 - 23 (8 bit)
access : read-only

TRIGGER : Trigger Number
bits : 24 - 31 (8 bit)
access : read-only


SHIFTBUF0

Shifter Buffer N Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTBUF0 SHIFTBUF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHIFTBUF

SHIFTBUF : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write


SHIFTCFG2

Shifter Configuration N Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTCFG2 SHIFTCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSTART SSTOP INSRC

SSTART : Shifter Start bit
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable

#01 : 01

Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift

#10 : 10

Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0

#11 : 11

Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1

End of enumeration elements list.

SSTOP : Shifter Stop bit
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 00

Stop bit disabled for transmitter/receiver/match store

#01 : 01

Reserved for transmitter/receiver/match store

#10 : 10

Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0

#11 : 11

Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1

End of enumeration elements list.

INSRC : Input Source
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin

#1 : 1

Shifter N+1 Output

End of enumeration elements list.


SHIFTBUFBIS0

Shifter Buffer N Bit Swapped Register
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTBUFBIS0 SHIFTBUFBIS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHIFTBUFBIS

SHIFTBUFBIS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write


SHIFTCFG3

Shifter Configuration N Register
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTCFG3 SHIFTCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSTART SSTOP INSRC

SSTART : Shifter Start bit
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable

#01 : 01

Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift

#10 : 10

Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0

#11 : 11

Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1

End of enumeration elements list.

SSTOP : Shifter Stop bit
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 00

Stop bit disabled for transmitter/receiver/match store

#01 : 01

Reserved for transmitter/receiver/match store

#10 : 10

Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0

#11 : 11

Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1

End of enumeration elements list.

INSRC : Input Source
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin

#1 : 1

Shifter N+1 Output

End of enumeration elements list.


SHIFTBUFBYS0

Shifter Buffer N Byte Swapped Register
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTBUFBYS0 SHIFTBUFBYS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHIFTBUFBYS

SHIFTBUFBYS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write


SHIFTBUF1

Shifter Buffer N Register
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTBUF1 SHIFTBUF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHIFTBUF

SHIFTBUF : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write


SHIFTBUFBBS0

Shifter Buffer N Bit Byte Swapped Register
address_offset : 0x700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTBUFBBS0 SHIFTBUFBBS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHIFTBUFBBS

SHIFTBUFBBS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write


SHIFTBUFBIS1

Shifter Buffer N Bit Swapped Register
address_offset : 0x784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTBUFBIS1 SHIFTBUFBIS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHIFTBUFBIS

SHIFTBUFBIS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write


CTRL

FlexIO Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLEXEN SWRST FASTACC DBGE DOZEN

FLEXEN : FlexIO Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

FlexIO module is disabled.

#1 : 1

FlexIO module is enabled.

End of enumeration elements list.

SWRST : Software Reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Software reset is disabled

#1 : 1

Software reset is enabled, all FlexIO registers except the Control Register are reset.

End of enumeration elements list.

FASTACC : Fast Access
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configures for normal register accesses to FlexIO

#1 : 1

Configures for fast register accesses to FlexIO

End of enumeration elements list.

DBGE : Debug Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

FlexIO is disabled in debug modes.

#1 : 1

FlexIO is enabled in debug modes

End of enumeration elements list.

DOZEN : Doze Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

FlexIO enabled in Doze modes.

#1 : 1

FlexIO disabled in Doze modes.

End of enumeration elements list.


TIMCTL0

Timer Control N Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMCTL0 TIMCTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMOD PINPOL PINSEL PINCFG TRGSRC TRGPOL TRGSEL

TIMOD : Timer Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

Timer Disabled.

#01 : 01

Dual 8-bit counters baud/bit mode.

#10 : 10

Dual 8-bit counters PWM mode.

#11 : 11

Single 16-bit counter mode.

End of enumeration elements list.

PINPOL : Timer Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin is active high

#1 : 1

Pin is active low

End of enumeration elements list.

PINSEL : Timer Pin Select
bits : 8 - 10 (3 bit)
access : read-write

PINCFG : Timer Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 00

Timer pin output disabled

#01 : 01

Timer pin open drain or bidirectional output enable

#10 : 10

Timer pin bidirectional output data

#11 : 11

Timer pin output

End of enumeration elements list.

TRGSRC : Trigger Source
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

External trigger selected

#1 : 1

Internal trigger selected

End of enumeration elements list.

TRGPOL : Trigger Polarity
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Trigger active high

#1 : 1

Trigger active low

End of enumeration elements list.

TRGSEL : Trigger Select
bits : 24 - 27 (4 bit)
access : read-write


SHIFTBUF2

Shifter Buffer N Register
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTBUF2 SHIFTBUF2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHIFTBUF

SHIFTBUF : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write


TIMCFG0

Timer Configuration N Register
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMCFG0 TIMCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSTART TSTOP TIMENA TIMDIS TIMRST TIMDEC TIMOUT

TSTART : Timer Start Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Start bit disabled

#1 : 1

Start bit enabled

End of enumeration elements list.

TSTOP : Timer Stop Bit
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 00

Stop bit disabled

#01 : 01

Stop bit is enabled on timer compare

#10 : 10

Stop bit is enabled on timer disable

#11 : 11

Stop bit is enabled on timer compare and timer disable

End of enumeration elements list.

TIMENA : Timer Enable
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Timer always enabled

#001 : 001

Timer enabled on Timer N-1 enable

#010 : 010

Timer enabled on Trigger high

#011 : 011

Timer enabled on Trigger high and Pin high

#100 : 100

Timer enabled on Pin rising edge

#101 : 101

Timer enabled on Pin rising edge and Trigger high

#110 : 110

Timer enabled on Trigger rising edge

#111 : 111

Timer enabled on Trigger rising or falling edge

End of enumeration elements list.

TIMDIS : Timer Disable
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 000

Timer never disabled

#001 : 001

Timer disabled on Timer N-1 disable

#010 : 010

Timer disabled on Timer compare

#011 : 011

Timer disabled on Timer compare and Trigger Low

#100 : 100

Timer disabled on Pin rising or falling edge

#101 : 101

Timer disabled on Pin rising or falling edge provided Trigger is high

#110 : 110

Timer disabled on Trigger falling edge

End of enumeration elements list.

TIMRST : Timer Reset
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 000

Timer never reset

#010 : 010

Timer reset on Timer Pin equal to Timer Output

#011 : 011

Timer reset on Timer Trigger equal to Timer Output

#100 : 100

Timer reset on Timer Pin rising edge

#110 : 110

Timer reset on Trigger rising edge

#111 : 111

Timer reset on Trigger rising or falling edge

End of enumeration elements list.

TIMDEC : Timer Decrement
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 00

Decrement counter on FlexIO clock, Shift clock equals Timer output.

#01 : 01

Decrement counter on Trigger input (both edges), Shift clock equals Timer output.

#10 : 10

Decrement counter on Pin input (both edges), Shift clock equals Pin input.

#11 : 11

Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.

End of enumeration elements list.

TIMOUT : Timer Output
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 00

Timer output is logic one when enabled and is not affected by timer reset

#01 : 01

Timer output is logic zero when enabled and is not affected by timer reset

#10 : 10

Timer output is logic one when enabled and on timer reset

#11 : 11

Timer output is logic zero when enabled and on timer reset

End of enumeration elements list.


SHIFTBUFBYS1

Shifter Buffer N Byte Swapped Register
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTBUFBYS1 SHIFTBUFBYS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHIFTBUFBYS

SHIFTBUFBYS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write


TIMCMP0

Timer Compare N Register
address_offset : 0xA00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMCMP0 TIMCMP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP

CMP : Timer Compare Value
bits : 0 - 15 (16 bit)
access : read-write


SHIFTBUFBIS2

Shifter Buffer N Bit Swapped Register
address_offset : 0xA0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTBUFBIS2 SHIFTBUFBIS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHIFTBUFBIS

SHIFTBUFBIS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write


SHIFTBUF3

Shifter Buffer N Register
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTBUF3 SHIFTBUF3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHIFTBUF

SHIFTBUF : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write


SHIFTBUFBBS1

Shifter Buffer N Bit Byte Swapped Register
address_offset : 0xA84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTBUFBBS1 SHIFTBUFBBS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHIFTBUFBBS

SHIFTBUFBBS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write


TIMCTL1

Timer Control N Register
address_offset : 0xC04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMCTL1 TIMCTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMOD PINPOL PINSEL PINCFG TRGSRC TRGPOL TRGSEL

TIMOD : Timer Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

Timer Disabled.

#01 : 01

Dual 8-bit counters baud/bit mode.

#10 : 10

Dual 8-bit counters PWM mode.

#11 : 11

Single 16-bit counter mode.

End of enumeration elements list.

PINPOL : Timer Pin Polarity
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin is active high

#1 : 1

Pin is active low

End of enumeration elements list.

PINSEL : Timer Pin Select
bits : 8 - 10 (3 bit)
access : read-write

PINCFG : Timer Pin Configuration
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 00

Timer pin output disabled

#01 : 01

Timer pin open drain or bidirectional output enable

#10 : 10

Timer pin bidirectional output data

#11 : 11

Timer pin output

End of enumeration elements list.

TRGSRC : Trigger Source
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

External trigger selected

#1 : 1

Internal trigger selected

End of enumeration elements list.

TRGPOL : Trigger Polarity
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Trigger active high

#1 : 1

Trigger active low

End of enumeration elements list.

TRGSEL : Trigger Select
bits : 24 - 27 (4 bit)
access : read-write


SHIFTBUFBYS2

Shifter Buffer N Byte Swapped Register
address_offset : 0xC0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTBUFBYS2 SHIFTBUFBYS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHIFTBUFBYS

SHIFTBUFBYS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write


SHIFTBUFBIS3

Shifter Buffer N Bit Swapped Register
address_offset : 0xC98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTBUFBIS3 SHIFTBUFBIS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHIFTBUFBIS

SHIFTBUFBIS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write


TIMCFG1

Timer Configuration N Register
address_offset : 0xD84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMCFG1 TIMCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSTART TSTOP TIMENA TIMDIS TIMRST TIMDEC TIMOUT

TSTART : Timer Start Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Start bit disabled

#1 : 1

Start bit enabled

End of enumeration elements list.

TSTOP : Timer Stop Bit
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 00

Stop bit disabled

#01 : 01

Stop bit is enabled on timer compare

#10 : 10

Stop bit is enabled on timer disable

#11 : 11

Stop bit is enabled on timer compare and timer disable

End of enumeration elements list.

TIMENA : Timer Enable
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Timer always enabled

#001 : 001

Timer enabled on Timer N-1 enable

#010 : 010

Timer enabled on Trigger high

#011 : 011

Timer enabled on Trigger high and Pin high

#100 : 100

Timer enabled on Pin rising edge

#101 : 101

Timer enabled on Pin rising edge and Trigger high

#110 : 110

Timer enabled on Trigger rising edge

#111 : 111

Timer enabled on Trigger rising or falling edge

End of enumeration elements list.

TIMDIS : Timer Disable
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 000

Timer never disabled

#001 : 001

Timer disabled on Timer N-1 disable

#010 : 010

Timer disabled on Timer compare

#011 : 011

Timer disabled on Timer compare and Trigger Low

#100 : 100

Timer disabled on Pin rising or falling edge

#101 : 101

Timer disabled on Pin rising or falling edge provided Trigger is high

#110 : 110

Timer disabled on Trigger falling edge

End of enumeration elements list.

TIMRST : Timer Reset
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 000

Timer never reset

#010 : 010

Timer reset on Timer Pin equal to Timer Output

#011 : 011

Timer reset on Timer Trigger equal to Timer Output

#100 : 100

Timer reset on Timer Pin rising edge

#110 : 110

Timer reset on Trigger rising edge

#111 : 111

Timer reset on Trigger rising or falling edge

End of enumeration elements list.

TIMDEC : Timer Decrement
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 00

Decrement counter on FlexIO clock, Shift clock equals Timer output.

#01 : 01

Decrement counter on Trigger input (both edges), Shift clock equals Timer output.

#10 : 10

Decrement counter on Pin input (both edges), Shift clock equals Pin input.

#11 : 11

Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.

End of enumeration elements list.

TIMOUT : Timer Output
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 00

Timer output is logic one when enabled and is not affected by timer reset

#01 : 01

Timer output is logic zero when enabled and is not affected by timer reset

#10 : 10

Timer output is logic one when enabled and on timer reset

#11 : 11

Timer output is logic zero when enabled and on timer reset

End of enumeration elements list.


SHIFTBUFBBS2

Shifter Buffer N Bit Byte Swapped Register
address_offset : 0xE0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTBUFBBS2 SHIFTBUFBBS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHIFTBUFBBS

SHIFTBUFBBS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write


TIMCMP1

Timer Compare N Register
address_offset : 0xF04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMCMP1 TIMCMP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMP

CMP : Timer Compare Value
bits : 0 - 15 (16 bit)
access : read-write


SHIFTBUFBYS3

Shifter Buffer N Byte Swapped Register
address_offset : 0xF18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFTBUFBYS3 SHIFTBUFBYS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHIFTBUFBYS

SHIFTBUFBYS : Shift Buffer
bits : 0 - 31 (32 bit)
access : read-write



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