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TPM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x88 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SC

C0SC

C0V

C1SC

C1V

CNT

STATUS

MOD

CONF


SC

Status and Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC SC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS CMOD CPWMS TOIE TOF DMA RESERVED

PS : Prescale Factor Selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

Divide by 1

#001 : 001

Divide by 2

#010 : 010

Divide by 4

#011 : 011

Divide by 8

#100 : 100

Divide by 16

#101 : 101

Divide by 32

#110 : 110

Divide by 64

#111 : 111

Divide by 128

End of enumeration elements list.

CMOD : Clock Mode Selection
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

#00 : 00

LPTPM counter is disabled

#01 : 01

LPTPM counter increments on every LPTPM counter clock

#10 : 10

LPTPM counter increments on rising edge of LPTPM_EXTCLK synchronized to the LPTPM counter clock

#11 : 11

Reserved

End of enumeration elements list.

CPWMS : Center-aligned PWM Select
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

LPTPM counter operates in up counting mode.

#1 : 1

LPTPM counter operates in up-down counting mode.

End of enumeration elements list.

TOIE : Timer Overflow Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable TOF interrupts. Use software polling or DMA request.

#1 : 1

Enable TOF interrupts. An interrupt is generated when TOF equals one.

End of enumeration elements list.

TOF : Timer Overflow Flag
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

LPTPM counter has not overflowed.

#1 : 1

LPTPM counter has overflowed.

End of enumeration elements list.

DMA : DMA Enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disables DMA transfers.

#1 : 1

Enables DMA transfers.

End of enumeration elements list.

RESERVED : no description available
bits : 9 - 31 (23 bit)
access : read-only


C0SC

Channel (n) Status and Control
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C0SC C0SC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA RESERVED ELSA ELSB MSA MSB CHIE CHF RESERVED

DMA : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable DMA transfers.

#1 : 1

Enable DMA transfers.

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 1 (1 bit)
access : read-only

ELSA : Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write

ELSB : Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write

MSA : Channel Mode Select
bits : 4 - 4 (1 bit)
access : read-write

MSB : Channel Mode Select
bits : 5 - 5 (1 bit)
access : read-write

CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable channel interrupts.

#1 : 1

Enable channel interrupts.

End of enumeration elements list.

CHF : Channel Flag
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

No channel event has occurred.

#1 : 1

A channel event has occurred.

End of enumeration elements list.

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only


C0V

Channel (n) Value
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C0V C0V read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL RESERVED

VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only


C1SC

Channel (n) Status and Control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1SC C1SC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA RESERVED ELSA ELSB MSA MSB CHIE CHF RESERVED

DMA : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable DMA transfers.

#1 : 1

Enable DMA transfers.

End of enumeration elements list.

RESERVED : no description available
bits : 1 - 1 (1 bit)
access : read-only

ELSA : Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write

ELSB : Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write

MSA : Channel Mode Select
bits : 4 - 4 (1 bit)
access : read-write

MSB : Channel Mode Select
bits : 5 - 5 (1 bit)
access : read-write

CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable channel interrupts.

#1 : 1

Enable channel interrupts.

End of enumeration elements list.

CHF : Channel Flag
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

No channel event has occurred.

#1 : 1

A channel event has occurred.

End of enumeration elements list.

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only


C1V

Channel (n) Value
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1V C1V read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL RESERVED

VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only


CNT

Counter
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT RESERVED

COUNT : Counter value
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only


STATUS

Capture and Compare Status
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0F CH1F CH2F CH3F CH4F CH5F RESERVED TOF RESERVED

CH0F : Channel 0 Flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No channel event has occurred.

#1 : 1

A channel event has occurred.

End of enumeration elements list.

CH1F : Channel 1 Flag
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No channel event has occurred.

#1 : 1

A channel event has occurred.

End of enumeration elements list.

CH2F : Channel 2 Flag
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No channel event has occurred.

#1 : 1

A channel event has occurred.

End of enumeration elements list.

CH3F : Channel 3 Flag
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No channel event has occurred.

#1 : 1

A channel event has occurred.

End of enumeration elements list.

CH4F : Channel 4 Flag
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No channel event has occurred.

#1 : 1

A channel event has occurred.

End of enumeration elements list.

CH5F : Channel 5 Flag
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No channel event has occurred.

#1 : 1

A channel event has occurred.

End of enumeration elements list.

RESERVED : no description available
bits : 6 - 7 (2 bit)
access : read-only

TOF : Timer Overflow Flag
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

LPTPM counter has not overflowed.

#1 : 1

LPTPM counter has overflowed.

End of enumeration elements list.

RESERVED : no description available
bits : 9 - 31 (23 bit)
access : read-only


MOD

Modulo
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOD MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOD RESERVED

MOD : Modulo value
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only


CONF

Configuration
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONF CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED DOZEEN DBGMODE RESERVED GTBEEN RESERVED CSOT CSOO CROT RESERVED TRGSEL RESERVED

RESERVED : no description available
bits : 0 - 4 (5 bit)
access : read-only

DOZEEN : Doze Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal LPTPM counter continues in Doze mode.

#1 : 1

Internal LPTPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.

End of enumeration elements list.

DBGMODE : Debug Mode
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 00

LPTPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored.

#11 : 11

LPTPM counter continues in debug mode.

End of enumeration elements list.

RESERVED : no description available
bits : 8 - 8 (1 bit)
access : read-only

GTBEEN : Global time base enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

All channels use the internally generated LPTPM counter as their timebase

#1 : 1

All channels use an externally generated global timebase as their timebase

End of enumeration elements list.

RESERVED : no description available
bits : 10 - 15 (6 bit)
access : read-only

CSOT : Counter Start on Trigger
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

LPTPM counter starts to increment immediately, once it is enabled.

#1 : 1

LPTPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.

End of enumeration elements list.

CSOO : Counter Stop On Overflow
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

LPTPM counter continues incrementing or decrementing after overflow

#1 : 1

LPTPM counter stops incrementing or decrementing after overflow.

End of enumeration elements list.

CROT : Counter Reload On Trigger
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Counter is not reloaded due to a rising edge on the selected input trigger

#1 : 1

Counter is reloaded when a rising edge is detected on the selected input trigger

End of enumeration elements list.

RESERVED : no description available
bits : 19 - 23 (5 bit)
access : read-only

TRGSEL : Trigger Select
bits : 24 - 27 (4 bit)
access : read-write

RESERVED : no description available
bits : 28 - 31 (4 bit)
access : read-only



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