Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x100 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected
Source Address Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
Destination Address Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
DMA Status Register / Byte Count Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCR : BCR
bits : 0 - 23 (24 bit)
access : read-write
DONE : Transactions Done
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA transfer is not yet complete. Writing a 0 has no effect.
#1 : 1
DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.
End of enumeration elements list.
BSY : Busy
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
DMA channel is inactive. Cleared when the DMA has finished the last transaction.
#1 : 1
BSY is set the first time the channel is enabled after a transfer is initiated.
End of enumeration elements list.
REQ : Request
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
No request is pending or the channel is currently active. Cleared when the channel is selected.
#1 : 1
The DMA channel has a transfer remaining and the channel is not selected.
End of enumeration elements list.
BED : Bus Error on Destination
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
#0 : 0
No bus error occurred.
#1 : 1
The DMA channel terminated with a bus error during the write portion of a transfer.
End of enumeration elements list.
BES : Bus Error on Source
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
No bus error occurred.
#1 : 1
The DMA channel terminated with a bus error during the read portion of a transfer.
End of enumeration elements list.
CE : Configuration Error
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
#0 : 0
No configuration error exists.
#1 : 1
A configuration error has occurred.
End of enumeration elements list.
DMA_DSR0 register.
address_offset : 0x10B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Control Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCH2 : Link Channel 2
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
DMA Channel 0
#01 : 01
DMA Channel 1
#10 : 10
DMA Channel 2
#11 : 11
DMA Channel 3
End of enumeration elements list.
LCH1 : Link Channel 1
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
DMA Channel 0
#01 : 01
DMA Channel 1
#10 : 10
DMA Channel 2
#11 : 11
DMA Channel 3
End of enumeration elements list.
LINKCC : Link Channel Control
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
No channel-to-channel linking
#01 : 01
Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.
#10 : 10
Perform a link to channel LCH1 after each cycle-steal transfer
#11 : 11
Perform a link to channel LCH1 after the BCR decrements to 0.
End of enumeration elements list.
D_REQ : Disable Request
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
ERQ bit is not affected.
#1 : 1
ERQ bit is cleared when the BCR is exhausted.
End of enumeration elements list.
DMOD : Destination Address Modulo
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Buffer disabled
#0001 : 0001
Circular buffer size is 16 bytes
#0010 : 0010
Circular buffer size is 32 bytes
#0011 : 0011
Circular buffer size is 64 bytes
#0100 : 0100
Circular buffer size is 128 bytes
#0101 : 0101
Circular buffer size is 256 bytes
#0110 : 0110
Circular buffer size is 512 bytes
#0111 : 0111
Circular buffer size is 1 KB
#1000 : 1000
Circular buffer size is 2 KB
#1001 : 1001
Circular buffer size is 4 KB
#1010 : 1010
Circular buffer size is 8 KB
#1011 : 1011
Circular buffer size is 16 KB
#1100 : 1100
Circular buffer size is 32 KB
#1101 : 1101
Circular buffer size is 64 KB
#1110 : 1110
Circular buffer size is 128 KB
#1111 : 1111
Circular buffer size is 256 KB
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Buffer disabled
#0001 : 0001
Circular buffer size is 16 bytes.
#0010 : 0010
Circular buffer size is 32 bytes.
#0011 : 0011
Circular buffer size is 64 bytes.
#0100 : 0100
Circular buffer size is 128 bytes.
#0101 : 0101
Circular buffer size is 256 bytes.
#0110 : 0110
Circular buffer size is 512 bytes.
#0111 : 0111
Circular buffer size is 1 KB.
#1000 : 1000
Circular buffer size is 2 KB.
#1001 : 1001
Circular buffer size is 4 KB.
#1010 : 1010
Circular buffer size is 8 KB.
#1011 : 1011
Circular buffer size is 16 KB.
#1100 : 1100
Circular buffer size is 32 KB.
#1101 : 1101
Circular buffer size is 64 KB.
#1110 : 1110
Circular buffer size is 128 KB.
#1111 : 1111
Circular buffer size is 256 KB.
End of enumeration elements list.
START : Start Transfer
bits : 16 - 16 (1 bit)
access : write-only
Enumeration:
#0 : 0
DMA inactive
#1 : 1
The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
End of enumeration elements list.
DSIZE : Destination Size
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
#00 : 00
32-bit
#01 : 01
8-bit
#10 : 10
16-bit
#11 : 11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
End of enumeration elements list.
DINC : Destination Increment
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
No change to the DAR after a successful transfer.
#1 : 1
The DAR increments by 1, 2, 4 depending upon the size of the transfer.
End of enumeration elements list.
SSIZE : Source Size
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
32-bit
#01 : 01
8-bit
#10 : 10
16-bit
#11 : 11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
End of enumeration elements list.
SINC : Source Increment
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
No change to SAR after a successful transfer.
#1 : 1
The SAR increments by 1, 2, 4 as determined by the transfer size.
End of enumeration elements list.
EADREQ : Enable asynchronous DMA requests
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
AA : Auto-align
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-align disabled
#1 : 1
If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
End of enumeration elements list.
CS : Cycle Steal
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA continuously makes read/write transfers until the BCR decrements to 0.
#1 : 1
Forces a single read/write transfer per request.
End of enumeration elements list.
ERQ : Enable Peripheral Request
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Peripheral request is ignored.
#1 : 1
Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.
End of enumeration elements list.
EINT : Enable Interrupt on Completion of Transfer
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt is generated.
#1 : 1
Interrupt signal is enabled.
End of enumeration elements list.
Source Address Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
Destination Address Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
DMA Status Register / Byte Count Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCR : BCR
bits : 0 - 23 (24 bit)
access : read-write
DONE : Transactions Done
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA transfer is not yet complete. Writing a 0 has no effect.
#1 : 1
DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.
End of enumeration elements list.
BSY : Busy
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
DMA channel is inactive. Cleared when the DMA has finished the last transaction.
#1 : 1
BSY is set the first time the channel is enabled after a transfer is initiated.
End of enumeration elements list.
REQ : Request
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
No request is pending or the channel is currently active. Cleared when the channel is selected.
#1 : 1
The DMA channel has a transfer remaining and the channel is not selected.
End of enumeration elements list.
BED : Bus Error on Destination
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
#0 : 0
No bus error occurred.
#1 : 1
The DMA channel terminated with a bus error during the write portion of a transfer.
End of enumeration elements list.
BES : Bus Error on Source
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
No bus error occurred.
#1 : 1
The DMA channel terminated with a bus error during the read portion of a transfer.
End of enumeration elements list.
CE : Configuration Error
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
#0 : 0
No configuration error exists.
#1 : 1
A configuration error has occurred.
End of enumeration elements list.
DMA_DSR1 register.
address_offset : 0x11B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Control Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCH2 : Link Channel 2
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
DMA Channel 0
#01 : 01
DMA Channel 1
#10 : 10
DMA Channel 2
#11 : 11
DMA Channel 3
End of enumeration elements list.
LCH1 : Link Channel 1
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
DMA Channel 0
#01 : 01
DMA Channel 1
#10 : 10
DMA Channel 2
#11 : 11
DMA Channel 3
End of enumeration elements list.
LINKCC : Link Channel Control
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
No channel-to-channel linking
#01 : 01
Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.
#10 : 10
Perform a link to channel LCH1 after each cycle-steal transfer
#11 : 11
Perform a link to channel LCH1 after the BCR decrements to 0.
End of enumeration elements list.
D_REQ : Disable Request
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
ERQ bit is not affected.
#1 : 1
ERQ bit is cleared when the BCR is exhausted.
End of enumeration elements list.
DMOD : Destination Address Modulo
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Buffer disabled
#0001 : 0001
Circular buffer size is 16 bytes
#0010 : 0010
Circular buffer size is 32 bytes
#0011 : 0011
Circular buffer size is 64 bytes
#0100 : 0100
Circular buffer size is 128 bytes
#0101 : 0101
Circular buffer size is 256 bytes
#0110 : 0110
Circular buffer size is 512 bytes
#0111 : 0111
Circular buffer size is 1 KB
#1000 : 1000
Circular buffer size is 2 KB
#1001 : 1001
Circular buffer size is 4 KB
#1010 : 1010
Circular buffer size is 8 KB
#1011 : 1011
Circular buffer size is 16 KB
#1100 : 1100
Circular buffer size is 32 KB
#1101 : 1101
Circular buffer size is 64 KB
#1110 : 1110
Circular buffer size is 128 KB
#1111 : 1111
Circular buffer size is 256 KB
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Buffer disabled
#0001 : 0001
Circular buffer size is 16 bytes.
#0010 : 0010
Circular buffer size is 32 bytes.
#0011 : 0011
Circular buffer size is 64 bytes.
#0100 : 0100
Circular buffer size is 128 bytes.
#0101 : 0101
Circular buffer size is 256 bytes.
#0110 : 0110
Circular buffer size is 512 bytes.
#0111 : 0111
Circular buffer size is 1 KB.
#1000 : 1000
Circular buffer size is 2 KB.
#1001 : 1001
Circular buffer size is 4 KB.
#1010 : 1010
Circular buffer size is 8 KB.
#1011 : 1011
Circular buffer size is 16 KB.
#1100 : 1100
Circular buffer size is 32 KB.
#1101 : 1101
Circular buffer size is 64 KB.
#1110 : 1110
Circular buffer size is 128 KB.
#1111 : 1111
Circular buffer size is 256 KB.
End of enumeration elements list.
START : Start Transfer
bits : 16 - 16 (1 bit)
access : write-only
Enumeration:
#0 : 0
DMA inactive
#1 : 1
The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
End of enumeration elements list.
DSIZE : Destination Size
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
#00 : 00
32-bit
#01 : 01
8-bit
#10 : 10
16-bit
#11 : 11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
End of enumeration elements list.
DINC : Destination Increment
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
No change to the DAR after a successful transfer.
#1 : 1
The DAR increments by 1, 2, 4 depending upon the size of the transfer.
End of enumeration elements list.
SSIZE : Source Size
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
32-bit
#01 : 01
8-bit
#10 : 10
16-bit
#11 : 11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
End of enumeration elements list.
SINC : Source Increment
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
No change to SAR after a successful transfer.
#1 : 1
The SAR increments by 1, 2, 4 as determined by the transfer size.
End of enumeration elements list.
EADREQ : Enable asynchronous DMA requests
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
AA : Auto-align
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-align disabled
#1 : 1
If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
End of enumeration elements list.
CS : Cycle Steal
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA continuously makes read/write transfers until the BCR decrements to 0.
#1 : 1
Forces a single read/write transfer per request.
End of enumeration elements list.
ERQ : Enable Peripheral Request
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Peripheral request is ignored.
#1 : 1
Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.
End of enumeration elements list.
EINT : Enable Interrupt on Completion of Transfer
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt is generated.
#1 : 1
Interrupt signal is enabled.
End of enumeration elements list.
Source Address Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
Destination Address Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
DMA Status Register / Byte Count Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCR : BCR
bits : 0 - 23 (24 bit)
access : read-write
DONE : Transactions Done
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA transfer is not yet complete. Writing a 0 has no effect.
#1 : 1
DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.
End of enumeration elements list.
BSY : Busy
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
DMA channel is inactive. Cleared when the DMA has finished the last transaction.
#1 : 1
BSY is set the first time the channel is enabled after a transfer is initiated.
End of enumeration elements list.
REQ : Request
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
No request is pending or the channel is currently active. Cleared when the channel is selected.
#1 : 1
The DMA channel has a transfer remaining and the channel is not selected.
End of enumeration elements list.
BED : Bus Error on Destination
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
#0 : 0
No bus error occurred.
#1 : 1
The DMA channel terminated with a bus error during the write portion of a transfer.
End of enumeration elements list.
BES : Bus Error on Source
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
No bus error occurred.
#1 : 1
The DMA channel terminated with a bus error during the read portion of a transfer.
End of enumeration elements list.
CE : Configuration Error
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
#0 : 0
No configuration error exists.
#1 : 1
A configuration error has occurred.
End of enumeration elements list.
DMA_DSR2 register.
address_offset : 0x12B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Control Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCH2 : Link Channel 2
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
DMA Channel 0
#01 : 01
DMA Channel 1
#10 : 10
DMA Channel 2
#11 : 11
DMA Channel 3
End of enumeration elements list.
LCH1 : Link Channel 1
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
DMA Channel 0
#01 : 01
DMA Channel 1
#10 : 10
DMA Channel 2
#11 : 11
DMA Channel 3
End of enumeration elements list.
LINKCC : Link Channel Control
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
No channel-to-channel linking
#01 : 01
Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.
#10 : 10
Perform a link to channel LCH1 after each cycle-steal transfer
#11 : 11
Perform a link to channel LCH1 after the BCR decrements to 0.
End of enumeration elements list.
D_REQ : Disable Request
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
ERQ bit is not affected.
#1 : 1
ERQ bit is cleared when the BCR is exhausted.
End of enumeration elements list.
DMOD : Destination Address Modulo
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Buffer disabled
#0001 : 0001
Circular buffer size is 16 bytes
#0010 : 0010
Circular buffer size is 32 bytes
#0011 : 0011
Circular buffer size is 64 bytes
#0100 : 0100
Circular buffer size is 128 bytes
#0101 : 0101
Circular buffer size is 256 bytes
#0110 : 0110
Circular buffer size is 512 bytes
#0111 : 0111
Circular buffer size is 1 KB
#1000 : 1000
Circular buffer size is 2 KB
#1001 : 1001
Circular buffer size is 4 KB
#1010 : 1010
Circular buffer size is 8 KB
#1011 : 1011
Circular buffer size is 16 KB
#1100 : 1100
Circular buffer size is 32 KB
#1101 : 1101
Circular buffer size is 64 KB
#1110 : 1110
Circular buffer size is 128 KB
#1111 : 1111
Circular buffer size is 256 KB
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Buffer disabled
#0001 : 0001
Circular buffer size is 16 bytes.
#0010 : 0010
Circular buffer size is 32 bytes.
#0011 : 0011
Circular buffer size is 64 bytes.
#0100 : 0100
Circular buffer size is 128 bytes.
#0101 : 0101
Circular buffer size is 256 bytes.
#0110 : 0110
Circular buffer size is 512 bytes.
#0111 : 0111
Circular buffer size is 1 KB.
#1000 : 1000
Circular buffer size is 2 KB.
#1001 : 1001
Circular buffer size is 4 KB.
#1010 : 1010
Circular buffer size is 8 KB.
#1011 : 1011
Circular buffer size is 16 KB.
#1100 : 1100
Circular buffer size is 32 KB.
#1101 : 1101
Circular buffer size is 64 KB.
#1110 : 1110
Circular buffer size is 128 KB.
#1111 : 1111
Circular buffer size is 256 KB.
End of enumeration elements list.
START : Start Transfer
bits : 16 - 16 (1 bit)
access : write-only
Enumeration:
#0 : 0
DMA inactive
#1 : 1
The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
End of enumeration elements list.
DSIZE : Destination Size
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
#00 : 00
32-bit
#01 : 01
8-bit
#10 : 10
16-bit
#11 : 11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
End of enumeration elements list.
DINC : Destination Increment
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
No change to the DAR after a successful transfer.
#1 : 1
The DAR increments by 1, 2, 4 depending upon the size of the transfer.
End of enumeration elements list.
SSIZE : Source Size
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
32-bit
#01 : 01
8-bit
#10 : 10
16-bit
#11 : 11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
End of enumeration elements list.
SINC : Source Increment
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
No change to SAR after a successful transfer.
#1 : 1
The SAR increments by 1, 2, 4 as determined by the transfer size.
End of enumeration elements list.
EADREQ : Enable asynchronous DMA requests
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
AA : Auto-align
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-align disabled
#1 : 1
If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
End of enumeration elements list.
CS : Cycle Steal
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA continuously makes read/write transfers until the BCR decrements to 0.
#1 : 1
Forces a single read/write transfer per request.
End of enumeration elements list.
ERQ : Enable Peripheral Request
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Peripheral request is ignored.
#1 : 1
Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.
End of enumeration elements list.
EINT : Enable Interrupt on Completion of Transfer
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt is generated.
#1 : 1
Interrupt signal is enabled.
End of enumeration elements list.
Source Address Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR : SAR
bits : 0 - 31 (32 bit)
access : read-write
Destination Address Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAR : DAR
bits : 0 - 31 (32 bit)
access : read-write
DMA Status Register / Byte Count Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCR : BCR
bits : 0 - 23 (24 bit)
access : read-write
DONE : Transactions Done
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA transfer is not yet complete. Writing a 0 has no effect.
#1 : 1
DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.
End of enumeration elements list.
BSY : Busy
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
DMA channel is inactive. Cleared when the DMA has finished the last transaction.
#1 : 1
BSY is set the first time the channel is enabled after a transfer is initiated.
End of enumeration elements list.
REQ : Request
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
No request is pending or the channel is currently active. Cleared when the channel is selected.
#1 : 1
The DMA channel has a transfer remaining and the channel is not selected.
End of enumeration elements list.
BED : Bus Error on Destination
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
#0 : 0
No bus error occurred.
#1 : 1
The DMA channel terminated with a bus error during the write portion of a transfer.
End of enumeration elements list.
BES : Bus Error on Source
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
No bus error occurred.
#1 : 1
The DMA channel terminated with a bus error during the read portion of a transfer.
End of enumeration elements list.
CE : Configuration Error
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
#0 : 0
No configuration error exists.
#1 : 1
A configuration error has occurred.
End of enumeration elements list.
DMA_DSR3 register.
address_offset : 0x13B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Control Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCH2 : Link Channel 2
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
DMA Channel 0
#01 : 01
DMA Channel 1
#10 : 10
DMA Channel 2
#11 : 11
DMA Channel 3
End of enumeration elements list.
LCH1 : Link Channel 1
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
DMA Channel 0
#01 : 01
DMA Channel 1
#10 : 10
DMA Channel 2
#11 : 11
DMA Channel 3
End of enumeration elements list.
LINKCC : Link Channel Control
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
No channel-to-channel linking
#01 : 01
Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.
#10 : 10
Perform a link to channel LCH1 after each cycle-steal transfer
#11 : 11
Perform a link to channel LCH1 after the BCR decrements to 0.
End of enumeration elements list.
D_REQ : Disable Request
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
ERQ bit is not affected.
#1 : 1
ERQ bit is cleared when the BCR is exhausted.
End of enumeration elements list.
DMOD : Destination Address Modulo
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Buffer disabled
#0001 : 0001
Circular buffer size is 16 bytes
#0010 : 0010
Circular buffer size is 32 bytes
#0011 : 0011
Circular buffer size is 64 bytes
#0100 : 0100
Circular buffer size is 128 bytes
#0101 : 0101
Circular buffer size is 256 bytes
#0110 : 0110
Circular buffer size is 512 bytes
#0111 : 0111
Circular buffer size is 1 KB
#1000 : 1000
Circular buffer size is 2 KB
#1001 : 1001
Circular buffer size is 4 KB
#1010 : 1010
Circular buffer size is 8 KB
#1011 : 1011
Circular buffer size is 16 KB
#1100 : 1100
Circular buffer size is 32 KB
#1101 : 1101
Circular buffer size is 64 KB
#1110 : 1110
Circular buffer size is 128 KB
#1111 : 1111
Circular buffer size is 256 KB
End of enumeration elements list.
SMOD : Source Address Modulo
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Buffer disabled
#0001 : 0001
Circular buffer size is 16 bytes.
#0010 : 0010
Circular buffer size is 32 bytes.
#0011 : 0011
Circular buffer size is 64 bytes.
#0100 : 0100
Circular buffer size is 128 bytes.
#0101 : 0101
Circular buffer size is 256 bytes.
#0110 : 0110
Circular buffer size is 512 bytes.
#0111 : 0111
Circular buffer size is 1 KB.
#1000 : 1000
Circular buffer size is 2 KB.
#1001 : 1001
Circular buffer size is 4 KB.
#1010 : 1010
Circular buffer size is 8 KB.
#1011 : 1011
Circular buffer size is 16 KB.
#1100 : 1100
Circular buffer size is 32 KB.
#1101 : 1101
Circular buffer size is 64 KB.
#1110 : 1110
Circular buffer size is 128 KB.
#1111 : 1111
Circular buffer size is 256 KB.
End of enumeration elements list.
START : Start Transfer
bits : 16 - 16 (1 bit)
access : write-only
Enumeration:
#0 : 0
DMA inactive
#1 : 1
The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
End of enumeration elements list.
DSIZE : Destination Size
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
#00 : 00
32-bit
#01 : 01
8-bit
#10 : 10
16-bit
#11 : 11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
End of enumeration elements list.
DINC : Destination Increment
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
No change to the DAR after a successful transfer.
#1 : 1
The DAR increments by 1, 2, 4 depending upon the size of the transfer.
End of enumeration elements list.
SSIZE : Source Size
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
32-bit
#01 : 01
8-bit
#10 : 10
16-bit
#11 : 11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
End of enumeration elements list.
SINC : Source Increment
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
No change to SAR after a successful transfer.
#1 : 1
The SAR increments by 1, 2, 4 as determined by the transfer size.
End of enumeration elements list.
EADREQ : Enable asynchronous DMA requests
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
AA : Auto-align
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-align disabled
#1 : 1
If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
End of enumeration elements list.
CS : Cycle Steal
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA continuously makes read/write transfers until the BCR decrements to 0.
#1 : 1
Forces a single read/write transfer per request.
End of enumeration elements list.
ERQ : Enable Peripheral Request
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Peripheral request is ignored.
#1 : 1
Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.
End of enumeration elements list.
EINT : Enable Interrupt on Completion of Transfer
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt is generated.
#1 : 1
Interrupt signal is enabled.
End of enumeration elements list.
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