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ADC0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SC1A

RA

SC2

SC3

OFS

PG

CV1

RB

CLPD

CLPS

CLP4

SC1B

CLP3

CLP2

CLP1

CV2

CLP0

CFG1

CFG2


SC1A

ADC Status and Control Registers 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC1A SC1A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCH RESERVED AIEN COCO RESERVED

ADCH : Input channel select
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

#00000 : 00000

AD0 is selected as input.

#00001 : 00001

AD1 is selected as input.

#00010 : 00010

AD2 is selected as input.

#00011 : 00011

AD3 is selected as input.

#00100 : 00100

AD4 is selected as input.

#00101 : 00101

AD5 is selected as input.

#00110 : 00110

AD6 is selected as input.

#00111 : 00111

AD7 is selected as input.

#01000 : 01000

AD8 is selected as input.

#01001 : 01001

AD9 is selected as input.

#01010 : 01010

AD10 is selected as input.

#01011 : 01011

AD11 is selected as input.

#01100 : 01100

AD12 is selected as input.

#01101 : 01101

AD13 is selected as input.

#01110 : 01110

AD14 is selected as input.

#01111 : 01111

AD15 is selected as input.

#10000 : 10000

AD16 is selected as input.

#10001 : 10001

AD17 is selected as input.

#10010 : 10010

AD18 is selected as input.

#10011 : 10011

AD19 is selected as input.

#10100 : 10100

AD20 is selected as input.

#10101 : 10101

AD21 is selected as input.

#10110 : 10110

AD22 is selected as input.

#10111 : 10111

AD23 is selected as input.

#11010 : 11010

Temp Sensor (single-ended) is selected as input.

#11011 : 11011

Bandgap (single-ended) is selected as input.

#11101 : 11101

VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL].

#11110 : 11110

VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL].

#11111 : 11111

Module is disabled.

#11000 : 11000

Reserved.

#11001 : 11001

Reserved.

#11100 : 11100

Reserved.

End of enumeration elements list.

RESERVED : no description available
bits : 5 - 5 (1 bit)
access : read-only

AIEN : Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Conversion complete interrupt is disabled.

#1 : 1

Conversion complete interrupt is enabled.

End of enumeration elements list.

COCO : Conversion Complete Flag
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

Conversion is not completed.

#1 : 1

Conversion is completed.

End of enumeration elements list.

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only


RA

ADC Data Result Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RA RA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D RESERVED

D : Data result
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only


SC2

Status and Control Register 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC2 SC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REFSEL DMAEN ACREN ACFGT ACFE ADTRG ADACT RESERVED

REFSEL : Voltage Reference Selection
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

Default voltage reference pin pair, that is, external pins VREFH and VREFL

#01 : 01

Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU

#10 : 10

Reserved

#11 : 11

Reserved

End of enumeration elements list.

DMAEN : DMA Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA is disabled.

#1 : 1

DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.

End of enumeration elements list.

ACREN : Compare Function Range Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Range function disabled. Only CV1 is compared.

#1 : 1

Range function enabled. Both CV1 and CV2 are compared.

End of enumeration elements list.

ACFGT : Compare Function Greater Than Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.

#1 : 1

Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.

End of enumeration elements list.

ACFE : Compare Function Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Compare function disabled.

#1 : 1

Compare function enabled.

End of enumeration elements list.

ADTRG : Conversion Trigger Select
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Software trigger selected.

#1 : 1

Hardware trigger selected.

End of enumeration elements list.

ADACT : Conversion Active
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

Conversion not in progress.

#1 : 1

Conversion in progress.

End of enumeration elements list.

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only


SC3

Status and Control Register 3
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC3 SC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVGS AVGE ADCO RESERVED CALF CAL RESERVED

AVGS : Hardware Average Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

4 samples averaged.

#01 : 01

8 samples averaged.

#10 : 10

16 samples averaged.

#11 : 11

32 samples averaged.

End of enumeration elements list.

AVGE : Hardware Average Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Hardware average function disabled.

#1 : 1

Hardware average function enabled.

End of enumeration elements list.

ADCO : Continuous Conversion Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.

#1 : 1

Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.

End of enumeration elements list.

RESERVED : no description available
bits : 4 - 5 (2 bit)
access : read-only

CALF : Calibration Failed Flag
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Calibration completed normally.

#1 : 1

Calibration failed. ADC accuracy specifications are not guaranteed.

End of enumeration elements list.

CAL : Calibration
bits : 7 - 7 (1 bit)
access : read-write

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only


OFS

ADC Offset Correction Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFS OFS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFS RESERVED

OFS : Offset Error Correction Value
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only


PG

ADC Plus-Side Gain Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG PG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PG RESERVED

PG : Plus-Side Gain
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only


CV1

Compare Value Registers
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CV1 CV1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CV RESERVED

CV : Compare Value.
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only


RB

ADC Data Result Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RB RB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D RESERVED

D : Data result
bits : 0 - 15 (16 bit)
access : read-only

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only


CLPD

ADC Plus-Side General Calibration Value Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLPD CLPD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLPD RESERVED

CLPD : no description available
bits : 0 - 5 (6 bit)
access : read-write

RESERVED : no description available
bits : 6 - 31 (26 bit)
access : read-only


CLPS

ADC Plus-Side General Calibration Value Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLPS CLPS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLPS RESERVED

CLPS : no description available
bits : 0 - 5 (6 bit)
access : read-write

RESERVED : no description available
bits : 6 - 31 (26 bit)
access : read-only


CLP4

ADC Plus-Side General Calibration Value Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLP4 CLP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLP4 RESERVED

CLP4 : no description available
bits : 0 - 9 (10 bit)
access : read-write

RESERVED : no description available
bits : 10 - 31 (22 bit)
access : read-only


SC1B

ADC Status and Control Registers 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC1B SC1B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCH RESERVED AIEN COCO RESERVED

ADCH : Input channel select
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

#00000 : 00000

AD0 is selected as input.

#00001 : 00001

AD1 is selected as input.

#00010 : 00010

AD2 is selected as input.

#00011 : 00011

AD3 is selected as input.

#00100 : 00100

AD4 is selected as input.

#00101 : 00101

AD5 is selected as input.

#00110 : 00110

AD6 is selected as input.

#00111 : 00111

AD7 is selected as input.

#01000 : 01000

AD8 is selected as input.

#01001 : 01001

AD9 is selected as input.

#01010 : 01010

AD10 is selected as input.

#01011 : 01011

AD11 is selected as input.

#01100 : 01100

AD12 is selected as input.

#01101 : 01101

AD13 is selected as input.

#01110 : 01110

AD14 is selected as input.

#01111 : 01111

AD15 is selected as input.

#10000 : 10000

AD16 is selected as input.

#10001 : 10001

AD17 is selected as input.

#10010 : 10010

AD18 is selected as input.

#10011 : 10011

AD19 is selected as input.

#10100 : 10100

AD20 is selected as input.

#10101 : 10101

AD21 is selected as input.

#10110 : 10110

AD22 is selected as input.

#10111 : 10111

AD23 is selected as input.

#11010 : 11010

Temp Sensor (single-ended) is selected as input.

#11011 : 11011

Bandgap (single-ended) is selected as input.

#11101 : 11101

VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL].

#11110 : 11110

VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL].

#11111 : 11111

Module is disabled.

#11000 : 11000

Reserved.

#11001 : 11001

Reserved.

#11100 : 11100

Reserved.

End of enumeration elements list.

RESERVED : no description available
bits : 5 - 5 (1 bit)
access : read-only

AIEN : Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Conversion complete interrupt is disabled.

#1 : 1

Conversion complete interrupt is enabled.

End of enumeration elements list.

COCO : Conversion Complete Flag
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

Conversion is not completed.

#1 : 1

Conversion is completed.

End of enumeration elements list.

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only


CLP3

ADC Plus-Side General Calibration Value Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLP3 CLP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLP3 RESERVED

CLP3 : no description available
bits : 0 - 8 (9 bit)
access : read-write

RESERVED : no description available
bits : 9 - 31 (23 bit)
access : read-only


CLP2

ADC Plus-Side General Calibration Value Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLP2 CLP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLP2 RESERVED

CLP2 : no description available
bits : 0 - 7 (8 bit)
access : read-write

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only


CLP1

ADC Plus-Side General Calibration Value Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLP1 CLP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLP1 RESERVED

CLP1 : no description available
bits : 0 - 6 (7 bit)
access : read-write

RESERVED : no description available
bits : 7 - 31 (25 bit)
access : read-only


CV2

Compare Value Registers
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CV2 CV2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CV RESERVED

CV : Compare Value.
bits : 0 - 15 (16 bit)
access : read-write

RESERVED : no description available
bits : 16 - 31 (16 bit)
access : read-only


CLP0

ADC Plus-Side General Calibration Value Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLP0 CLP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLP0 RESERVED

CLP0 : no description available
bits : 0 - 5 (6 bit)
access : read-write

RESERVED : no description available
bits : 6 - 31 (26 bit)
access : read-only


CFG1

ADC Configuration Register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG1 CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADICLK MODE ADLSMP ADIV ADLPC RESERVED

ADICLK : Input Clock Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

Bus clock

#01 : 01

(Bus clock)/2

#10 : 10

Alternate clock (ALTCLK)

#11 : 11

Asynchronous clock (ADACK)

End of enumeration elements list.

MODE : Conversion mode selection
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 00

It is single-ended 8-bit conversion.

#01 : 01

It is single-ended 12-bit conversion .

#10 : 10

It is single-ended 10-bit conversion .

#11 : 11

Reserved. Do not set the bitfield to this value.

End of enumeration elements list.

ADLSMP : Sample time configuration
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Short sample time.

#1 : 1

Long sample time.

End of enumeration elements list.

ADIV : Clock Divide Select
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

#00 : 00

The divide ratio is 1 and the clock rate is input clock.

#01 : 01

The divide ratio is 2 and the clock rate is (input clock)/2.

#10 : 10

The divide ratio is 4 and the clock rate is (input clock)/4.

#11 : 11

The divide ratio is 8 and the clock rate is (input clock)/8.

End of enumeration elements list.

ADLPC : Low-Power Configuration
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal power configuration.

#1 : 1

Low-power configuration. The power is reduced at the expense of maximum clock speed.

End of enumeration elements list.

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only


CFG2

ADC Configuration Register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG2 CFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADLSTS ADHSC ADACKEN MUXSEL RESERVED RESERVED

ADLSTS : Long Sample Time Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 00

Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.

#01 : 01

12 extra ADCK cycles; 16 ADCK cycles total sample time.

#10 : 10

6 extra ADCK cycles; 10 ADCK cycles total sample time.

#11 : 11

2 extra ADCK cycles; 6 ADCK cycles total sample time.

End of enumeration elements list.

ADHSC : High-Speed Configuration
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal conversion sequence selected.

#1 : 1

High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.

End of enumeration elements list.

ADACKEN : Asynchronous Clock Output Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.

#1 : 1

Asynchronous clock and clock output is enabled regardless of the state of the ADC.

End of enumeration elements list.

MUXSEL : ADC Mux Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

ADxxa channels are selected.

#1 : 1

ADxxb channels are selected.

End of enumeration elements list.

RESERVED : no description available
bits : 5 - 7 (3 bit)
access : read-only

RESERVED : no description available
bits : 8 - 31 (24 bit)
access : read-only



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