Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
UART Baud Rate Register High
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBR : Baud Rate Modulo Divisor.
bits : 0 - 4 (5 bit)
access : read-write
SBNS : Stop Bit Number Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
One stop bit.
#1 : 1
Two stop bit.
End of enumeration elements list.
RXEDGIE : RX Input Active Edge Interrupt Enable (for RXEDGIF)
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware interrupts from UART _S2[RXEDGIF] disabled (use polling).
#1 : 1
Hardware interrupt requested when UART _S2[RXEDGIF] flag is 1.
End of enumeration elements list.
LBKDIE : LIN Break Detect Interrupt Enable (for LBKDIF)
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware interrupts from UART _S2[LBKDIF] disabled (use polling).
#1 : 1
Hardware interrupt requested when UART _S2[LBKDIF] flag is 1.
End of enumeration elements list.
UART Baud Rate Register Low
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBR : Baud Rate Modulo Divisor
bits : 0 - 7 (8 bit)
access : read-write
UART Control Register 1
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PT : Parity Type
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Even parity.
#1 : 1
Odd parity.
End of enumeration elements list.
PE : Parity Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No hardware parity generation or checking.
#1 : 1
Parity enabled.
End of enumeration elements list.
ILT : Idle Line Type Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Idle character bit count starts after start bit.
#1 : 1
Idle character bit count starts after stop bit.
End of enumeration elements list.
WAKE : Receiver Wakeup Method Select
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Idle-line wakeup.
#1 : 1
Address-mark wakeup.
End of enumeration elements list.
M : 9-Bit or 8-Bit Mode Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver and transmitter use 8-bit data characters.
#1 : 1
Receiver and transmitter use 9-bit data characters.
End of enumeration elements list.
RSRC : Receiver Source Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the UART _RX pins.
#1 : 1
Single-wire UART mode where the UART _TX pin is connected to the transmitter output and receiver input.
End of enumeration elements list.
DOZEEN : Doze Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART is enabled in Wait mode.
#1 : 1
UART is disabled in Wait mode.
End of enumeration elements list.
LOOPS : Loop Mode Select
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation - UART _RX and UART _TX use separate pins.
#1 : 1
Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) UART _RX pin is not used by UART .
End of enumeration elements list.
UART Control Register 2
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBK : Send Break
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal transmitter operation.
#1 : 1
Queue break character(s) to be sent.
End of enumeration elements list.
RWU : Receiver Wakeup Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal UART receiver operation.
#1 : 1
UART receiver in standby waiting for wakeup condition.
End of enumeration elements list.
RE : Receiver Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver disabled.
#1 : 1
Receiver enabled.
End of enumeration elements list.
TE : Transmitter Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitter disabled.
#1 : 1
Transmitter enabled.
End of enumeration elements list.
ILIE : Idle Line Interrupt Enable for IDLE
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware interrupts from IDLE disabled; use polling.
#1 : 1
Hardware interrupt requested when IDLE flag is 1.
End of enumeration elements list.
RIE : Receiver Interrupt Enable for RDRF
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware interrupts from RDRF disabled; use polling.
#1 : 1
Hardware interrupt requested when RDRF flag is 1.
End of enumeration elements list.
TCIE : Transmission Complete Interrupt Enable for TC
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware interrupts from TC disabled; use polling.
#1 : 1
Hardware interrupt requested when TC flag is 1.
End of enumeration elements list.
TIE : Transmit Interrupt Enable for TDRE
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware interrupts from TDRE disabled; use polling.
#1 : 1
Hardware interrupt requested when TDRE flag is 1.
End of enumeration elements list.
UART Status Register 1
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF : Parity Error Flag
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No parity error.
#1 : 1
Parity error.
End of enumeration elements list.
FE : Framing Error Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No framing error detected. This does not guarantee the framing is correct.
#1 : 1
Framing error.
End of enumeration elements list.
NF : Noise Flag
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No noise detected.
#1 : 1
Noise detected in the received character in UART _D.
End of enumeration elements list.
OR : Receiver Overrun Flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No overrun.
#1 : 1
Receive overrun (new UART data lost).
End of enumeration elements list.
IDLE : Idle Line Flag
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No idle line detected.
#1 : 1
Idle line was detected.
End of enumeration elements list.
RDRF : Receive Data Register Full Flag
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive data buffer empty.
#1 : 1
Receive data buffer full.
End of enumeration elements list.
TC : Transmission Complete Flag
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmitter active (sending data, a preamble, or a break).
#1 : 1
Transmitter idle (transmission activity complete).
End of enumeration elements list.
TDRE : Transmit Data Register Empty Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit data buffer full.
#1 : 1
Transmit data buffer empty.
End of enumeration elements list.
UART Status Register 2
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAF : Receiver Active Flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
UART receiver idle waiting for a start bit.
#1 : 1
UART receiver active ( UART _RXD input not idle).
End of enumeration elements list.
LBKDE : LIN Break Detection Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
#1 : 1
Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).
End of enumeration elements list.
BRK13 : Break Character Generation Length
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
#1 : 1
Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).
End of enumeration elements list.
RWUID : Receive Wake Up Idle Detect
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character.
#1 : 1
During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.
End of enumeration elements list.
RXINV : Receive Data Inversion
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive data not inverted.
#1 : 1
Receive data inverted.
End of enumeration elements list.
MSBF : MSB First
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
#1 : 1
MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of C1[M], C1[PE] and C4[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of C1[M] and C1[PE].
End of enumeration elements list.
RXEDGIF : UART _RX Pin Active Edge Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No active edge on the receive pin has occurred.
#1 : 1
An active edge on the receive pin has occurred.
End of enumeration elements list.
LBKDIF : LIN Break Detect Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No LIN break character has been detected.
#1 : 1
LIN break character has been detected.
End of enumeration elements list.
UART Control Register 3
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEIE : Parity Error Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PF interrupts disabled; use polling).
#1 : 1
Hardware interrupt requested when PF is set.
End of enumeration elements list.
FEIE : Framing Error Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FE interrupts disabled; use polling.
#1 : 1
Hardware interrupt requested when FE is set.
End of enumeration elements list.
NEIE : Noise Error Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
NF interrupts disabled; use polling.
#1 : 1
Hardware interrupt requested when NF is set.
End of enumeration elements list.
ORIE : Overrun Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
OR interrupts disabled; use polling.
#1 : 1
Hardware interrupt requested when OR is set.
End of enumeration elements list.
TXINV : Transmit Data Inversion
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit data not inverted.
#1 : 1
Transmit data inverted.
End of enumeration elements list.
TXDIR : UART _TX Pin Direction in Single-Wire Mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART _TXD pin is an input in single-wire mode.
#1 : 1
UART _TXD pin is an output in single-wire mode.
End of enumeration elements list.
R9T8 : Receive Bit 9 / Transmit Bit 8
bits : 6 - 6 (1 bit)
access : read-write
R8T9 : Receive Bit 8 / Transmit Bit 9
bits : 7 - 7 (1 bit)
access : read-write
UART Data Register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R0T0 : no description available
bits : 0 - 0 (1 bit)
access : read-write
R1T1 : no description available
bits : 1 - 1 (1 bit)
access : read-write
R2T2 : no description available
bits : 2 - 2 (1 bit)
access : read-write
R3T3 : no description available
bits : 3 - 3 (1 bit)
access : read-write
R4T4 : no description available
bits : 4 - 4 (1 bit)
access : read-write
R5T5 : no description available
bits : 5 - 5 (1 bit)
access : read-write
R6T6 : no description available
bits : 6 - 6 (1 bit)
access : read-write
R7T7 : no description available
bits : 7 - 7 (1 bit)
access : read-write
UART Match Address Registers 1
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Match Address
bits : 0 - 7 (8 bit)
access : read-write
UART Match Address Registers 2
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Match Address
bits : 0 - 7 (8 bit)
access : read-write
UART Control Register 4
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSR : Over Sampling Ratio
bits : 0 - 4 (5 bit)
access : read-write
M10 : 10-bit Mode select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver and transmitter use 8-bit or 9-bit data characters.
#1 : 1
Receiver and transmitter use 10-bit data characters.
End of enumeration elements list.
MAEN2 : Match Address Mode Enable 2
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
All data received is transferred to the data buffer if MAEN1 is cleared.
#1 : 1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.
End of enumeration elements list.
MAEN1 : Match Address Mode Enable 1
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
All data received is transferred to the data buffer if MAEN2 is cleared.
#1 : 1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.
End of enumeration elements list.
UART Control Register 5
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESYNCDIS : Resynchronization Disable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Resynchronization during received data word is supported
#1 : 1
Resynchronization during received data word is disabled
End of enumeration elements list.
BOTHEDGE : Both Edge Sampling
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver samples input data using the rising edge of the baud rate clock.
#1 : 1
Receiver samples input data using the rising and falling edge of the baud rate clock.
End of enumeration elements list.
RESERVED : no description available
bits : 2 - 4 (3 bit)
access : read-only
RDMAE : Receiver Full DMA Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA request disabled.
#1 : 1
DMA request enabled.
End of enumeration elements list.
RESERVED : no description available
bits : 6 - 6 (1 bit)
access : read-only
TDMAE : Transmitter DMA Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA request disabled.
#1 : 1
DMA request enabled.
End of enumeration elements list.
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