\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Clock control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSION : HSI16 clock enable
bits : 8 - 8 (1 bit)
HSIKERON : HSI16 always enable for peripheral kernels
bits : 9 - 9 (1 bit)
HSIRDY : HSI16 clock ready flag
bits : 10 - 10 (1 bit)
HSIDIV : HSI16 clock division factor
bits : 11 - 13 (3 bit)
HSEON : HSE clock enable
bits : 16 - 16 (1 bit)
HSERDY : HSE clock ready flag
bits : 17 - 17 (1 bit)
HSEBYP : HSE crystal oscillator bypass
bits : 18 - 18 (1 bit)
CSSON : Clock security system enable
bits : 19 - 19 (1 bit)
PLLON : PLL enable
bits : 24 - 24 (1 bit)
PLLRDY : PLL clock ready flag
bits : 25 - 25 (1 bit)
Clock interrupt enable register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSIRDYIE : LSI ready interrupt enable
bits : 0 - 0 (1 bit)
LSERDYIE : LSE ready interrupt enable
bits : 1 - 1 (1 bit)
HSIRDYIE : HSI ready interrupt enable
bits : 3 - 3 (1 bit)
HSERDYIE : HSE ready interrupt enable
bits : 4 - 4 (1 bit)
PLLSYSRDYIE : PLL ready interrupt enable
bits : 5 - 5 (1 bit)
Clock interrupt flag register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LSIRDYF : LSI ready interrupt flag
bits : 0 - 0 (1 bit)
LSERDYF : LSE ready interrupt flag
bits : 1 - 1 (1 bit)
HSIRDYF : HSI ready interrupt flag
bits : 3 - 3 (1 bit)
HSERDYF : HSE ready interrupt flag
bits : 4 - 4 (1 bit)
PLLSYSRDYF : PLL ready interrupt flag
bits : 5 - 5 (1 bit)
CSSF : Clock security system interrupt flag
bits : 8 - 8 (1 bit)
LSECSSF : LSE Clock security system interrupt flag
bits : 9 - 9 (1 bit)
Clock interrupt clear register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
LSIRDYC : LSI ready interrupt clear
bits : 0 - 0 (1 bit)
LSERDYC : LSE ready interrupt clear
bits : 1 - 1 (1 bit)
HSIRDYC : HSI ready interrupt clear
bits : 3 - 3 (1 bit)
HSERDYC : HSE ready interrupt clear
bits : 4 - 4 (1 bit)
PLLSYSRDYC : PLL ready interrupt clear
bits : 5 - 5 (1 bit)
CSSC : Clock security system interrupt clear
bits : 8 - 8 (1 bit)
LSECSSC : LSE Clock security system interrupt clear
bits : 9 - 9 (1 bit)
GPIO reset register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOPARST : I/O port A reset
bits : 0 - 0 (1 bit)
IOPBRST : I/O port B reset
bits : 1 - 1 (1 bit)
IOPCRST : I/O port C reset
bits : 2 - 2 (1 bit)
IOPDRST : I/O port D reset
bits : 3 - 3 (1 bit)
IOPFRST : I/O port F reset
bits : 5 - 5 (1 bit)
AHB peripheral reset register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMARST : DMA1 reset
bits : 0 - 0 (1 bit)
FLASHRST : FLITF reset
bits : 8 - 8 (1 bit)
CRCRST : CRC reset
bits : 12 - 12 (1 bit)
APB peripheral reset register 1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2RST : TIM2 timer reset
bits : 0 - 0 (1 bit)
TIM3RST : TIM3 timer reset
bits : 1 - 1 (1 bit)
SPI2RST : SPI2 reset
bits : 14 - 14 (1 bit)
USART2RST : USART2 reset
bits : 17 - 17 (1 bit)
LPUART1RST : LPUART1 reset
bits : 20 - 20 (1 bit)
I2C1RST : I2C1 reset
bits : 21 - 21 (1 bit)
I2C2RST : I2C2 reset
bits : 22 - 22 (1 bit)
DBGRST : Debug support reset
bits : 27 - 27 (1 bit)
PWRRST : Power interface reset
bits : 28 - 28 (1 bit)
LPTIM2RST : Low Power Timer 2 reset
bits : 30 - 30 (1 bit)
LPTIM1RST : Low Power Timer 1 reset
bits : 31 - 31 (1 bit)
APB peripheral reset register 2
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCFGRST : SYSCFG, COMP and VREFBUF reset
bits : 0 - 0 (1 bit)
TIM1RST : TIM1 timer reset
bits : 11 - 11 (1 bit)
SPI1RST : SPI1 reset
bits : 12 - 12 (1 bit)
USART1RST : USART1 reset
bits : 14 - 14 (1 bit)
TIM14RST : TIM14 timer reset
bits : 15 - 15 (1 bit)
TIM16RST : TIM16 timer reset
bits : 17 - 17 (1 bit)
TIM17RST : TIM17 timer reset
bits : 18 - 18 (1 bit)
ADCRST : ADC reset
bits : 20 - 20 (1 bit)
GPIO clock enable register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOPAEN : I/O port A clock enable
bits : 0 - 0 (1 bit)
IOPBEN : I/O port B clock enable
bits : 1 - 1 (1 bit)
IOPCEN : I/O port C clock enable
bits : 2 - 2 (1 bit)
IOPDEN : I/O port D clock enable
bits : 3 - 3 (1 bit)
IOPFEN : I/O port F clock enable
bits : 5 - 5 (1 bit)
AHB peripheral clock enable register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAEN : DMA clock enable
bits : 0 - 0 (1 bit)
FLASHEN : Flash memory interface clock enable
bits : 8 - 8 (1 bit)
CRCEN : CRC clock enable
bits : 12 - 12 (1 bit)
APB peripheral clock enable register 1
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2EN : TIM2 timer clock enable
bits : 0 - 0 (1 bit)
TIM3EN : TIM3 timer clock enable
bits : 1 - 1 (1 bit)
RTCAPBEN : RTC APB clock enable
bits : 10 - 10 (1 bit)
WWDGEN : WWDG clock enable
bits : 11 - 11 (1 bit)
SPI2EN : SPI2 clock enable
bits : 14 - 14 (1 bit)
USART2EN : USART2 clock enable
bits : 17 - 17 (1 bit)
LPUART1EN : LPUART1 clock enable
bits : 20 - 20 (1 bit)
I2C1EN : I2C1 clock enable
bits : 21 - 21 (1 bit)
I2C2EN : I2C2 clock enable
bits : 22 - 22 (1 bit)
DBGEN : Debug support clock enable
bits : 27 - 27 (1 bit)
PWREN : Power interface clock enable
bits : 28 - 28 (1 bit)
LPTIM2EN : LPTIM2 clock enable
bits : 30 - 30 (1 bit)
LPTIM1EN : LPTIM1 clock enable
bits : 31 - 31 (1 bit)
Internal clock sources calibration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSICAL : HSI16 clock calibration
bits : 0 - 7 (8 bit)
access : read-only
HSITRIM : HSI16 clock trimming
bits : 8 - 14 (7 bit)
access : read-write
APB peripheral clock enable register 2
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCFGEN : SYSCFG, COMP and VREFBUF clock enable
bits : 0 - 0 (1 bit)
TIM1EN : TIM1 timer clock enable
bits : 11 - 11 (1 bit)
SPI1EN : SPI1 clock enable
bits : 12 - 12 (1 bit)
USART1EN : USART1 clock enable
bits : 14 - 14 (1 bit)
TIM14EN : TIM14 timer clock enable
bits : 15 - 15 (1 bit)
TIM16EN : TIM16 timer clock enable
bits : 17 - 17 (1 bit)
TIM17EN : TIM16 timer clock enable
bits : 18 - 18 (1 bit)
ADCEN : ADC clock enable
bits : 20 - 20 (1 bit)
GPIO in Sleep mode clock enable register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOPASMEN : I/O port A clock enable during Sleep mode
bits : 0 - 0 (1 bit)
IOPBSMEN : I/O port B clock enable during Sleep mode
bits : 1 - 1 (1 bit)
IOPCSMEN : I/O port C clock enable during Sleep mode
bits : 2 - 2 (1 bit)
IOPDSMEN : I/O port D clock enable during Sleep mode
bits : 3 - 3 (1 bit)
IOPFSMEN : I/O port F clock enable during Sleep mode
bits : 5 - 5 (1 bit)
AHB peripheral clock enable in Sleep mode register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMASMEN : DMA clock enable during Sleep mode
bits : 0 - 0 (1 bit)
FLASHSMEN : Flash memory interface clock enable during Sleep mode
bits : 8 - 8 (1 bit)
SRAMSMEN : SRAM clock enable during Sleep mode
bits : 9 - 9 (1 bit)
CRCSMEN : CRC clock enable during Sleep mode
bits : 12 - 12 (1 bit)
APB peripheral clock enable in Sleep mode register 1
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIM2SMEN : TIM2 timer clock enable during Sleep mode
bits : 0 - 0 (1 bit)
TIM3SMEN : TIM3 timer clock enable during Sleep mode
bits : 1 - 1 (1 bit)
RTCAPBSMEN : RTC APB clock enable during Sleep mode
bits : 10 - 10 (1 bit)
WWDGSMEN : WWDG clock enable during Sleep mode
bits : 11 - 11 (1 bit)
SPI2SMEN : SPI2 clock enable during Sleep mode
bits : 14 - 14 (1 bit)
USART2SMEN : USART2 clock enable during Sleep mode
bits : 17 - 17 (1 bit)
LPUART1SMEN : LPUART1 clock enable during Sleep mode
bits : 20 - 20 (1 bit)
I2C1SMEN : I2C1 clock enable during Sleep mode
bits : 21 - 21 (1 bit)
I2C2SMEN : I2C2 clock enable during Sleep mode
bits : 22 - 22 (1 bit)
DBGSMEN : Debug support clock enable during Sleep mode
bits : 27 - 27 (1 bit)
PWRSMEN : Power interface clock enable during Sleep mode
bits : 28 - 28 (1 bit)
LPTIM2SMEN : Low Power Timer 2 clock enable during Sleep mode
bits : 30 - 30 (1 bit)
LPTIM1SMEN : Low Power Timer 1 clock enable during Sleep mode
bits : 31 - 31 (1 bit)
APB peripheral clock enable in Sleep mode register 2
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCFGSMEN : SYSCFG, COMP and VREFBUF clock enable during Sleep mode
bits : 0 - 0 (1 bit)
TIM1SMEN : TIM1 timer clock enable during Sleep mode
bits : 11 - 11 (1 bit)
SPI1SMEN : SPI1 clock enable during Sleep mode
bits : 12 - 12 (1 bit)
USART1SMEN : USART1 clock enable during Sleep mode
bits : 14 - 14 (1 bit)
TIM14SMEN : TIM14 timer clock enable during Sleep mode
bits : 15 - 15 (1 bit)
TIM16SMEN : TIM16 timer clock enable during Sleep mode
bits : 17 - 17 (1 bit)
TIM17SMEN : TIM16 timer clock enable during Sleep mode
bits : 18 - 18 (1 bit)
ADCSMEN : ADC clock enable during Sleep mode
bits : 20 - 20 (1 bit)
Peripherals independent clock configuration register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USART1SEL : USART1 clock source selection
bits : 0 - 1 (2 bit)
LPUART1SEL : LPUART1 clock source selection
bits : 10 - 11 (2 bit)
I2C1SEL : I2C1 clock source selection
bits : 12 - 13 (2 bit)
I2S2SEL : I2S1 clock source selection
bits : 14 - 15 (2 bit)
LPTIM1SEL : LPTIM1 clock source selection
bits : 18 - 19 (2 bit)
LPTIM2SEL : LPTIM2 clock source selection
bits : 20 - 21 (2 bit)
TIM1SEL : TIM1 clock source selection
bits : 22 - 22 (1 bit)
RNGSEL : RNG clock source selection
bits : 26 - 27 (2 bit)
RNGDIV : Division factor of RNG clock divider
bits : 28 - 29 (2 bit)
ADCSEL : ADCs clock source selection
bits : 30 - 31 (2 bit)
RTC domain control register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSEON : LSE oscillator enable
bits : 0 - 0 (1 bit)
LSERDY : LSE oscillator ready
bits : 1 - 1 (1 bit)
LSEBYP : LSE oscillator bypass
bits : 2 - 2 (1 bit)
LSEDRV : LSE oscillator drive capability
bits : 3 - 4 (2 bit)
LSECSSON : CSS on LSE enable
bits : 5 - 5 (1 bit)
LSECSSD : CSS on LSE failure Detection
bits : 6 - 6 (1 bit)
RTCSEL : RTC clock source selection
bits : 8 - 9 (2 bit)
RTCEN : RTC clock enable
bits : 15 - 15 (1 bit)
BDRST : RTC domain software reset
bits : 16 - 16 (1 bit)
LSCOEN : Low-speed clock output (LSCO) enable
bits : 24 - 24 (1 bit)
LSCOSEL : Low-speed clock output selection
bits : 25 - 25 (1 bit)
Control/status register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSION : LSI oscillator enable
bits : 0 - 0 (1 bit)
LSIRDY : LSI oscillator ready
bits : 1 - 1 (1 bit)
RMVF : Remove reset flags
bits : 23 - 23 (1 bit)
OBLRSTF : Option byte loader reset flag
bits : 25 - 25 (1 bit)
PINRSTF : Pin reset flag
bits : 26 - 26 (1 bit)
PWRRSTF : BOR or POR/PDR flag
bits : 27 - 27 (1 bit)
SFTRSTF : Software reset flag
bits : 28 - 28 (1 bit)
IWDGRSTF : Independent window watchdog reset flag
bits : 29 - 29 (1 bit)
WWDGRSTF : Window watchdog reset flag
bits : 30 - 30 (1 bit)
LPWRRSTF : Low-power reset flag
bits : 31 - 31 (1 bit)
Clock configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW : System clock switch
bits : 0 - 2 (3 bit)
access : read-write
SWS : System clock switch status
bits : 3 - 5 (3 bit)
access : read-only
HPRE : AHB prescaler
bits : 8 - 11 (4 bit)
access : read-write
PPRE : APB prescaler
bits : 12 - 14 (3 bit)
access : read-write
MCOSEL : Microcontroller clock output
bits : 24 - 26 (3 bit)
access : read-write
MCOPRE : Microcontroller clock output prescaler
bits : 28 - 30 (3 bit)
access : read-only
PLL configuration register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLSRC : PLL input clock source
bits : 0 - 1 (2 bit)
PLLM : Division factor M of the PLL input clock divider
bits : 4 - 6 (3 bit)
PLLN : PLL frequency multiplication factor N
bits : 8 - 14 (7 bit)
PLLPEN : PLLPCLK clock output enable
bits : 16 - 16 (1 bit)
PLLP : PLL VCO division factor P for PLLPCLK clock output
bits : 17 - 21 (5 bit)
PLLQEN : PLLQCLK clock output enable
bits : 24 - 24 (1 bit)
PLLQ : PLL VCO division factor Q for PLLQCLK clock output
bits : 25 - 27 (3 bit)
PLLREN : PLLRCLK clock output enable
bits : 28 - 28 (1 bit)
PLLR : PLL VCO division factor R for PLLRCLK clock output
bits : 29 - 31 (3 bit)
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