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TRGMUX

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

Registers

TRGMUX_DMAMUX1

TRGMUX_FLEXIO

TRGMUX_LPUART0

TRGMUX_LPUART1

TRGMUX_LPI2C0

TRGMUX_LPI2C1

TRGMUX_LPSPI0

TRGMUX_LPSPI1

TRGMUX_LPIT1

TRGMUX_TPM0

TRGMUX_TPM1


TRGMUX_DMAMUX1

TRGMUX TRGCFG Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_DMAMUX1 TRGMUX_DMAMUX1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 SEL3 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write

Enumeration:

#0 : 0

Trigger function is disabled.

#1 : 1

Port pin trigger input is selected.

#10 : 2

FlexIO Timer 0 input is selected.

#11 : 3

FlexIO Timer 1 input is selected.

#100 : 4

FlexIO Timer 2 input is selected.

#101 : 5

FlexIO Timer 3 input is selected.

#110 : 6

FlexIO Timer 4 input is selected.

#111 : 7

FlexIO Timer 5 input is selected.

#1000 : 8

FlexIO Timer 6 input is selected.

#1001 : 9

FlexIO Timer 7 input is selected.

#1010 : 10

TPM0 Overflow is selected

#1011 : 11

TPM0 Channel 0 is selected

#1100 : 12

TPM0 Channel 1 is selected

#1101 : 13

TPM1 Overflow is selected

#1110 : 14

TPM1 Channel 0 is selected

#1111 : 15

TPM1 Channel 1 is selected

#10000 : 16

LPIT1 Channel 0 is selected

#10001 : 17

LPIT1 Channel 1 is selected

#10010 : 18

LPIT1 Channel 2 is selected

#10011 : 19

LPIT1 Channel 3 is selected

#10100 : 20

LPUART0 RX Data is selected.

#10101 : 21

LPUART0 TX Data is selected.

#10110 : 22

LPUART0 RX Idle is selected.

#10111 : 23

LPUART1 RX Data is selected.

#11000 : 24

LPUART1 TX Data is selected.

#11001 : 25

LPUART1 RX Idle is selected.

#11010 : 26

LPI2C0 Master STOP is selected.

#11011 : 27

LPI2C0 Slave STOP is selected.

#11100 : 28

LPI2C1 Master STOP is selected.

#11101 : 29

LPI2C1 Slave STOP is selected.

#11110 : 30

LPSPI0 Frame is selected.

#11111 : 31

LPSPI0 RX data is selected.

#100000 : 32

LPSPI1 Frame is selected.

#100001 : 33

LPSPI1 RX data is selected.

#100010 : 34

RTC Seconds Counter is selected.

#100011 : 35

RTC Alarm is selected.

#100100 : 36

LPTMR0 Trigger is selected.

#100101 : 37

LPTMR1 Trigger is selected.

#100110 : 38

CMP0 Output is selected.

#100111 : 39

CMP1 Output is selected.

#101000 : 40

ADC0 Conversion A Complete is selected.

#101001 : 41

ADC0 Conversion B Complete is selected.

#101010 : 42

Port A Pin Trigger is selected.

#101011 : 43

Port B Pin Trigger is selected.

#101100 : 44

Port C Pin Trigger is selected.

#101101 : 45

Port D Pin Trigger is selected.

#101110 : 46

Port E Pin Trigger is selected.

#101111 : 47

TPM2 Overflow selected.

#110000 : 48

TPM2 Channel 0 is selected.

#110001 : 49

TPM2 Channel 1 is selected.

#110010 : 50

LPIT0 Channel 0 is selected.

#110011 : 51

LPIT0 Channel 1 is selected.

#110100 : 52

LPIT0 Channel 2 is selected.

#110101 : 53

LPIT0 Channel 3 is selected.

#110110 : 54

USB Start-of-Frame is selected.

#110111 : 55

LPUART2 RX Data is selected.

#111000 : 56

LPUART2 TX Data is selected.

#111001 : 57

LPUART2 RX Idle is selected.

#111010 : 58

LPI2C2 Master STOP is selected.

#111011 : 59

LPI2C2 Slave STOP is selected.

#111100 : 60

LPSPI2 Frame is selected.

#111101 : 61

LPSPI2 RX Data is selected.

#111110 : 62

SAI TX Frame Sync selected.

#111111 : 63

SAI RX Frame Sync is selected.

End of enumeration elements list.

LK : Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Register can be written.

#1 : 1

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_FLEXIO

TRGMUX TRGCFG Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_FLEXIO TRGMUX_FLEXIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 SEL3 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write

Enumeration:

#0 : 0

Trigger function is disabled.

#1 : 1

Port pin trigger input is selected.

#10 : 2

FlexIO Timer 0 input is selected.

#11 : 3

FlexIO Timer 1 input is selected.

#100 : 4

FlexIO Timer 2 input is selected.

#101 : 5

FlexIO Timer 3 input is selected.

#110 : 6

FlexIO Timer 4 input is selected.

#111 : 7

FlexIO Timer 5 input is selected.

#1000 : 8

FlexIO Timer 6 input is selected.

#1001 : 9

FlexIO Timer 7 input is selected.

#1010 : 10

TPM0 Overflow is selected

#1011 : 11

TPM0 Channel 0 is selected

#1100 : 12

TPM0 Channel 1 is selected

#1101 : 13

TPM1 Overflow is selected

#1110 : 14

TPM1 Channel 0 is selected

#1111 : 15

TPM1 Channel 1 is selected

#10000 : 16

LPIT1 Channel 0 is selected

#10001 : 17

LPIT1 Channel 1 is selected

#10010 : 18

LPIT1 Channel 2 is selected

#10011 : 19

LPIT1 Channel 3 is selected

#10100 : 20

LPUART0 RX Data is selected.

#10101 : 21

LPUART0 TX Data is selected.

#10110 : 22

LPUART0 RX Idle is selected.

#10111 : 23

LPUART1 RX Data is selected.

#11000 : 24

LPUART1 TX Data is selected.

#11001 : 25

LPUART1 RX Idle is selected.

#11010 : 26

LPI2C0 Master STOP is selected.

#11011 : 27

LPI2C0 Slave STOP is selected.

#11100 : 28

LPI2C1 Master STOP is selected.

#11101 : 29

LPI2C1 Slave STOP is selected.

#11110 : 30

LPSPI0 Frame is selected.

#11111 : 31

LPSPI0 RX data is selected.

#100000 : 32

LPSPI1 Frame is selected.

#100001 : 33

LPSPI1 RX data is selected.

#100010 : 34

RTC Seconds Counter is selected.

#100011 : 35

RTC Alarm is selected.

#100100 : 36

LPTMR0 Trigger is selected.

#100101 : 37

LPTMR1 Trigger is selected.

#100110 : 38

CMP0 Output is selected.

#100111 : 39

CMP1 Output is selected.

#101000 : 40

ADC0 Conversion A Complete is selected.

#101001 : 41

ADC0 Conversion B Complete is selected.

#101010 : 42

Port A Pin Trigger is selected.

#101011 : 43

Port B Pin Trigger is selected.

#101100 : 44

Port C Pin Trigger is selected.

#101101 : 45

Port D Pin Trigger is selected.

#101110 : 46

Port E Pin Trigger is selected.

#101111 : 47

TPM2 Overflow selected.

#110000 : 48

TPM2 Channel 0 is selected.

#110001 : 49

TPM2 Channel 1 is selected.

#110010 : 50

LPIT0 Channel 0 is selected.

#110011 : 51

LPIT0 Channel 1 is selected.

#110100 : 52

LPIT0 Channel 2 is selected.

#110101 : 53

LPIT0 Channel 3 is selected.

#110110 : 54

USB Start-of-Frame is selected.

#110111 : 55

LPUART2 RX Data is selected.

#111000 : 56

LPUART2 TX Data is selected.

#111001 : 57

LPUART2 RX Idle is selected.

#111010 : 58

LPI2C2 Master STOP is selected.

#111011 : 59

LPI2C2 Slave STOP is selected.

#111100 : 60

LPSPI2 Frame is selected.

#111101 : 61

LPSPI2 RX Data is selected.

#111110 : 62

SAI TX Frame Sync selected.

#111111 : 63

SAI RX Frame Sync is selected.

End of enumeration elements list.

LK : Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Register can be written.

#1 : 1

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPUART0

TRGMUX TRGCFG Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPUART0 TRGMUX_LPUART0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Register can be written.

#1 : 1

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPUART1

TRGMUX TRGCFG Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPUART1 TRGMUX_LPUART1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Register can be written.

#1 : 1

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPI2C0

TRGMUX TRGCFG Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPI2C0 TRGMUX_LPI2C0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Register can be written.

#1 : 1

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPI2C1

TRGMUX TRGCFG Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPI2C1 TRGMUX_LPI2C1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Register can be written.

#1 : 1

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPSPI0

TRGMUX TRGCFG Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPSPI0 TRGMUX_LPSPI0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Register can be written.

#1 : 1

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPSPI1

TRGMUX TRGCFG Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPSPI1 TRGMUX_LPSPI1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

LK : Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Register can be written.

#1 : 1

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_LPIT1

TRGMUX TRGCFG Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_LPIT1 TRGMUX_LPIT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 SEL3 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

SEL3 : Trigger MUX Input 3 Source Select
bits : 24 - 29 (6 bit)
access : read-write

Enumeration:

#0 : 0

Trigger function is disabled.

#1 : 1

Port pin trigger input is selected.

#10 : 2

FlexIO Timer 0 input is selected.

#11 : 3

FlexIO Timer 1 input is selected.

#100 : 4

FlexIO Timer 2 input is selected.

#101 : 5

FlexIO Timer 3 input is selected.

#110 : 6

FlexIO Timer 4 input is selected.

#111 : 7

FlexIO Timer 5 input is selected.

#1000 : 8

FlexIO Timer 6 input is selected.

#1001 : 9

FlexIO Timer 7 input is selected.

#1010 : 10

TPM0 Overflow is selected

#1011 : 11

TPM0 Channel 0 is selected

#1100 : 12

TPM0 Channel 1 is selected

#1101 : 13

TPM1 Overflow is selected

#1110 : 14

TPM1 Channel 0 is selected

#1111 : 15

TPM1 Channel 1 is selected

#10000 : 16

LPIT1 Channel 0 is selected

#10001 : 17

LPIT1 Channel 1 is selected

#10010 : 18

LPIT1 Channel 2 is selected

#10011 : 19

LPIT1 Channel 3 is selected

#10100 : 20

LPUART0 RX Data is selected.

#10101 : 21

LPUART0 TX Data is selected.

#10110 : 22

LPUART0 RX Idle is selected.

#10111 : 23

LPUART1 RX Data is selected.

#11000 : 24

LPUART1 TX Data is selected.

#11001 : 25

LPUART1 RX Idle is selected.

#11010 : 26

LPI2C0 Master STOP is selected.

#11011 : 27

LPI2C0 Slave STOP is selected.

#11100 : 28

LPI2C1 Master STOP is selected.

#11101 : 29

LPI2C1 Slave STOP is selected.

#11110 : 30

LPSPI0 Frame is selected.

#11111 : 31

LPSPI0 RX data is selected.

#100000 : 32

LPSPI1 Frame is selected.

#100001 : 33

LPSPI1 RX data is selected.

#100010 : 34

RTC Seconds Counter is selected.

#100011 : 35

RTC Alarm is selected.

#100100 : 36

LPTMR0 Trigger is selected.

#100101 : 37

LPTMR1 Trigger is selected.

#100110 : 38

CMP0 Output is selected.

#100111 : 39

CMP1 Output is selected.

#101000 : 40

ADC0 Conversion A Complete is selected.

#101001 : 41

ADC0 Conversion B Complete is selected.

#101010 : 42

Port A Pin Trigger is selected.

#101011 : 43

Port B Pin Trigger is selected.

#101100 : 44

Port C Pin Trigger is selected.

#101101 : 45

Port D Pin Trigger is selected.

#101110 : 46

Port E Pin Trigger is selected.

#101111 : 47

TPM2 Overflow selected.

#110000 : 48

TPM2 Channel 0 is selected.

#110001 : 49

TPM2 Channel 1 is selected.

#110010 : 50

LPIT0 Channel 0 is selected.

#110011 : 51

LPIT0 Channel 1 is selected.

#110100 : 52

LPIT0 Channel 2 is selected.

#110101 : 53

LPIT0 Channel 3 is selected.

#110110 : 54

USB Start-of-Frame is selected.

#110111 : 55

LPUART2 RX Data is selected.

#111000 : 56

LPUART2 TX Data is selected.

#111001 : 57

LPUART2 RX Idle is selected.

#111010 : 58

LPI2C2 Master STOP is selected.

#111011 : 59

LPI2C2 Slave STOP is selected.

#111100 : 60

LPSPI2 Frame is selected.

#111101 : 61

LPSPI2 RX Data is selected.

#111110 : 62

SAI TX Frame Sync selected.

#111111 : 63

SAI RX Frame Sync is selected.

End of enumeration elements list.

LK : Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Register can be written.

#1 : 1

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_TPM0

TRGMUX TRGCFG Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_TPM0 TRGMUX_TPM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

LK : Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Register can be written.

#1 : 1

Register cannot be written until the next system Reset.

End of enumeration elements list.


TRGMUX_TPM1

TRGMUX TRGCFG Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGMUX_TPM1 TRGMUX_TPM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL0 SEL1 SEL2 LK

SEL0 : Trigger MUX Input 0 Source Select
bits : 0 - 5 (6 bit)
access : read-write

SEL1 : Trigger MUX Input 1 Source Select
bits : 8 - 13 (6 bit)
access : read-write

SEL2 : Trigger MUX Input 2 Source Select
bits : 16 - 21 (6 bit)
access : read-write

LK : Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Register can be written.

#1 : 1

Register cannot be written until the next system Reset.

End of enumeration elements list.



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