Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x4C byte (0x0)
mem_usage : registers
protection : not protected
Version ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VER : Version ID of the module
bits : 0 - 31 (32 bit)
access : read-only
Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IC : Inverse Convention
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Direction convention transfers enabled (default)
#1 : 1
Inverse convention transfers enabled
End of enumeration elements list.
ICM : Initial Character Mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Initial Character Mode disabled
#1 : 1
Initial Character Mode enabled (default)
End of enumeration elements list.
ANACK : Auto NACK Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
NACK generation on errors disabled
#1 : 1
NACK generation on errors enabled (default)
End of enumeration elements list.
ONACK : Overrun NACK Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
NACK generation on overrun is disabled (default)
#1 : 1
NACK generation on overrun is enabled
End of enumeration elements list.
FLSH_RX : Flush Receiver Bit
bits : 8 - 8 (1 bit)
access : write-only
Enumeration:
#0 : 0
EMV SIM Receiver normal operation (default)
#1 : 1
EMV SIM Receiver held in Reset
End of enumeration elements list.
FLSH_TX : Flush Transmitter Bit
bits : 9 - 9 (1 bit)
access : write-only
Enumeration:
#0 : 0
EMV SIM Transmitter normal operation (default)
#1 : 1
EMV SIM Transmitter held in Reset
End of enumeration elements list.
SW_RST : Software Reset Bit
bits : 10 - 10 (1 bit)
access : write-only
Enumeration:
#0 : 0
EMV SIM Normal operation (default)
#1 : 1
EMV SIM held in Reset
End of enumeration elements list.
KILL_CLOCKS : Kill all internal clocks
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
EMV SIM input clock enabled (default)
#1 : 1
EMV SIM input clock is disabled
End of enumeration elements list.
DOZE_EN : Doze Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
DOZE instruction will gate all internal EMV SIM clocks as well as the Smart Card clock when the transmit FIFO is empty (default)
#1 : 1
DOZE instruction has no effect on EMV SIM module
End of enumeration elements list.
STOP_EN : STOP Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
STOP instruction shuts down all EMV SIM clocks (default)
#1 : 1
STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card)
End of enumeration elements list.
RCV_EN : Receiver Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
EMV SIM Receiver disabled (default)
#1 : 1
EMV SIM Receiver enabled
End of enumeration elements list.
XMT_EN : Transmitter Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
EMV SIM Transmitter disabled (default)
#1 : 1
EMV SIM Transmitter enabled
End of enumeration elements list.
RCVR_11 : Receiver 11 ETU Mode Enable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver configured for 12 ETU operation mode (default)
#1 : 1
Receiver configured for 11 ETU operation mode
End of enumeration elements list.
RX_DMA_EN : Receive DMA Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
No DMA Read Request asserted for Receiver (default)
#1 : 1
DMA Read Request asserted for Receiver
End of enumeration elements list.
TX_DMA_EN : Transmit DMA Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
No DMA Write Request asserted for Transmitter (default)
#1 : 1
DMA Write Request asserted for Transmitter
End of enumeration elements list.
INV_CRC_VAL : Invert bits in the CRC Output Value
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bits in CRC Output value will not be inverted.
#1 : 1
Bits in CRC Output value will be inverted. (default)
End of enumeration elements list.
CRC_OUT_FLIP : CRC Output Value Bit Reversal or Flip
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bits within the CRC output bytes will not be reversed i.e. 15:0 will remain 15:0 (default)
#1 : 1
Bits within the CRC output bytes will be reversed i.e. 15:0 will become {8:15,0:7}
End of enumeration elements list.
CRC_IN_FLIP : CRC Input Byte's Bit Reversal or Flip Control
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bits in the input byte will not be reversed (i.e. 7:0 will remain 7:0) before the CRC calculation (default)
#1 : 1
Bits in the input byte will be reversed (i.e. 7:0 will become 0:7) before CRC calculation
End of enumeration elements list.
CWT_EN : Character Wait Time Counter Enable
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Character Wait time Counter is disabled (default)
#1 : 1
Character Wait time counter is enabled
End of enumeration elements list.
LRC_EN : LRC Enable
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
8-bit Linear Redundancy Checking disabled (default)
#1 : 1
8-bit Linear Redundancy Checking enabled
End of enumeration elements list.
CRC_EN : CRC Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
16-bit Cyclic Redundancy Checking disabled (default)
#1 : 1
16-bit Cyclic Redundancy Checking enabled
End of enumeration elements list.
XMT_CRC_LRC : Transmit CRC or LRC Enable
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
No CRC or LRC value is transmitted (default)
#1 : 1
Transmit LRC or CRC info when FIFO empties (whichever is enabled)
End of enumeration elements list.
BWT_EN : Block Wait Time Counter Enable
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable BWT, BGT Counters (default)
#1 : 1
Enable BWT, BGT Counters
End of enumeration elements list.
Interrupt Mask Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDT_IM : Receive Data Threshold Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
RDTF interrupt enabled
#1 : 1
RDTF interrupt masked (default)
End of enumeration elements list.
TC_IM : Transmit Complete Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
TCF interrupt enabled
#1 : 1
TCF interrupt masked (default)
End of enumeration elements list.
RFO_IM : Receive FIFO Overflow Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
RFO interrupt enabled
#1 : 1
RFO interrupt masked (default)
End of enumeration elements list.
ETC_IM : Early Transmit Complete Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
ETC interrupt enabled
#1 : 1
ETC interrupt masked (default)
End of enumeration elements list.
TFE_IM : Transmit FIFO Empty Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
TFE interrupt enabled
#1 : 1
TFE interrupt masked (default)
End of enumeration elements list.
TNACK_IM : Transmit NACK Threshold Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
TNTE interrupt enabled
#1 : 1
TNTE interrupt masked (default)
End of enumeration elements list.
TFF_IM : Transmit FIFO Full Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
TFF interrupt enabled
#1 : 1
TFF interrupt masked (default)
End of enumeration elements list.
TDT_IM : Transmit Data Threshold Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
TDTF interrupt enabled
#1 : 1
TDTF interrupt masked (default)
End of enumeration elements list.
GPCNT0_IM : General Purpose Timer 0 Timeout Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPCNT0_TO interrupt enabled
#1 : 1
GPCNT0_TO interrupt masked (default)
End of enumeration elements list.
CWT_ERR_IM : Character Wait Time Error Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
CWT_ERR interrupt enabled
#1 : 1
CWT_ERR interrupt masked (default)
End of enumeration elements list.
RNACK_IM : Receiver NACK Threshold Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTE interrupt enabled
#1 : 1
RTE interrupt masked (default)
End of enumeration elements list.
BWT_ERR_IM : Block Wait Time Error Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
BWT_ERR interrupt enabled
#1 : 1
BWT_ERR interrupt masked (default)
End of enumeration elements list.
BGT_ERR_IM : Block Guard Time Error Interrupt
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
BGT_ERR interrupt enabled
#1 : 1
BGT_ERR interrupt masked (default)
End of enumeration elements list.
GPCNT1_IM : General Purpose Counter 1 Timeout Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPCNT1_TO interrupt enabled
#1 : 1
GPCNT1_TO interrupt masked (default)
End of enumeration elements list.
RX_DATA_IM : Receive Data Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
RX_DATA interrupt enabled
#1 : 1
RX_DATA interrupt masked (default)
End of enumeration elements list.
PEF_IM : Parity Error Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
PEF interrupt enabled
#1 : 1
PEF interrupt masked (default)
End of enumeration elements list.
Receiver Threshold Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDT : Receiver Data Threshold Value
bits : 0 - 3 (4 bit)
access : read-write
RNCK_THD : Receiver NACK Threshold Value
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
Zero Threshold. RTE will not be set
End of enumeration elements list.
Transmitter Threshold Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDT : Transmitter Data Threshold Value
bits : 0 - 3 (4 bit)
access : read-write
TNCK_THD : Transmitter NACK Threshold Value
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
TNTE will never be set; retransmission after NACK reception is disabled.
#0001 : 1
TNTE will be set after 1 nack is received; 0 retransmissions occurs.
#0010 : 10
TNTE will be set after 2 nacks are received; at most 1 retransmission occurs.
#0011 : 11
TNTE will be set after 3 nacks are received; at most 2 retransmissions occurs.
#1111 : 1111
TNTE will be set after 15 nacks are received; at most 14 retransmissions occurs.
End of enumeration elements list.
Receive Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFO : Receive FIFO Overflow Flag
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No overrun error has occurred (default)
#1 : 1
A byte was received when the received FIFO was already full
End of enumeration elements list.
RX_DATA : Receive Data Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No new byte is received
#1 : 1
New byte is received ans stored in Receive FIFO
End of enumeration elements list.
RDTF : Receive Data Threshold Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Number of unread bytes in receive FIFO less than the value set by RDT[3:0] (default).
#1 : 1
Number of unread bytes in receive FIFO greater or than equal to value set by RDT[3:0].
End of enumeration elements list.
LRC_OK : LRC Check OK Flag
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Current LRC value does not match remainder.
#1 : 1
Current calculated LRC value matches the expected result (i.e. zero).
End of enumeration elements list.
CRC_OK : CRC Check OK Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Current CRC value does not match remainder.
#1 : 1
Current calculated CRC value matches the expected result.
End of enumeration elements list.
CWT_ERR : Character Wait Time Error Flag
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No CWT violation has occurred (default).
#1 : 1
Time between two consecutive characters has exceeded the value in CHAR_WAIT.
End of enumeration elements list.
RTE : Received NACK Threshold Error Flag
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Number of NACKs generated by the receiver is less than the value programmed in RTH[3:0]
#1 : 1
Number of NACKs generated by the receiver is equal to the value programmed in RTH[3:0]
End of enumeration elements list.
BWT_ERR : Block Wait Time Error Flag
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Block wait time not exceeded
#1 : 1
Block wait time was exceeded
End of enumeration elements list.
BGT_ERR : Block Guard Time Error Flag
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Block guard time was sufficient
#1 : 1
Block guard time was too small
End of enumeration elements list.
PEF : Parity Error Flag
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No parity error detected
#1 : 1
Parity error detected
End of enumeration elements list.
FEF : Frame Error Flag
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No frame error detected
#1 : 1
Frame error detected
End of enumeration elements list.
RX_WPTR : Receive FIFO Write Pointer Value
bits : 16 - 17 (2 bit)
access : read-only
RX_CNT : Receive FIFO Byte Count
bits : 22 - 24 (3 bit)
access : read-only
Enumeration:
#000 : 0
FIFO is emtpy
End of enumeration elements list.
Transmitter Status Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TNTE : Transmit NACK Threshold Error Flag
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit NACK threshold has not been reached (default)
#1 : 1
Transmit NACK threshold reached; transmitter frozen
End of enumeration elements list.
TFE : Transmit FIFO Empty Flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit FIFO is not empty
#1 : 1
Transmit FIFO is empty (default)
End of enumeration elements list.
ETCF : Early Transmit Complete Flag
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit pending or in progress
#1 : 1
Transmit complete (default)
End of enumeration elements list.
TCF : Transmit Complete Flag
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit pending or in progress
#1 : 1
Transmit complete (default)
End of enumeration elements list.
TFF : Transmit FIFO Full Flag
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit FIFO Full condition has not occurred (default)
#1 : 1
A Transmit FIFO Full condition has occurred
End of enumeration elements list.
TDTF : Transmit Data Threshold Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Number of bytes in FIFO is greater than TDT[3:0], or bit has been cleared
#1 : 1
Number of bytes in FIFO is less than or equal to TDT[3:0] (default)
End of enumeration elements list.
GPCNT0_TO : General Purpose Counter 0 Timeout Flag
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPCNT0_VAL time not reached, or bit has been cleared. (default)
#1 : 1
General Purpose counter has reached the GPCNT0_VAL value
End of enumeration elements list.
GPCNT1_TO : General Purpose Counter 1 Timeout Flag
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPCNT1_VAL time not reached, or bit has been cleared. (default)
#1 : 1
General Purpose counter has reached the GPCNT1_VAL value
End of enumeration elements list.
TX_RPTR : Transmit FIFO Read Pointer
bits : 16 - 17 (2 bit)
access : read-only
TX_CNT : Transmit FIFO Byte Count
bits : 22 - 24 (3 bit)
access : read-only
Enumeration:
#000 : 0
FIFO is emtpy
End of enumeration elements list.
Port Control and Status Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAPD : Auto Power Down Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto power down disabled (default)
#1 : 1
Auto power down enabled
End of enumeration elements list.
SVCC_EN : Vcc Enable for Smart Card
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Smart Card Voltage disabled (default)
#1 : 1
Smart Card Voltage enabled
End of enumeration elements list.
VCCENP : VCC Enable Polarity Control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
VCC_EN is active high. Polarity of SVCC_EN is unchanged.
#1 : 1
VCC_EN is active low. Polarity of SVCC_EN is inverted.
End of enumeration elements list.
SRST : Reset to Smart Card
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Smart Card Reset is asserted (default)
#1 : 1
Smart Card Reset is de-asserted
End of enumeration elements list.
SCEN : Clock Enable for Smart Card
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Smart Card Clock Disabled
#1 : 1
Smart Card Clock Enabled
End of enumeration elements list.
SCSP : Smart Card Clock Stop Polarity
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock is logic 0 when stopped by SCEN
#1 : 1
Clock is logic 1 when stopped by SCEN
End of enumeration elements list.
SPD : Auto Power Down Control
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect (default)
#1 : 1
Start Auto Powerdown or Power Down is in progress
End of enumeration elements list.
SPDIM : Smart Card Presence Detect Interrupt Mask
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
SIM presence detect interrupt is enabled
#1 : 1
SIM presence detect interrupt is masked (default)
End of enumeration elements list.
SPDIF : Smart Card Presence Detect Interrupt Flag
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
No insertion or removal of Smart Card detected on Port (default)
#1 : 1
Insertion or removal of Smart Card detected on Port
End of enumeration elements list.
SPDP : Smart Card Presence Detect Pin Status
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
SIM Presence Detect pin is logic low
#1 : 1
SIM Presence Detectpin is logic high
End of enumeration elements list.
SPDES : SIM Presence Detect Edge Select
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling edge on the pin (default)
#1 : 1
Rising edge on the pin
End of enumeration elements list.
Receive Data Read Buffer
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX_BYTE : Receive Data Byte Read
bits : 0 - 7 (8 bit)
access : read-only
Transmit Data Buffer
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_BYTE : Transmit Data Byte
bits : 0 - 7 (8 bit)
access : write-only
Transmitter Guard ETU Value Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GETU : Transmitter Guard Time Value in ETU
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
#0 : 0
no additional ETUs inserted (default)
#1 : 1
1 additional ETU inserted
#11111110 : 11111110
254 additional ETUs inserted
#11111111 : 11111111
Subtracts one ETU by reducing the number of STOP bits from two to one
End of enumeration elements list.
Character Wait Time Value Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CWT : Character Wait Time Value
bits : 0 - 15 (16 bit)
access : read-write
Block Wait Time Value Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BWT : Block Wait Time Value
bits : 0 - 31 (32 bit)
access : read-write
Parameter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX_FIFO_DEPTH : Receive FIFO Depth
bits : 0 - 7 (8 bit)
access : read-only
TX_FIFO_DEPTH : Transmit FIFO Depth
bits : 8 - 15 (8 bit)
access : read-only
Block Guard Time Value Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BGT : Block Guard Time Value
bits : 0 - 15 (16 bit)
access : read-write
General Purpose Counter 0 Timeout Value Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPCNT0 : General Purpose Counter 0 Timeout Value
bits : 0 - 15 (16 bit)
access : read-write
General Purpose Counter 1 Timeout Value
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPCNT1 : General Purpose Counter 1 Timeout Value
bits : 0 - 15 (16 bit)
access : read-write
Clock Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_PRSC : Clock Prescaler Value
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
#10 : 10
Divide by 2
End of enumeration elements list.
GPCNT1_CLK_SEL : General Purpose Counter 1 Clock Select
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled / Reset (default)
#01 : 01
Card Clock
#10 : 10
Receive Clock
#11 : 11
ETU Clock (transmit clock)
End of enumeration elements list.
GPCNT0_CLK_SEL : General Purpose Counter 0 Clock Select
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 00
Disabled / Reset (default)
#01 : 01
Card Clock
#10 : 10
Receive Clock
#11 : 11
ETU Clock (transmit clock)
End of enumeration elements list.
Baud Rate Divisor Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVISOR_VALUE : Divisor (F/D) Value
bits : 0 - 8 (9 bit)
access : read-write
Enumeration:
#101110100 : 101110100
Divisor value for F = 372 and D = 1 (default)
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.