Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
TSI General Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EOSDMEO : End-of-Scan DMA Transfer Request Enable Only
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not enable the End-of-Scan DMA transfer request only. Depending on ESOR state, either Out-of-Range or End-of-Scan can trigger a DMA transfer request and interrupt.
#1 : 1
Only the End-of-Scan event can trigger a DMA transfer request. The Out-of-Range event only and always triggers an interrupt if TSIIE is set.
End of enumeration elements list.
CURSW : CURSW
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The current source pair are not swapped.
#1 : 1
The current source pair are swapped.
End of enumeration elements list.
EOSF : End of Scan Flag
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Scan not complete.
#1 : 1
Scan complete.
End of enumeration elements list.
SCNIP : Scan In Progress Status
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
No scan in progress.
#1 : 1
Scan in progress.
End of enumeration elements list.
STM : Scan Trigger Mode
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Software trigger scan.
#1 : 1
Hardware trigger scan.
End of enumeration elements list.
STPE : TSI STOP Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
TSI is disabled when MCU goes into low power mode.
#1 : 1
Allows TSI to continue running in all low power modes.
End of enumeration elements list.
TSIIEN : Touch Sensing Input Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
TSI interrupt is disabled.
#1 : 1
TSI interrupt is enabled.
End of enumeration elements list.
TSIEN : Touch Sensing Input Module Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
TSI module disabled.
#1 : 1
TSI module enabled.
End of enumeration elements list.
NSCN : NSCN
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
#00000 : 00000
Once per electrode
#00001 : 00001
Twice per electrode
#00010 : 00010
3 times per electrode
#00011 : 00011
4 times per electrode
#00100 : 00100
5 times per electrode
#00101 : 00101
6 times per electrode
#00110 : 00110
7 times per electrode
#00111 : 00111
8 times per electrode
#01000 : 01000
9 times per electrode
#01001 : 01001
10 times per electrode
#01010 : 01010
11 times per electrode
#01011 : 01011
12 times per electrode
#01100 : 01100
13 times per electrode
#01101 : 01101
14 times per electrode
#01110 : 01110
15 times per electrode
#01111 : 01111
16 times per electrode
#10000 : 10000
17 times per electrode
#10001 : 10001
18 times per electrode
#10010 : 10010
19 times per electrode
#10011 : 10011
20 times per electrode
#10100 : 10100
21 times per electrode
#10101 : 10101
22 times per electrode
#10110 : 10110
23 times per electrode
#10111 : 10111
24 times per electrode
#11000 : 11000
25 times per electrode
#11001 : 11001
26 times per electrode
#11010 : 11010
27 times per electrode
#11011 : 11011
28 times per electrode
#11100 : 11100
29 times per electrode
#11101 : 11101
30 times per electrode
#11110 : 11110
31 times per electrode
#11111 : 11111
32 times per electrode
End of enumeration elements list.
PS : PS
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
#000 : 000
Electrode Oscillator Frequency divided by 1
#001 : 001
Electrode Oscillator Frequency divided by 2
#010 : 010
Electrode Oscillator Frequency divided by 4
#011 : 011
Electrode Oscillator Frequency divided by 8
#100 : 100
Electrode Oscillator Frequency divided by 16
#101 : 101
Electrode Oscillator Frequency divided by 32
#110 : 110
Electrode Oscillator Frequency divided by 64
#111 : 111
Electrode Oscillator Frequency divided by 128
End of enumeration elements list.
EXTCHRG : EXTCHRG
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 000
500 nA.
#001 : 001
1 uA.
#010 : 010
2 uA.
#011 : 011
4 uA.
#100 : 100
8 uA.
#101 : 101
16 uA.
#110 : 110
32 uA.
#111 : 111
64 uA.
End of enumeration elements list.
DVOLT : DVOLT
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
#00 : 00
DV = 1.026 V; VP = 1.328 V; Vm = 0.302 V.
#01 : 01
DV = 0.592 V; VP = 1.111 V; Vm = 0.519 V.
#10 : 10
DV = 0.342 V; VP = 0.986 V; Vm = 0.644 V.
#11 : 11
DV = 0.197 V; VP = 0.914 V; Vm = 0.716 V.
End of enumeration elements list.
REFCHRG : REFCHRG
bits : 21 - 23 (3 bit)
access : read-write
Enumeration:
#000 : 000
500 nA.
#001 : 001
1 uA.
#010 : 010
2 uA.
#011 : 011
4 uA.
#100 : 100
8 uA.
#101 : 101
16 uA.
#110 : 110
32 uA.
#111 : 111
64 uA.
End of enumeration elements list.
MODE : TSI analog modes setup and status bits.
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Set TSI in capacitive sensing(non-noise detection) mode.
#0100 : 0100
Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is disabled.
#1000 : 1000
Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is enabled to work in higher frequencies operations.
#1100 : 1100
Set TSI analog to work in automatic noise detection mode.
End of enumeration elements list.
ESOR : End-of-scan or Out-of-Range Interrupt Selection
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Out-of-range interrupt is allowed.
#1 : 1
End-of-scan interrupt is allowed.
End of enumeration elements list.
OUTRGF : Out of Range Flag.
bits : 31 - 31 (1 bit)
access : read-write
TSI DATA Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSICNT : TSI Conversion Counter Value
bits : 0 - 15 (16 bit)
access : read-only
SWTS : Software Trigger Start
bits : 22 - 22 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect.
#1 : 1
Start a scan to determine which channel is specified by TSI_DATA[TSICH].
End of enumeration elements list.
DMAEN : DMA Transfer Enabled
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt is selected when the interrupt enable bit is set and the corresponding TSI events assert.
#1 : 1
DMA transfer request is selected when the interrupt enable bit is set and the corresponding TSI events assert.
End of enumeration elements list.
TSICH : TSICH
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Channel 0.
#0001 : 0001
Channel 1.
#0010 : 0010
Channel 2.
#0011 : 0011
Channel 3.
#0100 : 0100
Channel 4.
#0101 : 0101
Channel 5.
#0110 : 0110
Channel 6.
#0111 : 0111
Channel 7.
#1000 : 1000
Channel 8.
#1001 : 1001
Channel 9.
#1010 : 1010
Channel 10.
#1011 : 1011
Channel 11.
#1100 : 1100
Channel 12.
#1101 : 1101
Channel 13.
#1110 : 1110
Channel 14.
#1111 : 1111
Channel 15.
End of enumeration elements list.
TSI Threshold Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THRESL : TSI Wakeup Channel Low-threshold
bits : 0 - 15 (16 bit)
access : read-write
THRESH : TSI Wakeup Channel High-threshold
bits : 16 - 31 (16 bit)
access : read-write
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