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PCC

Peripheral Memory Blocks

address_offset : 0x20 Bytes (0x0)
size : 0x1A0 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PCC_LPI2C0

PCC_LPI2C1

PCC_LPUART0

PCC_LPUART1

PCC_FLEXIO0

PCC_PORTM

PCC_CMP1

PCC_DMA1

PCC_SEMA42_1

PCC_DMAMUX1

PCC_MU0_B

PCC_INTMUX1

PCC_TRNG

PCC_TPM0

PCC_TPM1

PCC_LPIT1

PCC_LPTMR1

PCC_LPSPI0

PCC_LPSPI1


PCC_LPI2C0

PCC CLKCFG Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPI2C0 PCC_LPI2C0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#000 : 000

Clock is off (or test clock is enabled).

#001 : 1

OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).

#010 : 2

SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).

#011 : 3

SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).

#110 : 6

SCGPCLK System PLL clock (scg_spll_slow_clk).

End of enumeration elements list.

INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

#0 : 0

Another core is not using this peripheral.

#1 : 1

Another core is using this peripheral. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

PR : Enable
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Peripheral is not present.

#1 : 1

Peripheral is present.

End of enumeration elements list.


PCC_LPI2C1

PCC CLKCFG Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPI2C1 PCC_LPI2C1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#000 : 000

Clock is off (or test clock is enabled).

#001 : 1

OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).

#010 : 2

SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).

#011 : 3

SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).

#110 : 6

SCGPCLK System PLL clock (scg_spll_slow_clk).

End of enumeration elements list.

INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

#0 : 0

Another core is not using this peripheral.

#1 : 1

Another core is using this peripheral. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

PR : Enable
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Peripheral is not present.

#1 : 1

Peripheral is present.

End of enumeration elements list.


PCC_LPUART0

PCC CLKCFG Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPUART0 PCC_LPUART0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#000 : 000

Clock is off (or test clock is enabled).

#001 : 1

OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).

#010 : 2

SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).

#011 : 3

SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).

#110 : 6

SCGPCLK System PLL clock (scg_spll_slow_clk).

End of enumeration elements list.

INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

#0 : 0

Another core is not using this peripheral.

#1 : 1

Another core is using this peripheral. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

PR : Enable
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Peripheral is not present.

#1 : 1

Peripheral is present.

End of enumeration elements list.


PCC_LPUART1

PCC CLKCFG Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPUART1 PCC_LPUART1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#000 : 000

Clock is off (or test clock is enabled).

#001 : 1

OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).

#010 : 2

SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).

#011 : 3

SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).

#110 : 6

SCGPCLK System PLL clock (scg_spll_slow_clk).

End of enumeration elements list.

INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

#0 : 0

Another core is not using this peripheral.

#1 : 1

Another core is using this peripheral. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

PR : Enable
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Peripheral is not present.

#1 : 1

Peripheral is present.

End of enumeration elements list.


PCC_FLEXIO0

PCC CLKCFG Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_FLEXIO0 PCC_FLEXIO0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#000 : 000

Clock is off (or test clock is enabled).

#001 : 1

OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).

#010 : 2

SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).

#011 : 3

SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).

#110 : 6

SCGPCLK System PLL clock (scg_spll_slow_clk).

End of enumeration elements list.

INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

#0 : 0

Another core is not using this peripheral.

#1 : 1

Another core is using this peripheral. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

PR : Enable
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Peripheral is not present.

#1 : 1

Peripheral is present.

End of enumeration elements list.


PCC_PORTM

PCC CLKCFG Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_PORTM PCC_PORTM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

#0 : 0

Another core is not using this peripheral.

#1 : 1

Another core is using this peripheral. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

PR : Enable
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Peripheral is not present.

#1 : 1

Peripheral is present.

End of enumeration elements list.


PCC_CMP1

PCC CLKCFG Register
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_CMP1 PCC_CMP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

#0 : 0

Another core is not using this peripheral.

#1 : 1

Another core is using this peripheral. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

PR : Enable
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Peripheral is not present.

#1 : 1

Peripheral is present.

End of enumeration elements list.


PCC_DMA1

PCC CLKCFG Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_DMA1 PCC_DMA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

#0 : 0

Another core is not using this peripheral.

#1 : 1

Another core is using this peripheral. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

PR : Enable
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Peripheral is not present.

#1 : 1

Peripheral is present.

End of enumeration elements list.


PCC_SEMA42_1

PCC CLKCFG Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_SEMA42_1 PCC_SEMA42_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

#0 : 0

Another core is not using this peripheral.

#1 : 1

Another core is using this peripheral. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

PR : Enable
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Peripheral is not present.

#1 : 1

Peripheral is present.

End of enumeration elements list.


PCC_DMAMUX1

PCC CLKCFG Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_DMAMUX1 PCC_DMAMUX1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

#0 : 0

Another core is not using this peripheral.

#1 : 1

Another core is using this peripheral. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

PR : Enable
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Peripheral is not present.

#1 : 1

Peripheral is present.

End of enumeration elements list.


PCC_MU0_B

PCC CLKCFG Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_MU0_B PCC_MU0_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

#0 : 0

Another core is not using this peripheral.

#1 : 1

Another core is using this peripheral. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

PR : Enable
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Peripheral is not present.

#1 : 1

Peripheral is present.

End of enumeration elements list.


PCC_INTMUX1

PCC CLKCFG Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_INTMUX1 PCC_INTMUX1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

#0 : 0

Another core is not using this peripheral.

#1 : 1

Another core is using this peripheral. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

PR : Enable
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Peripheral is not present.

#1 : 1

Peripheral is present.

End of enumeration elements list.


PCC_TRNG

PCC CLKCFG Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_TRNG PCC_TRNG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

#0 : 0

Another core is not using this peripheral.

#1 : 1

Another core is using this peripheral. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

PR : Enable
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Peripheral is not present.

#1 : 1

Peripheral is present.

End of enumeration elements list.


PCC_TPM0

PCC CLKCFG Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_TPM0 PCC_TPM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#000 : 000

Clock is off (or test clock is enabled).

#001 : 1

OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).

#010 : 2

SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).

#011 : 3

SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).

#110 : 6

SCGPCLK System PLL clock (scg_spll_slow_clk).

End of enumeration elements list.

INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

#0 : 0

Another core is not using this peripheral.

#1 : 1

Another core is using this peripheral. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

PR : Enable
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Peripheral is not present.

#1 : 1

Peripheral is present.

End of enumeration elements list.


PCC_TPM1

PCC CLKCFG Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_TPM1 PCC_TPM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#000 : 000

Clock is off (or test clock is enabled).

#001 : 1

OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).

#010 : 2

SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).

#011 : 3

SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).

#110 : 6

SCGPCLK System PLL clock (scg_spll_slow_clk).

End of enumeration elements list.

INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

#0 : 0

Another core is not using this peripheral.

#1 : 1

Another core is using this peripheral. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

PR : Enable
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Peripheral is not present.

#1 : 1

Peripheral is present.

End of enumeration elements list.


PCC_LPIT1

PCC CLKCFG Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPIT1 PCC_LPIT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#000 : 000

Clock is off (or test clock is enabled).

#001 : 1

OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).

#010 : 2

SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).

#011 : 3

SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).

#110 : 6

SCGPCLK System PLL clock (scg_spll_slow_clk).

End of enumeration elements list.

INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

#0 : 0

Another core is not using this peripheral.

#1 : 1

Another core is using this peripheral. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

PR : Enable
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Peripheral is not present.

#1 : 1

Peripheral is present.

End of enumeration elements list.


PCC_LPTMR1

PCC CLKCFG Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPTMR1 PCC_LPTMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INUSE CGC PR

INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

#0 : 0

Another core is not using this peripheral.

#1 : 1

Another core is using this peripheral. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

PR : Enable
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Peripheral is not present.

#1 : 1

Peripheral is present.

End of enumeration elements list.


PCC_LPSPI0

PCC CLKCFG Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPSPI0 PCC_LPSPI0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#000 : 000

Clock is off (or test clock is enabled).

#001 : 1

OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).

#010 : 2

SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).

#011 : 3

SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).

#110 : 6

SCGPCLK System PLL clock (scg_spll_slow_clk).

End of enumeration elements list.

INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

#0 : 0

Another core is not using this peripheral.

#1 : 1

Another core is using this peripheral. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

PR : Enable
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Peripheral is not present.

#1 : 1

Peripheral is present.

End of enumeration elements list.


PCC_LPSPI1

PCC CLKCFG Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCC_LPSPI1 PCC_LPSPI1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCS INUSE CGC PR

PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#000 : 000

Clock is off (or test clock is enabled).

#001 : 1

OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).

#010 : 2

SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).

#011 : 3

SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).

#110 : 6

SCGPCLK System PLL clock (scg_spll_slow_clk).

End of enumeration elements list.

INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

#0 : 0

Another core is not using this peripheral.

#1 : 1

Another core is using this peripheral. Software cannot modify the existing clocking configuration.

End of enumeration elements list.

CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock disabled

#1 : 1

Clock enabled

End of enumeration elements list.

PR : Enable
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Peripheral is not present.

#1 : 1

Peripheral is present.

End of enumeration elements list.



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