\n
address_offset : 0x20 Bytes (0x0)
size : 0x1A0 byte (0x0)
mem_usage : registers
protection : not protected
PCC CLKCFG Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off (or test clock is enabled).
#001 : 1
OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).
#010 : 2
SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).
#011 : 3
SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).
#110 : 6
SCGPCLK System PLL clock (scg_spll_slow_clk).
End of enumeration elements list.
INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
Another core is not using this peripheral.
#1 : 1
Another core is using this peripheral. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PR : Enable
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC CLKCFG Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off (or test clock is enabled).
#001 : 1
OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).
#010 : 2
SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).
#011 : 3
SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).
#110 : 6
SCGPCLK System PLL clock (scg_spll_slow_clk).
End of enumeration elements list.
INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
Another core is not using this peripheral.
#1 : 1
Another core is using this peripheral. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PR : Enable
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC CLKCFG Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off (or test clock is enabled).
#001 : 1
OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).
#010 : 2
SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).
#011 : 3
SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).
#110 : 6
SCGPCLK System PLL clock (scg_spll_slow_clk).
End of enumeration elements list.
INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
Another core is not using this peripheral.
#1 : 1
Another core is using this peripheral. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PR : Enable
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC CLKCFG Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off (or test clock is enabled).
#001 : 1
OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).
#010 : 2
SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).
#011 : 3
SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).
#110 : 6
SCGPCLK System PLL clock (scg_spll_slow_clk).
End of enumeration elements list.
INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
Another core is not using this peripheral.
#1 : 1
Another core is using this peripheral. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PR : Enable
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC CLKCFG Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off (or test clock is enabled).
#001 : 1
OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).
#010 : 2
SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).
#011 : 3
SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).
#110 : 6
SCGPCLK System PLL clock (scg_spll_slow_clk).
End of enumeration elements list.
INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
Another core is not using this peripheral.
#1 : 1
Another core is using this peripheral. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PR : Enable
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC CLKCFG Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
Another core is not using this peripheral.
#1 : 1
Another core is using this peripheral. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PR : Enable
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC CLKCFG Register
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
Another core is not using this peripheral.
#1 : 1
Another core is using this peripheral. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PR : Enable
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC CLKCFG Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
Another core is not using this peripheral.
#1 : 1
Another core is using this peripheral. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PR : Enable
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC CLKCFG Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
Another core is not using this peripheral.
#1 : 1
Another core is using this peripheral. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PR : Enable
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC CLKCFG Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
Another core is not using this peripheral.
#1 : 1
Another core is using this peripheral. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PR : Enable
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC CLKCFG Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
Another core is not using this peripheral.
#1 : 1
Another core is using this peripheral. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PR : Enable
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC CLKCFG Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
Another core is not using this peripheral.
#1 : 1
Another core is using this peripheral. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PR : Enable
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC CLKCFG Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
Another core is not using this peripheral.
#1 : 1
Another core is using this peripheral. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PR : Enable
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC CLKCFG Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off (or test clock is enabled).
#001 : 1
OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).
#010 : 2
SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).
#011 : 3
SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).
#110 : 6
SCGPCLK System PLL clock (scg_spll_slow_clk).
End of enumeration elements list.
INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
Another core is not using this peripheral.
#1 : 1
Another core is using this peripheral. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PR : Enable
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC CLKCFG Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off (or test clock is enabled).
#001 : 1
OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).
#010 : 2
SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).
#011 : 3
SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).
#110 : 6
SCGPCLK System PLL clock (scg_spll_slow_clk).
End of enumeration elements list.
INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
Another core is not using this peripheral.
#1 : 1
Another core is using this peripheral. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PR : Enable
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC CLKCFG Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off (or test clock is enabled).
#001 : 1
OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).
#010 : 2
SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).
#011 : 3
SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).
#110 : 6
SCGPCLK System PLL clock (scg_spll_slow_clk).
End of enumeration elements list.
INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
Another core is not using this peripheral.
#1 : 1
Another core is using this peripheral. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PR : Enable
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC CLKCFG Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
Another core is not using this peripheral.
#1 : 1
Another core is using this peripheral. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PR : Enable
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC CLKCFG Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off (or test clock is enabled).
#001 : 1
OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).
#010 : 2
SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).
#011 : 3
SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).
#110 : 6
SCGPCLK System PLL clock (scg_spll_slow_clk).
End of enumeration elements list.
INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
Another core is not using this peripheral.
#1 : 1
Another core is using this peripheral. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PR : Enable
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
PCC CLKCFG Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCS : Peripheral Clock Source Select
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock is off (or test clock is enabled).
#001 : 1
OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).
#010 : 2
SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).
#011 : 3
SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).
#110 : 6
SCGPCLK System PLL clock (scg_spll_slow_clk).
End of enumeration elements list.
INUSE : Clock Gate Control
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
Another core is not using this peripheral.
#1 : 1
Another core is using this peripheral. Software cannot modify the existing clocking configuration.
End of enumeration elements list.
CGC : Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PR : Enable
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Peripheral is not present.
#1 : 1
Peripheral is present.
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.