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ASMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SRS

STOPCTRL

PMSTAT

PMPROT

PMCTRL


SRS

System Reset Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SRS SRS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAKEUP WDOG1 RES POR LOCKUP SW SACKERR

WAKEUP : Low Leakage Wakeup Reset
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by LLWU module wakeup source

#1 : 1

Reset caused by LLWU module wakeup source

End of enumeration elements list.

WDOG1 : Watchdog
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by watchdog timeout

#1 : 1

Reset caused by watchdog timeout

End of enumeration elements list.

RES : Chip Reset not POR
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Chip Reset did not occur

#1 : 1

Chip Reset caused by a source other than POR occured

End of enumeration elements list.

POR : Power-On Reset
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by POR

#1 : 1

Reset caused by POR

End of enumeration elements list.

LOCKUP : Core 1 Lockup
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by core LOCKUP event

#1 : 1

Reset caused by core LOCKUP event

End of enumeration elements list.

SW : Software
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by software setting of SYSRESETREQ bit

#1 : 1

Reset caused by software setting of SYSRESETREQ bit

End of enumeration elements list.

SACKERR : Stop Mode Acknowledge Error Reset
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset not caused by peripheral failure to acknowledge attempt to enter stop mode

#1 : 1

Reset caused by peripheral failure to acknowledge attempt to enter stop mode

End of enumeration elements list.


STOPCTRL

Stop Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STOPCTRL STOPCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSTOPO

PSTOPO : Partial Stop Option
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 00

STOP - Normal Stop mode

#01 : 01

PSTOP1 - Partial Stop with both system and bus clocks disabled

#10 : 10

PSTOP2 - Partial Stop with system clock disabled and bus clock enabled

End of enumeration elements list.


PMSTAT

Power Mode Status register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PMSTAT PMSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMSTAT

PMSTAT : Power Mode Status
bits : 0 - 7 (8 bit)
access : read-only


PMPROT

Power Mode Protection register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMPROT PMPROT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVLLS ALLS AVLP AHSRUN

AVLLS : Allow Very-Low-Leakage Stop Mode
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Any VLLSx mode is not allowed

#1 : 1

Any VLLSx mode is allowed

End of enumeration elements list.

ALLS : Allow Low-Leakage Stop Mode
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Any LLSx mode is not allowed

#1 : 1

Any LLSx mode is allowed

End of enumeration elements list.

AVLP : Allow Very-Low-Power Modes
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

VLPR, VLPW, and VLPS are not allowed.

#1 : 1

VLPR, VLPW, and VLPS are allowed.

End of enumeration elements list.

AHSRUN : Allow High Speed Run mode
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

HSRUN is not allowed

#1 : 1

HSRUN is allowed

End of enumeration elements list.


PMCTRL

Power Mode Control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMCTRL PMCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOPM RUNM

STOPM : Stop Mode Control
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

Normal Stop (STOP)

#010 : 010

Very-Low-Power Stop (VLPS)

#011 : 011

Low-Leakage Stop (LLSx)

#100 : 100

Very-Low-Leakage Stop (VLLSx)

#110 : 110

Reseved

End of enumeration elements list.

RUNM : Run Mode Control
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

#00 : 00

Normal Run mode (RUN)

#10 : 10

Very-Low-Power Run mode (VLPR)

#11 : 11

High Speed Run mode (HSRUN)

End of enumeration elements list.



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