Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x88 byte (0x0)
mem_usage : registers
protection : not protected
Version ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FEATURE : Feature Identification Number
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
#1 : 1
Standard feature set.
#11 : 11
Standard feature set with Filter and Combine registers implemented.
#111 : 111
Standard feature set with Filter, Combine and Quadrature registers implemented.
End of enumeration elements list.
MINOR : Minor Version Number
bits : 16 - 23 (8 bit)
access : read-only
MAJOR : Major Version Number
bits : 24 - 31 (8 bit)
access : read-only
Status and Control
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PS : Prescale Factor Selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 000
Divide by 1
#001 : 001
Divide by 2
#010 : 010
Divide by 4
#011 : 011
Divide by 8
#100 : 100
Divide by 16
#101 : 101
Divide by 32
#110 : 110
Divide by 64
#111 : 111
Divide by 128
End of enumeration elements list.
CMOD : Clock Mode Selection
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 00
TPM counter is disabled
#01 : 01
TPM counter increments on every TPM counter clock
#10 : 10
TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock
#11 : 11
TPM counter increments on rising edge of the selected external input trigger.
End of enumeration elements list.
CPWMS : Center-Aligned PWM Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
TPM counter operates in up counting mode.
#1 : 1
TPM counter operates in up-down counting mode.
End of enumeration elements list.
TOIE : Timer Overflow Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable TOF interrupts. Use software polling or DMA request.
#1 : 1
Enable TOF interrupts. An interrupt is generated when TOF equals one.
End of enumeration elements list.
TOF : Timer Overflow Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
TPM counter has not overflowed.
#1 : 1
TPM counter has overflowed.
End of enumeration elements list.
DMA : DMA Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disables DMA transfers.
#1 : 1
Enables DMA transfers.
End of enumeration elements list.
Counter
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Counter value
bits : 0 - 15 (16 bit)
access : read-write
Modulo
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD : Modulo value
bits : 0 - 15 (16 bit)
access : read-write
Capture and Compare Status
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0F : Channel 0 Flag
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
CH1F : Channel 1 Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
CH2F : Channel 2 Flag
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
CH3F : Channel 3 Flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
CH4F : Channel 4 Flag
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
CH5F : Channel 5 Flag
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
TOF : Timer Overflow Flag
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
TPM counter has not overflowed.
#1 : 1
TPM counter has overflowed.
End of enumeration elements list.
Parameter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHAN : Channel Count
bits : 0 - 7 (8 bit)
access : read-only
TRIG : Trigger Count
bits : 8 - 15 (8 bit)
access : read-only
WIDTH : Counter Width
bits : 16 - 23 (8 bit)
access : read-only
Channel (n) Status and Control
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DMA transfers.
#1 : 1
Enable DMA transfers.
End of enumeration elements list.
ELSA : Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel interrupts.
#1 : 1
Enable channel interrupts.
End of enumeration elements list.
CHF : Channel Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Combine Channel Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMBINE0 : Combine Channels 0 and 1
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channels 0 and 1 are independent.
#1 : 1
Channels 0 and 1 are combined.
End of enumeration elements list.
COMSWAP0 : Combine Channel 0 and 1 Swap
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Even channel is used for input capture and 1st compare.
#1 : 1
Odd channel is used for input capture and 1st compare.
End of enumeration elements list.
COMBINE1 : Combine Channels 2 and 3
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channels 2 and 3 are independent.
#1 : 1
Channels 2 and 3 are combined.
End of enumeration elements list.
COMSWAP1 : Combine Channels 2 and 3 Swap
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Even channel is used for input capture and 1st compare.
#1 : 1
Odd channel is used for input capture and 1st compare.
End of enumeration elements list.
COMBINE2 : Combine Channels 4 and 5
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channels 4 and 5 are independent.
#1 : 1
Channels 4 and 5 are combined.
End of enumeration elements list.
COMSWAP2 : Combine Channels 4 and 5 Swap
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Even channel is used for input capture and 1st compare.
#1 : 1
Odd channel is used for input capture and 1st compare.
End of enumeration elements list.
Channel (n) Status and Control
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DMA transfers.
#1 : 1
Enable DMA transfers.
End of enumeration elements list.
ELSA : Edge or Level Select
bits : 2 - 2 (1 bit)
access : read-write
ELSB : Edge or Level Select
bits : 3 - 3 (1 bit)
access : read-write
MSA : Channel Mode Select
bits : 4 - 4 (1 bit)
access : read-write
MSB : Channel Mode Select
bits : 5 - 5 (1 bit)
access : read-write
CHIE : Channel Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable channel interrupts.
#1 : 1
Enable channel interrupts.
End of enumeration elements list.
CHF : Channel Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No channel event has occurred.
#1 : 1
A channel event has occurred.
End of enumeration elements list.
Channel Trigger
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIG0 : Channel 0 Trigger
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
The input trigger is used for input capture and modulates output (for output compare and PWM).
End of enumeration elements list.
TRIG1 : Channel 1 Trigger
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
The input trigger is used for input capture and modulates output (for output compare and PWM).
End of enumeration elements list.
TRIG2 : Channel 2 Trigger
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
The input trigger is used for input capture and modulates output (for output compare and PWM).
End of enumeration elements list.
TRIG3 : Channel 3 Trigger
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
The input trigger is used for input capture and modulates output (for output compare and PWM).
End of enumeration elements list.
TRIG4 : Channel 4 Trigger
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
The input trigger is used for input capture and modulates output (for output compare and PWM).
End of enumeration elements list.
TRIG5 : Channel 5 Trigger
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
#1 : 1
The input trigger is used for input capture and modulates output (for output compare and PWM).
End of enumeration elements list.
Channel Polarity
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POL0 : Channel 0 Polarity
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
POL1 : Channel 1 Polarity
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
POL2 : Channel 2 Polarity
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
POL3 : Channel 3 Polarity
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
POL4 : Channel 4 Polarity
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
POL5 : Channel 5 Polarity
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The channel polarity is active high.
#1 : 1
The channel polarity is active low.
End of enumeration elements list.
Channel (n) Value
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Channel Value
bits : 0 - 15 (16 bit)
access : read-write
Filter Control
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0FVAL : Channel 0 Filter Value
bits : 0 - 3 (4 bit)
access : read-write
CH1FVAL : Channel 1 Filter Value
bits : 4 - 7 (4 bit)
access : read-write
CH2FVAL : Channel 2 Filter Value
bits : 8 - 11 (4 bit)
access : read-write
CH3FVAL : Channel 3 Filter Value
bits : 12 - 15 (4 bit)
access : read-write
CH4FVAL : Channel 4 Filter Value
bits : 16 - 19 (4 bit)
access : read-write
CH5FVAL : Channel 5 Filter Value
bits : 20 - 23 (4 bit)
access : read-write
TPM Global Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RST : Software Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Module is not reset.
#1 : 1
Module is reset.
End of enumeration elements list.
Quadrature Decoder Control and Status
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QUADEN : Enables the quadrature decoder mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Quadrature decoder mode is disabled.
#1 : 1
Quadrature decoder mode is enabled.
End of enumeration elements list.
TOFDIR : Indicates if the TOF bit was set on the top or the bottom of counting.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register).
#1 : 1
TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero).
End of enumeration elements list.
QUADIR : Counter Direction in Quadrature Decode Mode
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Counter direction is decreasing (counter decrement).
#1 : 1
Counter direction is increasing (counter increment).
End of enumeration elements list.
QUADMODE : Quadrature Decoder Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Phase encoding mode.
#1 : 1
Count and direction encoding mode.
End of enumeration elements list.
Configuration
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOZEEN : Doze Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal TPM counter continues in Doze mode.
#1 : 1
Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.
End of enumeration elements list.
DBGMODE : Debug Mode
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored.
#11 : 11
TPM counter continues in debug mode.
End of enumeration elements list.
GTBSYNC : Global Time Base Synchronization
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Global timebase synchronization disabled.
#1 : 1
Global timebase synchronization enabled.
End of enumeration elements list.
GTBEEN : Global time base enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
All channels use the internally generated TPM counter as their timebase
#1 : 1
All channels use an externally generated global timebase as their timebase
End of enumeration elements list.
CSOT : Counter Start on Trigger
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
TPM counter starts to increment immediately, once it is enabled.
#1 : 1
TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.
End of enumeration elements list.
CSOO : Counter Stop On Overflow
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
TPM counter continues incrementing or decrementing after overflow
#1 : 1
TPM counter stops incrementing or decrementing after overflow.
End of enumeration elements list.
CROT : Counter Reload On Trigger
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Counter is not reloaded due to a rising edge on the selected input trigger
#1 : 1
Counter is reloaded when a rising edge is detected on the selected input trigger
End of enumeration elements list.
CPOT : Counter Pause On Trigger
bits : 19 - 19 (1 bit)
access : read-write
TRGPOL : Trigger Polarity
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trigger is active high.
#1 : 1
Trigger is active low.
End of enumeration elements list.
TRGSRC : Trigger Source
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trigger source selected by TRGSEL is external.
#1 : 1
Trigger source selected by TRGSEL is internal (channel pin input capture).
End of enumeration elements list.
TRGSEL : Trigger Select
bits : 24 - 25 (2 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.