\n

PORT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xA4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x0 Bytes (0x0)
size : 0xCC byte (0x0)
mem_usage : registers
protection : not protected

Registers

PCR0

PCR4

PCR5

PCR6

PCR7

PCR8

PCR9

PCR10

PCR11

PCR12

PCR13

PCR14

PCR15

PCR1

PCR16

PCR17

PCR18

PCR19

PCR20

PCR21

PCR22

PCR23

PCR24

PCR25

PCR26

PCR27

PCR28

PCR29

PCR30

PCR31

PCR2

GPCLR

GPCHR

GICLR

GICHR

ISFR

PCR3

DFER

DFCR

DFWR


PCR0

Pin Control Register n
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR0 PCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR4

Pin Control Register n
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR4 PCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR5

Pin Control Register n
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR5 PCR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR6

Pin Control Register n
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR6 PCR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR7

Pin Control Register n
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR7 PCR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR8

Pin Control Register n
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR8 PCR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR9

Pin Control Register n
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR9 PCR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR10

Pin Control Register n
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR10 PCR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR11

Pin Control Register n
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR11 PCR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR12

Pin Control Register n
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR12 PCR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR13

Pin Control Register n
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR13 PCR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR14

Pin Control Register n
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR14 PCR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR15

Pin Control Register n
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR15 PCR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR1

Pin Control Register n
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR1 PCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR16

Pin Control Register n
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR16 PCR16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR17

Pin Control Register n
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR17 PCR17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR18

Pin Control Register n
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR18 PCR18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR19

Pin Control Register n
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR19 PCR19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR20

Pin Control Register n
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR20 PCR20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR21

Pin Control Register n
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR21 PCR21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR22

Pin Control Register n
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR22 PCR22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR23

Pin Control Register n
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR23 PCR23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR24

Pin Control Register n
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR24 PCR24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR25

Pin Control Register n
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR25 PCR25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR26

Pin Control Register n
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR26 PCR26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR27

Pin Control Register n
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR27 PCR27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR28

Pin Control Register n
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR28 PCR28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR29

Pin Control Register n
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR29 PCR29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR30

Pin Control Register n
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR30 PCR30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR31

Pin Control Register n
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR31 PCR31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR2

Pin Control Register n
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR2 PCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


GPCLR

Global Pin Control Low Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GPCLR GPCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPWD GPWE GPWE0 GPWE1 GPWE2 GPWE3 GPWE4 GPWE5 GPWE6 GPWE7 GPWE8 GPWE9 GPWE10 GPWE11 GPWE12 GPWE13 GPWE14 GPWE15

GPWD : Global Pin Write Data
bits : 0 - 15 (16 bit)
access : write-only

GPWE : Global Pin Write Enable
bits : 16 - 31 (16 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE0 : Global Pin Write Enable
bits : 16 - 16 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE1 : Global Pin Write Enable
bits : 17 - 17 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE2 : Global Pin Write Enable
bits : 18 - 18 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE3 : Global Pin Write Enable
bits : 19 - 19 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE4 : Global Pin Write Enable
bits : 20 - 20 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE5 : Global Pin Write Enable
bits : 21 - 21 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE6 : Global Pin Write Enable
bits : 22 - 22 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE7 : Global Pin Write Enable
bits : 23 - 23 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE8 : Global Pin Write Enable
bits : 24 - 24 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE9 : Global Pin Write Enable
bits : 25 - 25 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE10 : Global Pin Write Enable
bits : 26 - 26 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE11 : Global Pin Write Enable
bits : 27 - 27 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE12 : Global Pin Write Enable
bits : 28 - 28 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE13 : Global Pin Write Enable
bits : 29 - 29 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE14 : Global Pin Write Enable
bits : 30 - 30 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE15 : Global Pin Write Enable
bits : 31 - 31 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.


GPCHR

Global Pin Control High Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GPCHR GPCHR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPWD GPWE GPWE0 GPWE1 GPWE2 GPWE3 GPWE4 GPWE5 GPWE6 GPWE7 GPWE8 GPWE9 GPWE10 GPWE11 GPWE12 GPWE13 GPWE14 GPWE15

GPWD : Global Pin Write Data
bits : 0 - 15 (16 bit)
access : write-only

GPWE : Global Pin Write Enable
bits : 16 - 31 (16 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE0 : Global Pin Write Enable
bits : 16 - 16 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE1 : Global Pin Write Enable
bits : 17 - 17 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE2 : Global Pin Write Enable
bits : 18 - 18 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE3 : Global Pin Write Enable
bits : 19 - 19 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE4 : Global Pin Write Enable
bits : 20 - 20 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE5 : Global Pin Write Enable
bits : 21 - 21 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE6 : Global Pin Write Enable
bits : 22 - 22 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE7 : Global Pin Write Enable
bits : 23 - 23 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE8 : Global Pin Write Enable
bits : 24 - 24 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE9 : Global Pin Write Enable
bits : 25 - 25 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE10 : Global Pin Write Enable
bits : 26 - 26 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE11 : Global Pin Write Enable
bits : 27 - 27 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE12 : Global Pin Write Enable
bits : 28 - 28 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE13 : Global Pin Write Enable
bits : 29 - 29 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE14 : Global Pin Write Enable
bits : 30 - 30 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GPWE15 : Global Pin Write Enable
bits : 31 - 31 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.


GICLR

Global Interrupt Control Low Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GICLR GICLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GIWE GIWE0 GIWE1 GIWE2 GIWE3 GIWE4 GIWE5 GIWE6 GIWE7 GIWE8 GIWE9 GIWE10 GIWE11 GIWE12 GIWE13 GIWE14 GIWE15 GIWD

GIWE : Global Interrupt Write Enable
bits : 0 - 15 (16 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE0 : Global Interrupt Write Enable
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE1 : Global Interrupt Write Enable
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE2 : Global Interrupt Write Enable
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE3 : Global Interrupt Write Enable
bits : 3 - 3 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE4 : Global Interrupt Write Enable
bits : 4 - 4 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE5 : Global Interrupt Write Enable
bits : 5 - 5 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE6 : Global Interrupt Write Enable
bits : 6 - 6 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE7 : Global Interrupt Write Enable
bits : 7 - 7 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE8 : Global Interrupt Write Enable
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE9 : Global Interrupt Write Enable
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE10 : Global Interrupt Write Enable
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE11 : Global Interrupt Write Enable
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE12 : Global Interrupt Write Enable
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE13 : Global Interrupt Write Enable
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE14 : Global Interrupt Write Enable
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE15 : Global Interrupt Write Enable
bits : 15 - 15 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWD : Global Interrupt Write Data
bits : 16 - 31 (16 bit)
access : write-only


GICHR

Global Interrupt Control High Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GICHR GICHR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GIWE GIWE0 GIWE1 GIWE2 GIWE3 GIWE4 GIWE5 GIWE6 GIWE7 GIWE8 GIWE9 GIWE10 GIWE11 GIWE12 GIWE13 GIWE14 GIWE15 GIWD

GIWE : Global Interrupt Write Enable
bits : 0 - 15 (16 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE0 : Global Interrupt Write Enable
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE1 : Global Interrupt Write Enable
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE2 : Global Interrupt Write Enable
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE3 : Global Interrupt Write Enable
bits : 3 - 3 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE4 : Global Interrupt Write Enable
bits : 4 - 4 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE5 : Global Interrupt Write Enable
bits : 5 - 5 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE6 : Global Interrupt Write Enable
bits : 6 - 6 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE7 : Global Interrupt Write Enable
bits : 7 - 7 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE8 : Global Interrupt Write Enable
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE9 : Global Interrupt Write Enable
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE10 : Global Interrupt Write Enable
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE11 : Global Interrupt Write Enable
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE12 : Global Interrupt Write Enable
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE13 : Global Interrupt Write Enable
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE14 : Global Interrupt Write Enable
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWE15 : Global Interrupt Write Enable
bits : 15 - 15 (1 bit)
access : write-only

Enumeration:

#0 : 0

Corresponding Pin Control Register is not updated with the value in GPWD.

#1 : 1

Corresponding Pin Control Register is updated with the value in GPWD.

End of enumeration elements list.

GIWD : Global Interrupt Write Data
bits : 16 - 31 (16 bit)
access : write-only


ISFR

Interrupt Status Flag Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISFR ISFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISF ISF0 ISF1 ISF2 ISF3 ISF4 ISF5 ISF6 ISF7 ISF8 ISF9 ISF10 ISF11 ISF12 ISF13 ISF14 ISF15 ISF16 ISF17 ISF18 ISF19 ISF20 ISF21 ISF22 ISF23 ISF24 ISF25 ISF26 ISF27 ISF28 ISF29 ISF30 ISF31

ISF : Interrupt Status Flag
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF0 : Interrupt Status Flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF1 : Interrupt Status Flag
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF2 : Interrupt Status Flag
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF3 : Interrupt Status Flag
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF4 : Interrupt Status Flag
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF5 : Interrupt Status Flag
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF6 : Interrupt Status Flag
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF7 : Interrupt Status Flag
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF8 : Interrupt Status Flag
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF9 : Interrupt Status Flag
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF10 : Interrupt Status Flag
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF11 : Interrupt Status Flag
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF12 : Interrupt Status Flag
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF13 : Interrupt Status Flag
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF14 : Interrupt Status Flag
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF15 : Interrupt Status Flag
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF16 : Interrupt Status Flag
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF17 : Interrupt Status Flag
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF18 : Interrupt Status Flag
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF19 : Interrupt Status Flag
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF20 : Interrupt Status Flag
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF21 : Interrupt Status Flag
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF22 : Interrupt Status Flag
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF23 : Interrupt Status Flag
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF24 : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF25 : Interrupt Status Flag
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF26 : Interrupt Status Flag
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF27 : Interrupt Status Flag
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF28 : Interrupt Status Flag
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF29 : Interrupt Status Flag
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF30 : Interrupt Status Flag
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.

ISF31 : Interrupt Status Flag
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


PCR3

Pin Control Register n
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR3 PCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS PE SRE PFE ODE DSE MUX LK IRQC ISF

PS : Pull Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.

#1 : 1

Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

End of enumeration elements list.

PE : Pull Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal pullup or pulldown resistor is not enabled on the corresponding pin.

#1 : 1

Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.

SRE : Slew Rate Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

#1 : 1

Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

PFE : Passive Filter Enable
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Passive input filter is disabled on the corresponding pin.

#1 : 1

Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

End of enumeration elements list.

ODE : Open Drain Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Open drain output is disabled on the corresponding pin.

#1 : 1

Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

End of enumeration elements list.

DSE : Drive Strength Enable
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.

#1 : 1

High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

End of enumeration elements list.

MUX : Pin Mux Control
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 000

Pin disabled (Alternative 0) (analog).

#001 : 001

Alternative 1 (GPIO).

#010 : 010

Alternative 2 (chip-specific).

#011 : 011

Alternative 3 (chip-specific).

#100 : 100

Alternative 4 (chip-specific).

#101 : 101

Alternative 5 (chip-specific).

#110 : 110

Alternative 6 (chip-specific).

#111 : 111

Alternative 7 (chip-specific).

End of enumeration elements list.

LK : Lock Register
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pin Control Register fields [15:0] are not locked.

#1 : 1

Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

End of enumeration elements list.

IRQC : Interrupt Configuration
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0000

Interrupt Status Flag (ISF) is disabled.

#0001 : 0001

ISF flag and DMA request on rising edge.

#0010 : 0010

ISF flag and DMA request on falling edge.

#0011 : 0011

ISF flag and DMA request on either edge.

#0101 : 0101

Flag sets on rising edge.

#0110 : 0110

Flag sets on falling edge.

#0111 : 0111

Flag sets on either edge.

#1000 : 1000

ISF flag and Interrupt when logic 0.

#1001 : 1001

ISF flag and Interrupt on rising-edge.

#1010 : 1010

ISF flag and Interrupt on falling-edge.

#1011 : 1011

ISF flag and Interrupt on either edge.

#1100 : 1100

ISF flag and Interrupt when logic 1.

#1101 : 1101

Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux, which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins are configured, then they are ORed together to create the trigger)]

#1110 : 1110

Enable active low trigger output, flag is disabled.

End of enumeration elements list.

ISF : Interrupt Status Flag
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configured interrupt is not detected.

#1 : 1

Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

End of enumeration elements list.


DFER

Digital Filter Enable Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFER DFER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFE

DFE : Digital Filter Enable
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

#0 : 0

Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.

#1 : 1

Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.

End of enumeration elements list.


DFCR

Digital Filter Clock Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFCR DFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CS

CS : Clock Source
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Digital filters are clocked by the bus clock.

#1 : 1

Digital filters are clocked by the LPO clock.

End of enumeration elements list.


DFWR

Digital Filter Width Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFWR DFWR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILT

FILT : Filter Length
bits : 0 - 4 (5 bit)
access : read-write



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