\n
address_offset : 0x0 Bytes (0x0)
size : 0x60C byte (0x0)
mem_usage : registers
protection : not protected
Version ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : SCG Version Number
bits : 0 - 31 (32 bit)
access : read-only
Clock Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DIVSLOW : Slow Clock Divide Ratio
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
#0000 : 0000
Divide-by-1
#0001 : 0001
Divide-by-2
#0010 : 0010
Divide-by-3
#0011 : 0011
Divide-by-4
#0100 : 0100
Divide-by-5
#0101 : 0101
Divide-by-6
#0110 : 0110
Divide-by-7
#0111 : 0111
Divide-by-8
#1000 : 1000
Divide-by-9
#1001 : 1001
Divide-by-10
#1010 : 1010
Divide-by-11
#1011 : 1011
Divide-by-12
#1100 : 1100
Divide-by-13
#1101 : 1101
Divide-by-14
#1110 : 1110
Divide-by-15
#1111 : 1111
Divide-by-16
End of enumeration elements list.
DIVCORE : Core Clock Divide Ratio
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
#0000 : 0000
Divide-by-1
#0001 : 0001
Divide-by-2
#0010 : 0010
Divide-by-3
#0011 : 0011
Divide-by-4
#0100 : 0100
Divide-by-5
#0101 : 0101
Divide-by-6
#0110 : 0110
Divide-by-7
#0111 : 0111
Divide-by-8
#1000 : 1000
Divide-by-9
#1001 : 1001
Divide-by-10
#1010 : 1010
Divide-by-11
#1011 : 1011
Divide-by-12
#1100 : 1100
Divide-by-13
#1101 : 1101
Divide-by-14
#1110 : 1110
Divide-by-15
#1111 : 1111
Divide-by-16
End of enumeration elements list.
SCS : System Clock Source
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
#0001 : 0001
System OSC (SOSC_CLK)
#0010 : 0010
Slow IRC (SIRC_CLK)
#0011 : 0011
Fast IRC (FIRC_CLK)
#0110 : 0110
System PLL (SPLL_CLK)
End of enumeration elements list.
System OSC Control Status Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOSCEN : System OSC Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
System OSC is disabled
#1 : 1
System OSC is enabled
End of enumeration elements list.
SOSCSTEN : System OSC Stop Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
System OSC is disabled in Stop modes
#1 : 1
System OSC is enabled in Stop modes if SOSCEN=1. In VLLS0, system oscillator is disabled even if SOSCSTEN=1 and SOSCEN=1.
End of enumeration elements list.
SOSCLPEN : System OSC Low Power Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
System OSC is disabled in VLP modes
#1 : 1
System OSC is enabled in VLP modes
End of enumeration elements list.
SOSCERCLKEN : System OSC 3V ERCLK Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
System OSC 3V ERCLK output clock is disabled.
#1 : 1
System OSC 3V ERCLK output clock is enabled when SYSOSC is enabled.
End of enumeration elements list.
SOSCCM : System OSC Clock Monitor
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
System OSC Clock Monitor is disabled
#1 : 1
System OSC Clock Monitor is enabled
End of enumeration elements list.
SOSCCMRE : System OSC Clock Monitor Reset Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Monitor generates interrupt when error detected
#1 : 1
Clock Monitor generates reset when error detected
End of enumeration elements list.
LK : Lock Register
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
This Control Status Register can be written.
#1 : 1
This Control Status Register cannot be written.
End of enumeration elements list.
SOSCVLD : System OSC Valid
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
System OSC is not enabled or clock is not valid
#1 : 1
System OSC is enabled and output clock is valid
End of enumeration elements list.
SOSCSEL : System OSC Selected
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
System OSC is not the system clock source
#1 : 1
System OSC is the system clock source
End of enumeration elements list.
SOSCERR : System OSC Clock Error
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
System OSC Clock Monitor is disabled or has not detected an error
#1 : 1
System OSC Clock Monitor is enabled and detected an error
End of enumeration elements list.
System OSC Divide Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOSCDIV1 : System OSC Clock Divide 1
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 000
Output disabled
#001 : 001
Divide by 1
#010 : 010
Divide by 2
#011 : 011
Divide by 4
#100 : 100
Divide by 8
#101 : 101
Divide by 16
#110 : 110
Divide by 32
#111 : 111
Divide by 64
End of enumeration elements list.
SOSCDIV2 : System OSC Clock Divide 2
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Output disabled
#001 : 001
Divide by 1
#010 : 010
Divide by 2
#011 : 011
Divide by 4
#100 : 100
Divide by 8
#101 : 101
Divide by 16
#110 : 110
Divide by 32
#111 : 111
Divide by 64
End of enumeration elements list.
SOSCDIV3 : System OSC Clock Divide 3
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 000
Output disabled
#001 : 001
Divide by 1
#010 : 010
Divide by 2
#011 : 011
Divide by 4
#100 : 100
Divide by 8
#101 : 101
Divide by 16
#110 : 110
Divide by 32
#111 : 111
Divide by 64
End of enumeration elements list.
System Oscillator Configuration Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EREFS : External Reference Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
External reference clock selected
#1 : 1
Internal crystal oscillator of OSC requested. In VLLS0, the internal oscillator of OSC is disabled even if SOSCEN=1 and SOSCSTEN=1.
End of enumeration elements list.
HGO : High Gain Oscillator Select
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configure crystal oscillator for low-power operation
#1 : 1
Configure crystal oscillator for high-gain operation
End of enumeration elements list.
RANGE : System OSC Range Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#01 : 01
Low frequency range selected for the crystal oscillator of 32 kHz to 40 kHz.
#10 : 10
Medium frequency range selected for the crytstal oscillator of 1 Mhz to 8 Mhz.
#11 : 11
High frequency range selected for the crystal oscillator of 8 Mhz to 32 Mhz.
End of enumeration elements list.
SC16P : Oscillator 16 pF Capacitor Load
bits : 8 - 8 (1 bit)
access : read-write
SC8P : Oscillator 8 pF Capacitor Load Configure
bits : 9 - 9 (1 bit)
access : read-write
SC4P : Oscillator 4 pF Capacitor Load
bits : 10 - 10 (1 bit)
access : read-write
SC2P : Oscillator 2 pF Capacitor Load
bits : 11 - 11 (1 bit)
access : read-write
Run Clock Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVSLOW : Slow Clock Divide Ratio
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide-by-1
#0001 : 0001
Divide-by-2
#0010 : 0010
Divide-by-3
#0011 : 0011
Divide-by-4
#0100 : 0100
Divide-by-5
#0101 : 0101
Divide-by-6
#0110 : 0110
Divide-by-7
#0111 : 0111
Divide-by-8
#1000 : 1000
Divide-by-9
#1001 : 1001
Divide-by-10
#1010 : 1010
Divide-by-11
#1011 : 1011
Divide-by-12
#1100 : 1100
Divide-by-13
#1101 : 1101
Divide-by-14
#1110 : 1110
Divide-by-15
#1111 : 1111
Divide-by-16
End of enumeration elements list.
DIVCORE : Core Clock Divide Ratio
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide-by-1
#0001 : 0001
Divide-by-2
#0010 : 0010
Divide-by-3
#0011 : 0011
Divide-by-4
#0100 : 0100
Divide-by-5
#0101 : 0101
Divide-by-6
#0110 : 0110
Divide-by-7
#0111 : 0111
Divide-by-8
#1000 : 1000
Divide-by-9
#1001 : 1001
Divide-by-10
#1010 : 1010
Divide-by-11
#1011 : 1011
Divide-by-12
#1100 : 1100
Divide-by-13
#1101 : 1101
Divide-by-14
#1110 : 1110
Divide-by-15
#1111 : 1111
Divide-by-16
End of enumeration elements list.
SCS : System Clock Source
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0001 : 0001
System OSC (SOSC_CLK)
#0010 : 0010
Slow IRC (SIRC_CLK)
#0011 : 0011
Fast IRC (FIRC_CLK)
#0110 : 0110
System PLL (SPLL_CLK)
End of enumeration elements list.
VLPR Clock Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVSLOW : Slow Clock Divide Ratio
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide-by-1
#0001 : 0001
Divide-by-2
#0010 : 0010
Divide-by-3
#0011 : 0011
Divide-by-4
#0100 : 0100
Divide-by-5
#0101 : 0101
Divide-by-6
#0110 : 0110
Divide-by-7
#0111 : 0111
Divide-by-8
#1000 : 1000
Divide-by-9
#1001 : 1001
Divide-by-10
#1010 : 1010
Divide-by-11
#1011 : 1011
Divide-by-12
#1100 : 1100
Divide-by-13
#1101 : 1101
Divide-by-14
#1110 : 1110
Divide-by-15
#1111 : 1111
Divide-by-16
End of enumeration elements list.
DIVCORE : Core Clock Divide Ratio
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide-by-1
#0001 : 0001
Divide-by-2
#0010 : 0010
Divide-by-3
#0011 : 0011
Divide-by-4
#0100 : 0100
Divide-by-5
#0101 : 0101
Divide-by-6
#0110 : 0110
Divide-by-7
#0111 : 0111
Divide-by-8
#1000 : 1000
Divide-by-9
#1001 : 1001
Divide-by-10
#1010 : 1010
Divide-by-11
#1011 : 1011
Divide-by-12
#1100 : 1100
Divide-by-13
#1101 : 1101
Divide-by-14
#1110 : 1110
Divide-by-15
#1111 : 1111
Divide-by-16
End of enumeration elements list.
SCS : System Clock Source
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0001 : 0001
System OSC (SOSC_CLK)
#0010 : 0010
Slow IRC (SIRC_CLK)
End of enumeration elements list.
HSRUN Clock Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVSLOW : Slow Clock Divide Ratio
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide-by-1
#0001 : 0001
Divide-by-2
#0010 : 0010
Divide-by-3
#0011 : 0011
Divide-by-4
#0100 : 0100
Divide-by-5
#0101 : 0101
Divide-by-6
#0110 : 0110
Divide-by-7
#0111 : 0111
Divide-by-8
#1000 : 1000
Divide-by-9
#1001 : 1001
Divide-by-10
#1010 : 1010
Divide-by-11
#1011 : 1011
Divide-by-12
#1100 : 1100
Divide-by-13
#1101 : 1101
Divide-by-14
#1110 : 1110
Divide-by-15
#1111 : 1111
Divide-by-16
End of enumeration elements list.
DIVCORE : Core Clock Divide Ratio
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide-by-1
#0001 : 0001
Divide-by-2
#0010 : 0010
Divide-by-3
#0011 : 0011
Divide-by-4
#0100 : 0100
Divide-by-5
#0101 : 0101
Divide-by-6
#0110 : 0110
Divide-by-7
#0111 : 0111
Divide-by-8
#1000 : 1000
Divide-by-9
#1001 : 1001
Divide-by-10
#1010 : 1010
Divide-by-11
#1011 : 1011
Divide-by-12
#1100 : 1100
Divide-by-13
#1101 : 1101
Divide-by-14
#1110 : 1110
Divide-by-15
#1111 : 1111
Divide-by-16
End of enumeration elements list.
SCS : System Clock Source
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0001 : 0001
System OSC (SOSC_CLK)
#0010 : 0010
Slow IRC (SIRC_CLK)
#0011 : 0011
Fast IRC (FIRC_CLK)
#0110 : 0110
System PLL (SPLL_CLK)
End of enumeration elements list.
SCG CLKOUT Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKOUTSEL : SCG Clkout Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
SCG SLOW Clock
#0001 : 0001
System OSC (SOSC_CLK)
#0010 : 0010
Slow IRC (SIRC_CLK)
#0011 : 0011
Fast IRC (FIRC_CLK)
#0110 : 0110
System PLL (SPLL_CLK)
End of enumeration elements list.
Slow IRC Control Status Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIRCEN : Slow IRC Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slow IRC is disabled
#1 : 1
Slow IRC is enabled
End of enumeration elements list.
SIRCSTEN : Slow IRC Stop Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slow IRC is disabled in Stop modes
#1 : 1
Slow IRC is enabled in Stop modes
End of enumeration elements list.
SIRCLPEN : Slow IRC Low Power Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slow IRC is disabled in VLP modes
#1 : 1
Slow IRC is enabled in VLP modes
End of enumeration elements list.
LK : Lock Register
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Control Status Register can be written.
#1 : 1
Control Status Register cannot be written.
End of enumeration elements list.
SIRCVLD : Slow IRC Valid
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
Slow IRC is not enabled or clock is not valid
#1 : 1
Slow IRC is enabled and output clock is valid
End of enumeration elements list.
SIRCSEL : Slow IRC Selected
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
Slow IRC is not the system clock source
#1 : 1
Slow IRC is the system clock source
End of enumeration elements list.
Slow IRC Divide Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIRCDIV1 : Slow IRC Clock Divide 1
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 000
Output disabled
#001 : 001
Divide by 1
#010 : 010
Divide by 2
#011 : 011
Divide by 4
#100 : 100
Divide by 8
#101 : 101
Divide by 16
#110 : 110
Divide by 32
#111 : 111
Divide by 64
End of enumeration elements list.
SIRCDIV2 : Slow IRC Clock Divide 2
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Output disabled
#001 : 001
Divide by 1
#010 : 010
Divide by 2
#011 : 011
Divide by 4
#100 : 100
Divide by 8
#101 : 101
Divide by 16
#110 : 110
Divide by 32
#111 : 111
Divide by 64
End of enumeration elements list.
SIRCDIV3 : Slow IRC Clock Divider 3
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 000
Output disabled
#001 : 001
Divide by 1
#010 : 010
Divide by 2
#011 : 011
Divide by 4
#100 : 100
Divide by 8
#101 : 101
Divide by 16
#110 : 110
Divide by 32
#111 : 111
Divide by 64
End of enumeration elements list.
Slow IRC Configuration Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RANGE : Frequency Range
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slow IRC low range clock (2 MHz)
#1 : 1
Slow IRC high range clock (8 MHz )
End of enumeration elements list.
Fast IRC Control Status Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIRCEN : Fast IRC Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast IRC is disabled
#1 : 1
Fast IRC is enabled
End of enumeration elements list.
FIRCSTEN : Fast IRC Stop Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast IRC is disabled in Stop modes. When selected as the reference clock to the System PLL and if the System PLL is enabled in STOP mode, the Fast IRC will stay enabled even if FIRCSTEN=0.
#1 : 1
Fast IRC is enabled in Stop modes
End of enumeration elements list.
FIRCLPEN : Fast IRC Low Power Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast IRC is disabled in VLP modes
#1 : 1
Fast IRC is enabled in VLP modes
End of enumeration elements list.
FIRCREGOFF : Fast IRC Regulator Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast IRC Regulator is enabled.
#1 : 1
Fast IRC Regulator is disabled.
End of enumeration elements list.
FIRCTREN : Fast IRC Trim Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable trimming Fast IRC to an external clock source
#1 : 1
Enable trimming Fast IRC to an external clock source
End of enumeration elements list.
FIRCTRUP : Fast IRC Trim Update
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Fast IRC trimming updates
#1 : 1
Enable Fast IRC trimming updates
End of enumeration elements list.
LK : Lock Register
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Control Status Register can be written.
#1 : 1
Control Status Register cannot be written.
End of enumeration elements list.
FIRCVLD : Fast IRC Valid status
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
Fast IRC is not enabled or clock is not valid.
#1 : 1
Fast IRC is enabled and output clock is valid. The clock is valid once there is an output clock from the FIRC analog.
End of enumeration elements list.
FIRCSEL : Fast IRC Selected status
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
Fast IRC is not the system clock source
#1 : 1
Fast IRC is the system clock source
End of enumeration elements list.
FIRCERR : Fast IRC Clock Error
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Error not detected with the Fast IRC trimming.
#1 : 1
Error detected with the Fast IRC trimming.
End of enumeration elements list.
Fast IRC Divide Register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIRCDIV1 : Fast IRC Clock Divide 1
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 000
Output disabled
#001 : 001
Divide by 1
#010 : 010
Divide by 2
#011 : 011
Divide by 4
#100 : 100
Divide by 8
#101 : 101
Divide by 16
#110 : 110
Divide by 32
#111 : 111
Divide by 64
End of enumeration elements list.
FIRCDIV2 : Fast IRC Clock Divide 2
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Output disabled
#001 : 001
Divide by 1
#010 : 010
Divide by 2
#011 : 011
Divide by 4
#100 : 100
Divide by 8
#101 : 101
Divide by 16
#110 : 110
Divide by 32
#111 : 111
Divide by 64
End of enumeration elements list.
FIRCDIV3 : Fast IRC Clock Divider 3
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock disabled
#001 : 001
Divide by 1
#010 : 010
Divide by 2
#011 : 011
Divide by 4
#100 : 100
Divide by 8
#101 : 101
Divide by 16
#110 : 110
Divide by 32
#111 : 111
Divide by 64
End of enumeration elements list.
Fast IRC Configuration Register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RANGE : Frequency Range
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
Fast IRC is trimmed to 48 MHz
#01 : 01
Fast IRC is trimmed to 52 MHz
#10 : 10
Fast IRC is trimmed to 56 MHz
#11 : 11
Fast IRC is trimmed to 60 MHz
End of enumeration elements list.
Fast IRC Trim Configuration Register
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIMSRC : Trim Source
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
USB0 Start of Frame (1 kHz)
#10 : 10
System OSC
End of enumeration elements list.
TRIMDIV : Fast IRC Trim Predivide
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Divide by 1
#001 : 001
Divide by 128
#010 : 010
Divide by 256
#011 : 011
Divide by 512
#100 : 100
Divide by 1024
#101 : 101
Divide by 2048
#110 : 110
Reserved. Writing this value will result in Divide by 1.
#111 : 111
Reserved. Writing this value will result in a Divide by 1.
End of enumeration elements list.
Fast IRC Status Register
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIMFINE : Trim Fine Status
bits : 0 - 6 (7 bit)
access : read-write
TRIMCOAR : Trim Coarse
bits : 8 - 13 (6 bit)
access : read-write
Parameter Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CLKPRES : Clock Present
bits : 0 - 7 (8 bit)
access : read-only
DIVPRES : Divider Present
bits : 27 - 31 (5 bit)
access : read-only
System PLL Control Status Register
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPLLEN : System PLL Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
System PLL is disabled
#1 : 1
System PLL is enabled
End of enumeration elements list.
SPLLSTEN : System PLL Stop Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
System PLL is disabled in Stop modes
#1 : 1
System PLL is enabled in Stop modes
End of enumeration elements list.
SPLLCM : System PLL Clock Monitor
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
System PLL Clock Monitor is disabled
#1 : 1
System PLL Clock Monitor is enabled
End of enumeration elements list.
SPLLCMRE : System PLL Clock Monitor Reset Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Monitor generates interrupt when error detected
#1 : 1
Clock Monitor generates reset when error detected
End of enumeration elements list.
LK : Lock Register
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Control Status Register can be written.
#1 : 1
Control Status Register cannot be written.
End of enumeration elements list.
SPLLVLD : System PLL Valid
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
System PLL is not enabled or clock is not valid
#1 : 1
System PLL is enabled and output clock is valid
End of enumeration elements list.
SPLLSEL : System PLL Selected
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
System PLL is not the system clock source
#1 : 1
System PLL is the system clock source
End of enumeration elements list.
SPLLERR : System PLL Clock Error
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
System PLL Clock Monitor is disabled or has not detected an error
#1 : 1
System PLL Clock Monitor is enabled and detected an error. System PLL Clock Error flag will not set when System OSC is selected as its source and SOSCERR has set.
End of enumeration elements list.
System PLL Divide Register
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPLLDIV1 : System PLL Clock Divide 1
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock disabled
#001 : 001
Divide by 1
#010 : 010
Divide by 2
#011 : 011
Divide by 4
#100 : 100
Divide by 8
#101 : 101
Divide by 16
#110 : 110
Divide by 32
#111 : 111
Divide by 64
End of enumeration elements list.
SPLLDIV2 : System PLL Clock Divide 2
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock disabled
#001 : 001
Divide by 1
#010 : 010
Divide by 2
#011 : 011
Divide by 4
#100 : 100
Divide by 8
#101 : 101
Divide by 16
#110 : 110
Divide by 32
#111 : 111
Divide by 64
End of enumeration elements list.
SPLLDIV3 : System PLL Clock Divide 3
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 000
Clock disabled
#001 : 001
Divide by 1
#010 : 010
Divide by 2
#011 : 011
Divide by 4
#100 : 100
Divide by 8
#101 : 101
Divide by 16
#110 : 110
Divide by 32
#111 : 111
Divide by 64
End of enumeration elements list.
System PLL Configuration Register
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : Clock Source
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
System OSC (SOSC)
#1 : 1
Fast IRC (FIRC)
End of enumeration elements list.
PREDIV : PLL Reference Clock Divider
bits : 8 - 10 (3 bit)
access : read-write
MULT : System PLL Multiplier
bits : 16 - 20 (5 bit)
access : read-write
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