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MCG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected

Registers

C1

C2

HCTRIM

HTTRIM

HFTRIM

MC

LTRIMRNG

LFTRIM

LSTRIM

S

SC


C1

MCG Control Register 1
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1 C1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IREFSTEN IRCLKEN CLKS

IREFSTEN : Internal Reference Stop Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

LIRC is disabled in Stop mode.

#1 : 1

LIRC is enabled in Stop mode, if IRCLKEN is set.

End of enumeration elements list.

IRCLKEN : Internal Reference Clock Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

LIRC is disabled.

#1 : 1

LIRC is enabled.

End of enumeration elements list.

CLKS : Clock Source Select
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 00

Selects HIRC clock as the main clock source. This is HIRC mode.

#01 : 01

Selects LIRC clock as the main clock source. This is LIRC2M or LIRC8M mode.

#10 : 10

Selects external clock as the main clock source. This is EXT mode.

#11 : 11

Reserved. Writing 11 takes no effect.

End of enumeration elements list.


C2

MCG Control Register 2
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2 C2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRCS EREFS0 HGO0 RANGE0

IRCS : Low-frequency Internal Reference Clock Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

LIRC is in 2 MHz mode.

#1 : 1

LIRC is in 8 MHz mode.

End of enumeration elements list.

EREFS0 : External Clock Source Select
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

External clock requested.

#1 : 1

Oscillator requested.

End of enumeration elements list.

HGO0 : Crystal Oscillator Operation Mode Select
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Configure crystal oscillator for low-power operation.

#1 : 1

Configure crystal oscillator for high-gain operation.

End of enumeration elements list.

RANGE0 : External Clock Source Frequency Range Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 00

Low frequency range selected for the crystal oscillator or the external clock source.

#01 : 01

High frequency range selected for the crystal oscillator or the external clock source.

#10 : 10

Very high frequency range selected for the crystal oscillator or the external clock source.

#11 : 11

Very high frequency range selected for the crystal oscillator or the external clock source. Same effect as 10.

End of enumeration elements list.


HCTRIM

MCG High-frequency IRC Coarse Trim Register
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HCTRIM HCTRIM read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 COARSE_TRIM

COARSE_TRIM : High-frequency IRC Coarse Trim
bits : 0 - 5 (6 bit)
access : read-only


HTTRIM

MCG High-frequency IRC Tempco (Temperature Coefficient) Trim Register
address_offset : 0x15 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HTTRIM HTTRIM read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TEMPCO_TRIM

TEMPCO_TRIM : High-frequency IRC Tempco Trim
bits : 0 - 4 (5 bit)
access : read-only


HFTRIM

MCG High-frequency IRC Fine Trim Register
address_offset : 0x16 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HFTRIM HFTRIM read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FINE_TRIM

FINE_TRIM : High-frequency IRC Fine Trim
bits : 0 - 6 (7 bit)
access : read-only


MC

MCG Miscellaneous Control Register
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MC MC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LIRC_DIV2 HIRCEN

LIRC_DIV2 : Second Low-frequency Internal Reference Clock Divider
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 000

Division factor is 1.

#001 : 001

Division factor is 2.

#010 : 010

Division factor is 4.

#011 : 011

Division factor is 8.

#100 : 100

Division factor is 16.

#101 : 101

Division factor is 32.

#110 : 110

Division factor is 64.

#111 : 111

Division factor is 128.

End of enumeration elements list.

HIRCEN : High-frequency IRC Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

HIRC source is not enabled.

#1 : 1

HIRC source is enabled.

End of enumeration elements list.


LTRIMRNG

MCG Low-frequency IRC Trim Range Register
address_offset : 0x19 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LTRIMRNG LTRIMRNG read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 STRIMRNG FTRIMRNG

STRIMRNG : LIRC Slow TRIM (2 MHz) Range
bits : 0 - 1 (2 bit)
access : read-only

Enumeration:

#00 : 00

Frequency shift by 10%.

#01 : 01

No frequency shift.

#10 : 10

No frequency shift.

#11 : 11

Frequency shift by -10%.

End of enumeration elements list.

FTRIMRNG : LIRC Fast TRIM (8 MHz) Range
bits : 2 - 3 (2 bit)
access : read-only

Enumeration:

#00 : 00

Frequency shift by 10%.

#01 : 01

No frequency shift.

#10 : 10

No frequency shift.

#11 : 11

Frequency shift by -10%.

End of enumeration elements list.


LFTRIM

MCG Low-frequency IRC8M Trim Register
address_offset : 0x1A Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LFTRIM LFTRIM read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LIRC_FTRIM

LIRC_FTRIM : LIRC8M TRIM
bits : 0 - 6 (7 bit)
access : read-only


LSTRIM

MCG Low-frequency IRC2M Trim Register
address_offset : 0x1B Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LSTRIM LSTRIM read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LIRC_STRIM

LIRC_STRIM : LIRC2M TRIM
bits : 0 - 6 (7 bit)
access : read-only


S

MCG Status Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

S S read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OSCINIT0 CLKST

OSCINIT0 : OSC Initialization Status
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

OSC is not ready.

#1 : 1

OSC clock is ready.

End of enumeration elements list.

CLKST : Clock Mode Status
bits : 2 - 3 (2 bit)
access : read-only

Enumeration:

#00 : 00

HIRC clock is selected as the main clock source, and MCG_Lite works at HIRC mode.

#01 : 01

LIRC clock is selected as the main clock source, and MCG_Lite works at LIRC2M or LIRC8M mode.

#10 : 10

External clock is selected as the main clock source, and MCG_Lite works at EXT mode.

End of enumeration elements list.


SC

MCG Status and Control Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SC SC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FCRDIV

FCRDIV : Low-frequency Internal Reference Clock Divider
bits : 1 - 3 (3 bit)
access : read-write

Enumeration:

#000 : 000

Division factor is 1.

#001 : 001

Division factor is 2.

#010 : 010

Division factor is 4.

#011 : 011

Division factor is 8.

#100 : 100

Division factor is 16.

#101 : 101

Division factor is 32.

#110 : 110

Division factor is 64.

#111 : 111

Division factor is 128.

End of enumeration elements list.



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