Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xD byte (0x0)
mem_usage : registers
protection : not protected
I2C Address Register 1
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AD : Address
bits : 1 - 7 (7 bit)
access : read-write
I2C Frequency Divider register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICR : ClockRate
bits : 0 - 5 (6 bit)
access : read-write
MULT : Multiplier Factor
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
mul = 1
#01 : 01
mul = 2
#10 : 10
mul = 4
End of enumeration elements list.
I2C Control Register 1
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAEN : DMA Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
All DMA signalling disabled.
#1 : 1
DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.
End of enumeration elements list.
WUEN : Wakeup Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation. No interrupt generated when address matching in low power mode.
#1 : 1
Enables the wakeup function in low power mode.
End of enumeration elements list.
RSTA : Repeat START
bits : 2 - 2 (1 bit)
access : write-only
TXAK : Transmit Acknowledge Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).
#1 : 1
No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).
End of enumeration elements list.
TX : Transmit Mode Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive
#1 : 1
Transmit
End of enumeration elements list.
MST : Master Mode Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave mode
#1 : 1
Master mode
End of enumeration elements list.
IICIE : I2C Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
IICEN : I2C Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
I2C Status register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXAK : Receive Acknowledge
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Acknowledge signal was received after the completion of one byte of data transmission on the bus
#1 : 1
No acknowledge signal detected
End of enumeration elements list.
IICIF : Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt pending
#1 : 1
Interrupt pending
End of enumeration elements list.
SRW : Slave Read/Write
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Slave receive, master writing to slave
#1 : 1
Slave transmit, master reading from slave
End of enumeration elements list.
RAM : Range Address Match
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not addressed
#1 : 1
Addressed as a slave
End of enumeration elements list.
ARBL : Arbitration Lost
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Standard bus operation.
#1 : 1
Loss of arbitration.
End of enumeration elements list.
BUSY : Bus Busy
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Bus is idle
#1 : 1
Bus is busy
End of enumeration elements list.
IAAS : Addressed As A Slave
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not addressed
#1 : 1
Addressed as a slave
End of enumeration elements list.
TCF : Transfer Complete Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transfer in progress
#1 : 1
Transfer complete
End of enumeration elements list.
I2C Data I/O register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 7 (8 bit)
access : read-write
I2C Control Register 2
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AD : Slave Address
bits : 0 - 2 (3 bit)
access : read-write
RMEN : Range Address Matching Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.
#1 : 1
Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.
End of enumeration elements list.
SBRC : Slave Baud Rate Control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The slave baud rate follows the master baud rate and clock stretching may occur
#1 : 1
Slave baud rate is independent of the master baud rate
End of enumeration elements list.
HDRS : High Drive Select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal drive mode
#1 : 1
High drive mode
End of enumeration elements list.
ADEXT : Address Extension
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
7-bit address scheme
#1 : 1
10-bit address scheme
End of enumeration elements list.
GCAEN : General Call Address Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
I2C Programmable Input Glitch Filter Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLT : I2C Programmable Filter Factor
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
No filter/bypass
End of enumeration elements list.
STARTF : I2C Bus Start Detect Flag
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No start happens on I2C bus
#1 : 1
Start detected on I2C bus
End of enumeration elements list.
SSIE : I2C Bus Stop or Start Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stop or start detection interrupt is disabled
#1 : 1
Stop or start detection interrupt is enabled
End of enumeration elements list.
STOPF : I2C Bus Stop Detect Flag
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No stop happens on I2C bus
#1 : 1
Stop detected on I2C bus
End of enumeration elements list.
SHEN : Stop Hold Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
#1 : 1
Stop holdoff is enabled.
End of enumeration elements list.
I2C Range Address register
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAD : Range Slave Address
bits : 1 - 7 (7 bit)
access : read-write
I2C SMBus Control and Status register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHTF2IE : SHTF2 Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SHTF2 interrupt is disabled
#1 : 1
SHTF2 interrupt is enabled
End of enumeration elements list.
SHTF2 : SCL High Timeout Flag 2
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No SCL high and SDA low timeout occurs
#1 : 1
SCL high and SDA low timeout occurs
End of enumeration elements list.
SHTF1 : SCL High Timeout Flag 1
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
No SCL high and SDA high timeout occurs
#1 : 1
SCL high and SDA high timeout occurs
End of enumeration elements list.
SLTF : SCL Low Timeout Flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No low timeout occurs
#1 : 1
Low timeout occurs
End of enumeration elements list.
TCKSEL : Timeout Counter Clock Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timeout counter counts at the frequency of the I2C module clock / 64
#1 : 1
Timeout counter counts at the frequency of the I2C module clock
End of enumeration elements list.
SIICAEN : Second I2C Address Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C address register 2 matching is disabled
#1 : 1
I2C address register 2 matching is enabled
End of enumeration elements list.
ALERTEN : SMBus Alert Response Address Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
SMBus alert response address matching is disabled
#1 : 1
SMBus alert response address matching is enabled
End of enumeration elements list.
FACK : Fast NACK/ACK Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
An ACK or NACK is sent on the following receiving data byte
#1 : 1
Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
End of enumeration elements list.
I2C Address Register 2
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAD : SMBus Address
bits : 1 - 7 (7 bit)
access : read-write
I2C SCL Low Timeout Register High
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSLT : SSLT[15:8]
bits : 0 - 7 (8 bit)
access : read-write
I2C SCL Low Timeout Register Low
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSLT : SSLT[7:0]
bits : 0 - 7 (8 bit)
access : read-write
I2C Status register 2
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMPTY : Empty flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Tx or Rx buffer is not empty and cannot be written to, that is new data cannot be loaded into the buffer.
#1 : 1
Tx or Rx buffer is empty and can be written to, that is new data can be loaded into the buffer.
End of enumeration elements list.
ERROR : Error flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The buffer is not full and all write/read operations have no errors.
#1 : 1
There are 3 or more write/read errors during the data transfer phase (when the Empty flag is not set and the buffer is busy).
End of enumeration elements list.
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