Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
SPI Status Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RFIFOEF : SPI read FIFO empty flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Read FIFO has data. Reads of the DH:DL registers in 16-bit mode or the DL register in 8-bit mode will empty the read FIFO.
#1 : 1
Read FIFO is empty.
End of enumeration elements list.
TXFULLF : Transmit FIFO full flag
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO has less than 8 bytes
#1 : 1
Transmit FIFO has 8 bytes of data
End of enumeration elements list.
TNEAREF : Transmit FIFO nearly empty flag
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO has more than 16 bits (when C3[TNEAREF_MARK] is 0) or more than 32 bits (when C3[TNEAREF_MARK] is 1) remaining to transmit
#1 : 1
Transmit FIFO has an amount of data equal to or less than 16 bits (when C3[TNEAREF_MARK] is 0) or 32 bits (when C3[TNEAREF_MARK] is 1) remaining to transmit
End of enumeration elements list.
RNFULLF : Receive FIFO nearly full flag
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIFO has received less than 48 bits (when C3[RNFULLF_MARK] is 0) or less than 32 bits (when C3[RNFULLF_MARK] is 1)
#1 : 1
Receive FIFO has received data of an amount equal to or greater than 48 bits (when C3[RNFULLF_MARK] is 0) or 32 bits (when C3[RNFULLF_MARK] is 1)
End of enumeration elements list.
MODF : Master Mode Fault Flag
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
No mode fault error
#1 : 1
Mode fault error detected
End of enumeration elements list.
SPTEF : SPI Transmit Buffer Empty Flag (when FIFO is not supported or not enabled) or SPI transmit FIFO empty flag (when FIFO is supported and enabled)
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or SPI FIFO not empty (when FIFOMODE is 1)
#1 : 1
SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI FIFO empty (when FIFOMODE is 1)
End of enumeration elements list.
SPMF : SPI Match Flag
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Value in the receive data buffer does not match the value in the MH:ML registers
#1 : 1
Value in the receive data buffer matches the value in the MH:ML registers
End of enumeration elements list.
SPRF : SPI Read Buffer Full Flag (when FIFO is not supported or not enabled) or SPI read FIFO FULL flag (when FIFO is supported and enabled)
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is not full (when FIFOMODE is 1)
#1 : 1
Data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is full (when FIFOMODE is 1)
End of enumeration elements list.
SPI Baud Rate Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPR : SPI Baud Rate Divisor
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Baud rate divisor is 2.
#0001 : 0001
Baud rate divisor is 4.
#0010 : 0010
Baud rate divisor is 8.
#0011 : 0011
Baud rate divisor is 16.
#0100 : 0100
Baud rate divisor is 32.
#0101 : 0101
Baud rate divisor is 64.
#0110 : 0110
Baud rate divisor is 128.
#0111 : 0111
Baud rate divisor is 256.
#1000 : 1000
Baud rate divisor is 512.
End of enumeration elements list.
SPPR : SPI Baud Rate Prescale Divisor
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 000
Baud rate prescaler divisor is 1.
#001 : 001
Baud rate prescaler divisor is 2.
#010 : 010
Baud rate prescaler divisor is 3.
#011 : 011
Baud rate prescaler divisor is 4.
#100 : 100
Baud rate prescaler divisor is 5.
#101 : 101
Baud rate prescaler divisor is 6.
#110 : 110
Baud rate prescaler divisor is 7.
#111 : 111
Baud rate prescaler divisor is 8.
End of enumeration elements list.
SPI Control Register 2
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPC0 : SPI Pin Control 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in.
#1 : 1
SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI.
End of enumeration elements list.
SPISWAI : SPI Stop in Wait Mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI clocks continue to operate in Wait mode.
#1 : 1
SPI clocks stop when the MCU enters Wait mode.
End of enumeration elements list.
RXDMAE : Receive DMA enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA request for receive is disabled and interrupt from SPRF is allowed
#1 : 1
DMA request for receive is enabled and interrupt from SPRF is disabled
End of enumeration elements list.
BIDIROE : Bidirectional Mode Output Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output driver disabled so SPI data I/O pin acts as an input
#1 : 1
SPI I/O pin enabled as an output
End of enumeration elements list.
MODFEN : Master Mode-Fault Function Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
#1 : 1
Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
End of enumeration elements list.
TXDMAE : Transmit DMA enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA request for transmit is disabled and interrupt from SPTEF is allowed
#1 : 1
DMA request for transmit is enabled and interrupt from SPTEF is disabled
End of enumeration elements list.
SPIMODE : SPI 8-bit or 16-bit mode
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
8-bit SPI shift register, match register, and buffers
#1 : 1
16-bit SPI shift register, match register, and buffers
End of enumeration elements list.
SPMIE : SPI Match Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts from SPMF inhibited (use polling)
#1 : 1
When SPMF is 1, requests a hardware interrupt
End of enumeration elements list.
SPI Control Register 1
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSBFE : LSB First (shifter direction)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI serial data transfers start with the most significant bit.
#1 : 1
SPI serial data transfers start with the least significant bit.
End of enumeration elements list.
SSOE : Slave Select Output Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input.
#1 : 1
When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input.
End of enumeration elements list.
CPHA : Clock Phase
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
First edge on SPSCK occurs at the middle of the first cycle of a data transfer.
#1 : 1
First edge on SPSCK occurs at the start of the first cycle of a data transfer.
End of enumeration elements list.
CPOL : Clock Polarity
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Active-high SPI clock (idles low)
#1 : 1
Active-low SPI clock (idles high)
End of enumeration elements list.
MSTR : Master/Slave Mode Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI module configured as a slave SPI device
#1 : 1
SPI module configured as a master SPI device
End of enumeration elements list.
SPTIE : SPI Transmit Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts from SPTEF inhibited (use polling)
#1 : 1
When SPTEF is 1, hardware interrupt requested
End of enumeration elements list.
SPE : SPI System Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI system inactive
#1 : 1
SPI system enabled
End of enumeration elements list.
SPIE : SPI Interrupt Enable: for SPRF and MODF (when FIFO is not supported or not enabled) or for read FIFO (when FIFO is supported and enabled)
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupts from SPRF and MODF are inhibited-use polling (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are disabled (when FIFOMODE is 1)
#1 : 1
Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are enabled (when FIFOMODE is 1)
End of enumeration elements list.
SPI Match Register low
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Bits : Hardware compare value (low byte)
bits : 0 - 7 (8 bit)
access : read-write
SPI match register high
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Bits : Hardware compare value (high byte)
bits : 0 - 7 (8 bit)
access : read-write
SPI Data Register low
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Bits : Data (low byte)
bits : 0 - 7 (8 bit)
access : read-write
SPI data register high
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Bits : Data (high byte)
bits : 0 - 7 (8 bit)
access : read-write
SPI clear interrupt register
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPRFCI : Receive FIFO full flag clear interrupt
bits : 0 - 0 (1 bit)
access : write-only
SPTEFCI : Transmit FIFO empty flag clear interrupt
bits : 1 - 1 (1 bit)
access : write-only
RNFULLFCI : Receive FIFO nearly full flag clear interrupt
bits : 2 - 2 (1 bit)
access : write-only
TNEAREFCI : Transmit FIFO nearly empty flag clear interrupt
bits : 3 - 3 (1 bit)
access : write-only
RXFOF : Receive FIFO overflow flag
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIFO overflow condition has not occurred
#1 : 1
Receive FIFO overflow condition occurred
End of enumeration elements list.
TXFOF : Transmit FIFO overflow flag
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO overflow condition has not occurred
#1 : 1
Transmit FIFO overflow condition occurred
End of enumeration elements list.
RXFERR : Receive FIFO error flag
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
No receive FIFO error occurred
#1 : 1
A receive FIFO error occurred
End of enumeration elements list.
TXFERR : Transmit FIFO error flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No transmit FIFO error occurred
#1 : 1
A transmit FIFO error occurred
End of enumeration elements list.
SPI control register 3
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOMODE : FIFO mode enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
FIFO mode disabled
#1 : 1
FIFO mode enabled
End of enumeration elements list.
RNFULLIEN : Receive FIFO nearly full interrupt enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt upon RNFULLF being set
#1 : 1
Enable interrupts upon RNFULLF being set
End of enumeration elements list.
TNEARIEN : Transmit FIFO nearly empty interrupt enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt upon TNEAREF being set
#1 : 1
Enable interrupts upon TNEAREF being set
End of enumeration elements list.
INTCLR : Interrupt clearing mechanism select
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
These interrupts are cleared when the corresponding flags are cleared depending on the state of the FIFOs
#1 : 1
These interrupts are cleared by writing the corresponding bits in the CI register
End of enumeration elements list.
RNFULLF_MARK : Receive FIFO nearly full watermark
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
RNFULLF is set when the receive FIFO has 48 bits or more
#1 : 1
RNFULLF is set when the receive FIFO has 32 bits or more
End of enumeration elements list.
TNEAREF_MARK : Transmit FIFO nearly empty watermark
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
TNEAREF is set when the transmit FIFO has 16 bits or less
#1 : 1
TNEAREF is set when the transmit FIFO has 32 bits or less
End of enumeration elements list.
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