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address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
MTB Position Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRAP : This field is set to 1 automatically when the POINTER value wraps as determined by the MTB_MASTER[MASK] field in the MASTER Trace Control Register
bits : 2 - 2 (1 bit)
access : read-write
POINTER : Trace Packet Address Pointer[28:0]
bits : 3 - 31 (29 bit)
access : read-write
Peripheral ID Register
address_offset : 0x1FA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERIPHID : Peripheral ID4 is hardwired to 0x0000_0004; ID0 to 0x0000_0032; ID1 to 0x0000_00B9; ID2 to 0x0000_000B; and all the others to 0x0000_0000
bits : 0 - 31 (32 bit)
access : read-only
Component ID Register
address_offset : 0x1FE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMPID : Component ID
bits : 0 - 31 (32 bit)
access : read-only
Peripheral ID Register
address_offset : 0x2F74 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERIPHID : Peripheral ID4 is hardwired to 0x0000_0004; ID0 to 0x0000_0032; ID1 to 0x0000_00B9; ID2 to 0x0000_000B; and all the others to 0x0000_0000
bits : 0 - 31 (32 bit)
access : read-only
Component ID Register
address_offset : 0x2FD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMPID : Component ID
bits : 0 - 31 (32 bit)
access : read-only
Peripheral ID Register
address_offset : 0x3F4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERIPHID : Peripheral ID4 is hardwired to 0x0000_0004; ID0 to 0x0000_0032; ID1 to 0x0000_00B9; ID2 to 0x0000_000B; and all the others to 0x0000_0000
bits : 0 - 31 (32 bit)
access : read-only
Component ID Register
address_offset : 0x3FCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMPID : Component ID
bits : 0 - 31 (32 bit)
access : read-only
MTB Master Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK : Mask
bits : 0 - 4 (5 bit)
access : read-write
TSTARTEN : Trace Start Input Enable
bits : 5 - 5 (1 bit)
access : read-write
TSTOPEN : Trace Stop Input Enable
bits : 6 - 6 (1 bit)
access : read-write
SFRWPRIV : Special Function Register Write Privilege
bits : 7 - 7 (1 bit)
access : read-write
RAMPRIV : RAM Privilege
bits : 8 - 8 (1 bit)
access : read-write
HALTREQ : Halt Request
bits : 9 - 9 (1 bit)
access : read-write
EN : Main Trace Enable
bits : 31 - 31 (1 bit)
access : read-write
Peripheral ID Register
address_offset : 0x4F28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERIPHID : Peripheral ID4 is hardwired to 0x0000_0004; ID0 to 0x0000_0032; ID1 to 0x0000_00B9; ID2 to 0x0000_000B; and all the others to 0x0000_0000
bits : 0 - 31 (32 bit)
access : read-only
Component ID Register
address_offset : 0x4FC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COMPID : Component ID
bits : 0 - 31 (32 bit)
access : read-only
Peripheral ID Register
address_offset : 0x5F08 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERIPHID : Peripheral ID4 is hardwired to 0x0000_0004; ID0 to 0x0000_0032; ID1 to 0x0000_00B9; ID2 to 0x0000_000B; and all the others to 0x0000_0000
bits : 0 - 31 (32 bit)
access : read-only
Peripheral ID Register
address_offset : 0x6EEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERIPHID : Peripheral ID4 is hardwired to 0x0000_0004; ID0 to 0x0000_0032; ID1 to 0x0000_00B9; ID2 to 0x0000_000B; and all the others to 0x0000_0000
bits : 0 - 31 (32 bit)
access : read-only
Peripheral ID Register
address_offset : 0x7ED4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERIPHID : Peripheral ID4 is hardwired to 0x0000_0004; ID0 to 0x0000_0032; ID1 to 0x0000_00B9; ID2 to 0x0000_000B; and all the others to 0x0000_0000
bits : 0 - 31 (32 bit)
access : read-only
MTB Flow Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTOSTOP : If this field is 1 and WATERMARK is equal to MTB_POSITION[POINTER], then MTB_MASTER[EN] is automatically set to 0
bits : 0 - 0 (1 bit)
access : read-write
AUTOHALT : If this field is 1 and WATERMARK is equal to MTB_POSITION[POINTER], then MTB_MASTER[HALTREQ] is automatically set to 1
bits : 1 - 1 (1 bit)
access : read-write
WATERMARK : WATERMARK[28:0]
bits : 3 - 31 (29 bit)
access : read-write
Peripheral ID Register
address_offset : 0x8EC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERIPHID : Peripheral ID4 is hardwired to 0x0000_0004; ID0 to 0x0000_0032; ID1 to 0x0000_00B9; ID2 to 0x0000_000B; and all the others to 0x0000_0000
bits : 0 - 31 (32 bit)
access : read-only
MTB Base Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BASEADDR : This value is defined with a hardwired signal and the expression: 0x2000_0000 - (RAM_Size/4)
bits : 0 - 31 (32 bit)
access : read-only
Integration Mode Control Register
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MODECTRL : Hardwired to 0x0000_0000
bits : 0 - 31 (32 bit)
access : read-only
Claim TAG Set Register
address_offset : 0xFA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TAGSET : Hardwired to 0x0000_0000
bits : 0 - 31 (32 bit)
access : read-only
Claim TAG Clear Register
address_offset : 0xFA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TAGCLEAR : Hardwired to 0x0000_0000
bits : 0 - 31 (32 bit)
access : read-only
Lock Access Register
address_offset : 0xFB0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LOCKACCESS : Hardwired to 0x0000_0000
bits : 0 - 31 (32 bit)
access : read-only
Lock Status Register
address_offset : 0xFB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LOCKSTAT : Hardwired to 0x0000_0000
bits : 0 - 31 (32 bit)
access : read-only
Authentication Status Register
address_offset : 0xFB8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIT0 : Connected to DBGEN.
bits : 0 - 0 (1 bit)
access : read-only
BIT1 : Hardwired to 1.
bits : 1 - 1 (1 bit)
access : read-only
BIT2 : Connected to NIDEN or DBGEN signal.
bits : 2 - 2 (1 bit)
access : read-only
BIT3 : Hardwired to 1.
bits : 3 - 3 (1 bit)
access : read-only
Device Architecture Register
address_offset : 0xFBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DEVICEARCH : Hardwired to 0x4770_0A31.
bits : 0 - 31 (32 bit)
access : read-only
Device Configuration Register
address_offset : 0xFC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DEVICECFG : Hardwired to 0x0000_0000.
bits : 0 - 31 (32 bit)
access : read-only
Device Type Identifier Register
address_offset : 0xFCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DEVICETYPID : Hardwired to 0x0000_0031.
bits : 0 - 31 (32 bit)
access : read-only
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