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USB0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x15D byte (0x0)
mem_usage : registers
protection : not protected

Registers

PERID

USBCTRL

OBSERVE

CONTROL

USBTRC0

USBFRMADJUST

CLK_RECOVER_CTRL

CLK_RECOVER_IRC_EN

CLK_RECOVER_INT_EN

CLK_RECOVER_INT_STATUS

ENDPT0

OTGCTL

ENDPT1

ENDPT2

ENDPT3

IDCOMP

ENDPT4

ENDPT5

ENDPT6

ENDPT7

REV

ISTAT

ENDPT8

INTEN

ERRSTAT

ERREN

ENDPT9

STAT

CTL

ADDR

BDTPAGE1

ENDPT10

FRMNUML

FRMNUMH

ENDPT11

BDTPAGE2

BDTPAGE3

ENDPT12

ADDINFO

ENDPT13

ENDPT14

ENDPT15


PERID

Peripheral ID register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PERID PERID read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ID

ID : Peripheral Identification
bits : 0 - 5 (6 bit)
access : read-only


USBCTRL

USB Control register
address_offset : 0x100 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBCTRL USBCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PDE SUSP

PDE : Enables the weak pulldowns on the USB transceiver.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Weak pulldowns are disabled on D+ and D-.

#1 : 1

Weak pulldowns are enabled on D+ and D-.

End of enumeration elements list.

SUSP : Places the USB transceiver into the suspend state.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

USB transceiver is not in suspend state.

#1 : 1

USB transceiver is in suspend state.

End of enumeration elements list.


OBSERVE

USB OTG Observe register
address_offset : 0x104 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OBSERVE OBSERVE read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DMPD DPPD DPPU

DMPD : Provides observability of the D- Pulldown signal output from USB.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

D- pulldown disabled.

#1 : 1

D- pulldown enabled.

End of enumeration elements list.

DPPD : Provides observability of the D+ Pulldown signal output from USB.
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

D+ pulldown disabled.

#1 : 1

D+ pulldown enabled.

End of enumeration elements list.

DPPU : Provides observability of the D+ Pullup signal output from USB .
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

D+ pullup disabled.

#1 : 1

D+ pullup enabled.

End of enumeration elements list.


CONTROL

USB OTG Control register
address_offset : 0x108 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONTROL CONTROL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DPPULLUPNONOTG

DPPULLUPNONOTG : Provides control of the DP Pullup in USB, if USB is configured in non-OTG device mode.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

DP Pullup in non-OTG device mode is not enabled.

#1 : 1

DP Pullup in non-OTG device mode is enabled.

End of enumeration elements list.


USBTRC0

USB Transceiver Control register 0
address_offset : 0x10C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBTRC0 USBTRC0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RESUME_INT SYNC_DET USB_CLK_RECOVERY_INT USBRESMEN USBRESET

USB_RESUME_INT : USB Asynchronous Interrupt
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

No interrupt was generated.

#1 : 1

Interrupt was generated because of the USB asynchronous interrupt.

End of enumeration elements list.

SYNC_DET : Synchronous USB Interrupt Detect
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Synchronous interrupt has not been detected.

#1 : 1

Synchronous interrupt has been detected.

End of enumeration elements list.

USB_CLK_RECOVERY_INT : Combined USB Clock Recovery interrupt status
bits : 2 - 2 (1 bit)
access : read-only

USBRESMEN : Asynchronous Resume Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

USB asynchronous wakeup from suspend mode disabled.

#1 : 1

USB asynchronous wakeup from suspend mode enabled. The asynchronous resume interrupt differs from the synchronous resume interrupt in that it asynchronously detects K-state using the unfiltered state of the D+ and D- pins. This interrupt should only be enabled when the Transceiver is suspended.

End of enumeration elements list.

USBRESET : USB Reset
bits : 7 - 7 (1 bit)
access : write-only

Enumeration:

#0 : 0

Normal USB module operation.

#1 : 1

Returns the USB module to its reset state.

End of enumeration elements list.


USBFRMADJUST

Frame Adjust Register
address_offset : 0x114 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBFRMADJUST USBFRMADJUST read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ADJ

ADJ : Frame Adjustment
bits : 0 - 7 (8 bit)
access : read-write


CLK_RECOVER_CTRL

USB Clock recovery control
address_offset : 0x140 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_RECOVER_CTRL CLK_RECOVER_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RESTART_IFRTRIM_EN RESET_RESUME_ROUGH_EN CLOCK_RECOVER_EN

RESTART_IFRTRIM_EN : Restart from IFR trim value
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Trim fine adjustment always works based on the previous updated trim fine value (default)

#1 : 1

Trim fine restarts from the IFR trim value whenever bus_reset/bus_resume is detected or module enable is desasserted

End of enumeration elements list.

RESET_RESUME_ROUGH_EN : Reset/resume to rough phase enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Always works in tracking phase after the first time rough to track transition (default)

#1 : 1

Go back to rough stage whenever bus reset or bus resume occurs

End of enumeration elements list.

CLOCK_RECOVER_EN : Crystal-less USB enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable clock recovery block (default)

#1 : 1

Enable clock recovery block

End of enumeration elements list.


CLK_RECOVER_IRC_EN

IRC48M oscillator enable register
address_offset : 0x144 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_RECOVER_IRC_EN CLK_RECOVER_IRC_EN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IRC_EN

IRC_EN : IRC48M enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the IRC48M module (default)

#1 : 1

Enable the IRC48M module

End of enumeration elements list.


CLK_RECOVER_INT_EN

Clock recovery combined interrupt enable
address_offset : 0x154 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_RECOVER_INT_EN CLK_RECOVER_INT_EN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVF_ERROR_EN

OVF_ERROR_EN : Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The interrupt will be masked

#1 : 1

The interrupt will be enabled (default)

End of enumeration elements list.


CLK_RECOVER_INT_STATUS

Clock recovery separated interrupt status
address_offset : 0x15C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_RECOVER_INT_STATUS CLK_RECOVER_INT_STATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVF_ERROR

OVF_ERROR : Indicates that the USB clock recovery algorithm has detected that the frequency trim adjustment needed for the IRC48M output clock is outside the available TRIM_FINE adjustment range for the IRC48M module
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt is reported

#1 : 1

Unmasked interrupt has been generated

End of enumeration elements list.


ENDPT0

Endpoint Control register
address_offset : 0x180 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPT0 ENDPT0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPHSHK EPSTALL EPTXEN EPRXEN EPCTLDIS

EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write

EPSTALL : When set this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write

EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write

EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write

EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write


OTGCTL

OTG Control register
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OTGCTL OTGCTL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DPHIGH

DPHIGH : D+ Data Line pullup resistor enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

D+ pullup resistor is not enabled

#1 : 1

D+ pullup resistor is enabled

End of enumeration elements list.


ENDPT1

Endpoint Control register
address_offset : 0x244 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPT1 ENDPT1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPHSHK EPSTALL EPTXEN EPRXEN EPCTLDIS

EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write

EPSTALL : When set this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write

EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write

EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write

EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write


ENDPT2

Endpoint Control register
address_offset : 0x30C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPT2 ENDPT2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPHSHK EPSTALL EPTXEN EPRXEN EPCTLDIS

EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write

EPSTALL : When set this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write

EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write

EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write

EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write


ENDPT3

Endpoint Control register
address_offset : 0x3D8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPT3 ENDPT3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPHSHK EPSTALL EPTXEN EPRXEN EPCTLDIS

EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write

EPSTALL : When set this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write

EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write

EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write

EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write


IDCOMP

Peripheral ID Complement register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IDCOMP IDCOMP read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NID

NID : Ones' complement of PERID[ID]. bits.
bits : 0 - 5 (6 bit)
access : read-only


ENDPT4

Endpoint Control register
address_offset : 0x4A8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPT4 ENDPT4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPHSHK EPSTALL EPTXEN EPRXEN EPCTLDIS

EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write

EPSTALL : When set this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write

EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write

EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write

EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write


ENDPT5

Endpoint Control register
address_offset : 0x57C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPT5 ENDPT5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPHSHK EPSTALL EPTXEN EPRXEN EPCTLDIS

EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write

EPSTALL : When set this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write

EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write

EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write

EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write


ENDPT6

Endpoint Control register
address_offset : 0x654 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPT6 ENDPT6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPHSHK EPSTALL EPTXEN EPRXEN EPCTLDIS

EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write

EPSTALL : When set this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write

EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write

EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write

EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write


ENDPT7

Endpoint Control register
address_offset : 0x730 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPT7 ENDPT7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPHSHK EPSTALL EPTXEN EPRXEN EPCTLDIS

EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write

EPSTALL : When set this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write

EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write

EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write

EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write


REV

Peripheral Revision register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REV REV read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 REV

REV : Revision
bits : 0 - 7 (8 bit)
access : read-only


ISTAT

Interrupt Status register
address_offset : 0x80 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISTAT ISTAT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USBRST ERROR SOFTOK TOKDNE SLEEP RESUME STALL

USBRST : This bit is set when the USB Module has decoded a valid USB reset
bits : 0 - 0 (1 bit)
access : read-write

ERROR : This bit is set when any of the error conditions within Error Interrupt Status (ERRSTAT) register occur
bits : 1 - 1 (1 bit)
access : read-write

SOFTOK : This bit is set when the USB Module receives a Start Of Frame (SOF) token.
bits : 2 - 2 (1 bit)
access : read-write

TOKDNE : This bit is set when the current token being processed has completed
bits : 3 - 3 (1 bit)
access : read-write

SLEEP : This bit is set when the USB Module detects a constant idle on the USB bus for 3 ms
bits : 4 - 4 (1 bit)
access : read-write

RESUME : This bit is set when a K-state is observed on the DP/DM signals for 2
bits : 5 - 5 (1 bit)
access : read-write

STALL : Stall Interrupt
bits : 7 - 7 (1 bit)
access : read-write


ENDPT8

Endpoint Control register
address_offset : 0x810 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPT8 ENDPT8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPHSHK EPSTALL EPTXEN EPRXEN EPCTLDIS

EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write

EPSTALL : When set this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write

EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write

EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write

EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write


INTEN

Interrupt Enable register
address_offset : 0x84 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USBRSTEN ERROREN SOFTOKEN TOKDNEEN SLEEPEN RESUMEEN STALLEN

USBRSTEN : USBRST Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disables the USBRST interrupt.

#1 : 1

Enables the USBRST interrupt.

End of enumeration elements list.

ERROREN : ERROR Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disables the ERROR interrupt.

#1 : 1

Enables the ERROR interrupt.

End of enumeration elements list.

SOFTOKEN : SOFTOK Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disbles the SOFTOK interrupt.

#1 : 1

Enables the SOFTOK interrupt.

End of enumeration elements list.

TOKDNEEN : TOKDNE Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disables the TOKDNE interrupt.

#1 : 1

Enables the TOKDNE interrupt.

End of enumeration elements list.

SLEEPEN : SLEEP Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disables the SLEEP interrupt.

#1 : 1

Enables the SLEEP interrupt.

End of enumeration elements list.

RESUMEEN : RESUME Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disables the RESUME interrupt.

#1 : 1

Enables the RESUME interrupt.

End of enumeration elements list.

STALLEN : STALL Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Diasbles the STALL interrupt.

#1 : 1

Enables the STALL interrupt.

End of enumeration elements list.


ERRSTAT

Error Interrupt Status register
address_offset : 0x88 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERRSTAT ERRSTAT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PIDERR CRC5 CRC16 DFN8 BTOERR DMAERR BTSERR

PIDERR : This bit is set when the PID check field fails.
bits : 0 - 0 (1 bit)
access : read-write

CRC5 : This error interrupt has two functions
bits : 1 - 1 (1 bit)
access : read-write

CRC16 : This bit is set when a data packet is rejected due to a CRC16 error.
bits : 2 - 2 (1 bit)
access : read-write

DFN8 : This bit is set if the data field received was not 8 bits in length
bits : 3 - 3 (1 bit)
access : read-write

BTOERR : This bit is set when a bus turnaround timeout error occurs
bits : 4 - 4 (1 bit)
access : read-write

DMAERR : This bit is set if the USB Module has requested a DMA access to read a new BDT but has not been given the bus before it needs to receive or transmit data
bits : 5 - 5 (1 bit)
access : read-write

BTSERR : This bit is set when a bit stuff error is detected
bits : 7 - 7 (1 bit)
access : read-write


ERREN

Error Interrupt Enable register
address_offset : 0x8C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERREN ERREN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PIDERREN CRC5EOFEN CRC16EN DFN8EN BTOERREN DMAERREN BTSERREN

PIDERREN : PIDERR Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disables the PIDERR interrupt.

#1 : 1

Enters the PIDERR interrupt.

End of enumeration elements list.

CRC5EOFEN : CRC5/EOF Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disables the CRC5/EOF interrupt.

#1 : 1

Enables the CRC5/EOF interrupt.

End of enumeration elements list.

CRC16EN : CRC16 Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disables the CRC16 interrupt.

#1 : 1

Enables the CRC16 interrupt.

End of enumeration elements list.

DFN8EN : DFN8 Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disables the DFN8 interrupt.

#1 : 1

Enables the DFN8 interrupt.

End of enumeration elements list.

BTOERREN : BTOERR Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disables the BTOERR interrupt.

#1 : 1

Enables the BTOERR interrupt.

End of enumeration elements list.

DMAERREN : DMAERR Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disables the DMAERR interrupt.

#1 : 1

Enables the DMAERR interrupt.

End of enumeration elements list.

BTSERREN : BTSERR Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disables the BTSERR interrupt.

#1 : 1

Enables the BTSERR interrupt.

End of enumeration elements list.


ENDPT9

Endpoint Control register
address_offset : 0x8F4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPT9 ENDPT9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPHSHK EPSTALL EPTXEN EPRXEN EPCTLDIS

EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write

EPSTALL : When set this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write

EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write

EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write

EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write


STAT

Status register
address_offset : 0x90 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ODD TX ENDP

ODD : This bit is set if the last buffer descriptor updated was in the odd bank of the BDT.
bits : 2 - 2 (1 bit)
access : read-only

TX : Transmit Indicator
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

The most recent transaction was a receive operation.

#1 : 1

The most recent transaction was a transmit operation.

End of enumeration elements list.

ENDP : This four-bit field encodes the endpoint address that received or transmitted the previous token
bits : 4 - 7 (4 bit)
access : read-only


CTL

Control register
address_offset : 0x94 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USBENSOFEN ODDRST RESUME TXSUSPENDTOKENBUSY SE0 JSTATE

USBENSOFEN : USB Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disables the USB Module.

#1 : 1

Enables the USB Module.

End of enumeration elements list.

ODDRST : Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which then specifies the EVEN BDT bank
bits : 1 - 1 (1 bit)
access : read-write

RESUME : When set to 1 this bit enables the USB Module to execute resume signaling
bits : 2 - 2 (1 bit)
access : read-write

TXSUSPENDTOKENBUSY : In Device mode, TXD_SUSPEND is set when the SIE has disabled packet transmission and reception
bits : 5 - 5 (1 bit)
access : read-write

SE0 : Live USB Single Ended Zero signal
bits : 6 - 6 (1 bit)
access : read-write

JSTATE : Live USB differential receiver JSTATE signal
bits : 7 - 7 (1 bit)
access : read-write


ADDR

Address register
address_offset : 0x98 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR ADDR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ADDR

ADDR : USB Address
bits : 0 - 6 (7 bit)
access : read-write


BDTPAGE1

BDT Page register 1
address_offset : 0x9C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDTPAGE1 BDTPAGE1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BDTBA

BDTBA : Provides address bits 15 through 9 of the BDT base address.
bits : 1 - 7 (7 bit)
access : read-write


ENDPT10

Endpoint Control register
address_offset : 0x9DC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPT10 ENDPT10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPHSHK EPSTALL EPTXEN EPRXEN EPCTLDIS

EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write

EPSTALL : When set this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write

EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write

EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write

EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write


FRMNUML

Frame Number register Low
address_offset : 0xA0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRMNUML FRMNUML read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FRM

FRM : This 8-bit field and the 3-bit field in the Frame Number Register High are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory
bits : 0 - 7 (8 bit)
access : read-write


FRMNUMH

Frame Number register High
address_offset : 0xA4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRMNUMH FRMNUMH read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FRM

FRM : This 3-bit field and the 8-bit field in the Frame Number Register Low are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory
bits : 0 - 2 (3 bit)
access : read-write


ENDPT11

Endpoint Control register
address_offset : 0xAC8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPT11 ENDPT11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPHSHK EPSTALL EPTXEN EPRXEN EPCTLDIS

EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write

EPSTALL : When set this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write

EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write

EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write

EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write


BDTPAGE2

BDT Page Register 2
address_offset : 0xB0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDTPAGE2 BDTPAGE2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BDTBA

BDTBA : Provides address bits 23 through 16 of the BDT base address that defines the location of Buffer Descriptor Table resides in system memory
bits : 0 - 7 (8 bit)
access : read-write


BDTPAGE3

BDT Page Register 3
address_offset : 0xB4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDTPAGE3 BDTPAGE3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BDTBA

BDTBA : Provides address bits 31 through 24 of the BDT base address that defines the location of Buffer Descriptor Table resides in system memory
bits : 0 - 7 (8 bit)
access : read-write


ENDPT12

Endpoint Control register
address_offset : 0xBB8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPT12 ENDPT12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPHSHK EPSTALL EPTXEN EPRXEN EPCTLDIS

EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write

EPSTALL : When set this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write

EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write

EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write

EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write


ADDINFO

Peripheral Additional Info register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADDINFO ADDINFO read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 IEHOST

IEHOST : This bit is set if host mode is enabled.
bits : 0 - 0 (1 bit)
access : read-only


ENDPT13

Endpoint Control register
address_offset : 0xCAC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPT13 ENDPT13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPHSHK EPSTALL EPTXEN EPRXEN EPCTLDIS

EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write

EPSTALL : When set this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write

EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write

EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write

EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write


ENDPT14

Endpoint Control register
address_offset : 0xDA4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPT14 ENDPT14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPHSHK EPSTALL EPTXEN EPRXEN EPCTLDIS

EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write

EPSTALL : When set this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write

EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write

EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write

EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write


ENDPT15

Endpoint Control register
address_offset : 0xEA0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENDPT15 ENDPT15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EPHSHK EPSTALL EPTXEN EPRXEN EPCTLDIS

EPHSHK : When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint
bits : 0 - 0 (1 bit)
access : read-write

EPSTALL : When set this bit indicates that the endpoint is stalled
bits : 1 - 1 (1 bit)
access : read-write

EPTXEN : This bit, when set, enables the endpoint for TX transfers. See
bits : 2 - 2 (1 bit)
access : read-write

EPRXEN : This bit, when set, enables the endpoint for RX transfers. See
bits : 3 - 3 (1 bit)
access : read-write

EPCTLDIS : This bit, when set, disables control (SETUP) transfers
bits : 4 - 4 (1 bit)
access : read-write



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