\n
address_offset : 0x0 Bytes (0x0)
size : 0x1070 byte (0x0)
mem_usage : registers
protection : not protected
System Options Register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAMSIZE : Returns the size of the system RAM
bits : 12 - 15 (4 bit)
access : read-only
Enumeration:
#0101 : 0101
16kB System RAM
End of enumeration elements list.
OSC32KSEL : 32K oscillator clock select
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 00
OSC32KCLK
#01 : 01
ERCLK32K
#10 : 10
MCGIRCLK
#11 : 11
LPO
End of enumeration elements list.
System Control Register
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMIDIS : NMI Disable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
NMI enabled
#1 : 1
NMI disabled
End of enumeration elements list.
PLL_VLP_EN : PLL VLP Enable
bits : 1 - 1 (1 bit)
access : read-write
PTC2_HD_EN : PTC2 HighDrive Enable
bits : 2 - 2 (1 bit)
access : read-write
SAR_TRG_CLK_SEL : SAR ADC Trigger Clk Select
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 00
Bus Clock (During Low Power Modes such as stop, the Bus clock is not available for conversion and should not be selected in case a conversion needs to be performed while in stop)
#01 : 01
ADC asynchronous Clock
#10 : 10
ERCLK32K
#11 : 11
OSCCLK
End of enumeration elements list.
CLKOUTSEL : Clock out Select
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
#000 : 000
Disabled
#001 : 001
Gated Core Clk
#010 : 010
Bus/Flash Clk
#011 : 011
LPO clock from PMC
#100 : 100
IRC clock from MCG
#101 : 101
Muxed 32Khz source (please refer SOPT1[19:18] for possible options)
#110 : 110
MHz Oscillator external reference clock
#111 : 111
PLL clock output from MCG
End of enumeration elements list.
System Device Identification Register
address_offset : 0x1024 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PINID : Pincount identification
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
#0011 : 0011
44-pin
#0101 : 0101
64-pin
#1000 : 1000
100-pin
End of enumeration elements list.
DIEID : Die ID
bits : 4 - 7 (4 bit)
access : read-only
Enumeration:
#0000 : 0000
First cut
End of enumeration elements list.
REVID : Revision ID
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
#0001 : 0001
Second Cut
End of enumeration elements list.
SRAMSIZE : SRAM Size
bits : 12 - 15 (4 bit)
access : read-only
Enumeration:
#0101 : 0101
16kB SRAM
End of enumeration elements list.
ATTR : Attribute ID
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
#0000 : 0000
M0+ core
End of enumeration elements list.
SERIESID : Series ID
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
#0011 : 0011
Metering Series
End of enumeration elements list.
SUBFAMID : Sub-Family ID
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
#0010 : 0010
Device derivatives with 2 AFE enabled (AFE Channels 0 and 2 are enabled)
#0011 : 0011
Device derivatives with 3 AFE enabled (AFE Channels 0, 1, and 2 are enabled)
#0100 : 0100
Device derivatives with 4 AFE enabled
End of enumeration elements list.
FAMID : Metering family ID
bits : 28 - 31 (4 bit)
access : read-only
Enumeration:
#0001 : 0001
Device derivatives without LCD
#0011 : 0011
Device derivatives with LCD
End of enumeration elements list.
System Clock Gating Control Register 4
address_offset : 0x1034 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EWM : External Watchdog Monitor Clock gate control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
MCG : MCG clock gate control.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
OSC : Oscillator (Mhz) Clock Gate Control
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
I2C0 : I2C0 Clock Gate Control
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
I2C1 : I2C1 Clock Gate Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
UART0 : UART0 Clock Gate Control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
UART1 : UART1 Clock Gate Control
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
UART2 : UART2 Clock Gate Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
UART3 : UART3 Clock Gate Control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
VREF : VREF Clock Gate Control
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
CMP0 : High Speed Comparator0 Clock Gate Control.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
CMP1 : High Speed Comparator1 Clock Gate Control.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
SPI0 : SPI0 Clock Gate Control
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
SPI1 : SPI1 Clock Gate Control
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Gating Control Register 5
address_offset : 0x1038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLCD : Segmented LCD Clock Gate Control
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTA : PCTLA Clock Gate Control
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTB : PCTLB Clock Gate Control
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTC : PCTLC Clock Gate Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTD : PCTLD Clock Gate Control
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTE : PCTLE Clock Gate Control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTF : PCTLF Clock Gate Control
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTG : PCTLG Clock Gate Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTH : PCTLH Clock Gate Control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PORTI : PCTLI Clock Gate Control
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
IRTC : IRTC Clock Gate Control
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
IRTCREGFILE : IRTC_REG_FILE Clock Gate Control
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
WDOG : Watchdog Clock Gate Control
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
XBAR : Peripheral Crossbar Clock Gate Control
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
TMR0 : Quadtimer0 Clock Gate Control
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
TMR1 : Quadtimer1 Clock Gate Control
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
TMR2 : Quadtimer2 Clock Gate Control
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
TMR3 : Quadtimer3 Clock Gate Control
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Gating Control Register 6
address_offset : 0x103C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTFA : FTFA Clock Gate Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
DMAMUX0 : DMA MUX0 Clock Gate Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
DMAMUX1 : DMA MUX1 Clock Gate Control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
DMAMUX2 : DMA MUX2 Clock Gate Control
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
DMAMUX3 : DMA MUX3 Clock Gate Control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
RNGA : RNGA Clock Gate Control
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
ADC : SAR ADC Clock Gate Control
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PIT0 : PIT0 Clock Gate Control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
PIT1 : PIT1 Clock Gate Control
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
AFE : AFE Clock Gate Control
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
CRC : Programmable CRC Clock Gate Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
LPTMR : LPTMR Clock Gate Control
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
SIM_LP : SIM_LP Clock Gate Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#1 : 1
Clock is enabled
#0 : 0
Clock is disabled
End of enumeration elements list.
SIM_HP : SIM_HP Clock Gate Control
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#1 : 1
Clock is always enabled to SIM
End of enumeration elements list.
System Clock Gating Control Register 7
address_offset : 0x1040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPU : MPU Clock Gate control.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
DMA : DMA Clock Gate control.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock disabled
#1 : 1
Clock enabled
End of enumeration elements list.
System Clock Divider Register 1
address_offset : 0x1044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSCLKMODE : System Clock Mode
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
1:1:1
#1 : 1
2:1:1
End of enumeration elements list.
SYSDIV : System Clock divider
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0000
Divide by 1
#0001 : 0001
Divide by 2
#0010 : 0010
Divide by 3
#0011 : 0011
Divide by 4 and so on..... If FOPT[0] is 0, the divider is set to div-by-8 after system reset is deasserted (after completion of system initialization sequence)
End of enumeration elements list.
Flash Configuration Register 1
address_offset : 0x104C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLASHDIS : Flash Disable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash is enabled
#1 : 1
Flash is disabled
End of enumeration elements list.
FLASHDOZE : Flash Doze
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash remains enabled during Wait mode
#1 : 1
Flash is disabled for the duration of Wait mode
End of enumeration elements list.
PFSIZE : Program flash size
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
#0101 : 0101
64 KB of program flash memory, 2 KB protection region
#0111 : 0111
128 KB of program flash memory, 4 KB protection region
#1111 : 1111
(Default)
End of enumeration elements list.
Flash Configuration Register 2
address_offset : 0x1050 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MAXADDR : Max address block
bits : 24 - 30 (7 bit)
access : read-only
Unique Identification Register 0
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only
Unique Identification Register 1
address_offset : 0x1058 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only
Unique Identification Register 2
address_offset : 0x105C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only
Unique Identification Register 3
address_offset : 0x1060 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UID : Unique Identification
bits : 0 - 31 (32 bit)
access : read-only
Miscellaneous Control Register
address_offset : 0x106C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XBARAFEMODOUTSEL : XBAR AFE Modulator Output Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
Sigma Delta Modulator 0 data output
#01 : 01
Sigma Delta Modulator 1 data output
#10 : 10
Sigma Delta Modulator 2 data output
#11 : 11
Sigma Delta Modulator 3 data output
End of enumeration elements list.
DMADONESEL : DMA Done select
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
DMA0
#01 : 01
DMA1
#10 : 10
DMA2
#11 : 11
DMA3
End of enumeration elements list.
AFECLKSEL : AFE Clock Source Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
MCG PLL Clock selected
#01 : 01
MCG FLL Clock selected
#10 : 10
OSC Clock selected
#11 : 11
Disabled
End of enumeration elements list.
AFECLKPADDIR : AFE Clock Pad Direction
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
AFE CLK PAD is input
#1 : 1
AFE CLK PAD is output
End of enumeration elements list.
UARTMODTYPE : UART Modulation Type
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
TypeA (ORed) Modulation selected for IRDA
#1 : 1
TypeB (ANDed) Modulation selected for IRDA
End of enumeration elements list.
UART0IRSEL : UART0 IRDA Select
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pad RX input (PTD[0] or PTF[3], as selected in Pinmux control) selected for RX input of UART0 and UART0 TX signal is not used for modulation
#1 : 1
UART0 selected for IRDA modulation. UART0 TX modulated by XBAR_OUT[14] and UART0 RX input connected to XBAR_OUT[13]
End of enumeration elements list.
UART1IRSEL : UART1 IRDA Select
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pad RX input (PTD[2] or PTI[0], as selected in Pinmux control) selected for RX input of UART1 and UART1 TX signal is not used for modulation
#1 : 1
UART1 selected for IRDA modulation. UART1 TX modulated by XBAR_OUT[14] and UART1 RX input connected to XBAR_OUT[13]
End of enumeration elements list.
UART2IRSEL : UART2 IRDA Select
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pad RX input PTE[6] selected for RX input of UART2 and UART2 TX signal is not used for modulation
#1 : 1
UART2 selected for IRDA modulation. UART2 TX modulated by XBAR_OUT[14] and UART2 RX input connected to XBAR_OUT[13].
End of enumeration elements list.
UART3IRSEL : UART3 IRDA Select
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pad RX input (PTC[3] or PTD[7], as selected in Pinmux control) selected for RX input of UART3 and UART3 TX signal is not used for modulation
#1 : 1
UART3 selected for IRDA modulation. UART3 TX modulated by XBAR_OUT[14] and UART3 RX input connected to XBAR_OUT[13].
End of enumeration elements list.
XBARPITOUTSEL : XBAR PIT Output select
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 00
PIT0[0] (default)
#01 : 01
PIT0[1]
#10 : 10
PIT1[0]
#11 : 11
PIT1[1]
End of enumeration elements list.
EWMINSEL : External Watchdog Monitor Input Select
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input from PAD (PTE[2] or PTE[4] as selected from Pinmux control )
#1 : 1
Peripheral Crossbar (XBAR) Output[32]
End of enumeration elements list.
TMR0PLLCLKSEL : Timer CH0 PLL clock select
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Selects Bus Clock as source for the Timer CH0
#1 : 1
Selects the PLL_AFE clock as the source for Timer CH0. The PLL_AFE clock source is itself selected using the MISC_CTL[5:4]
End of enumeration elements list.
TMR0SCSSEL : Quadtimer Channel0 Secondary Count Source Select
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pad PTF1 or PTD5, depending upon PCTL configuration.
#1 : 1
Peripheral Crossbar (XBAR) Output[5]
End of enumeration elements list.
TMR1SCSSEL : Quadtimer Channel1 Secondary Count Source Select
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pad PTG0 or PTC6, depending upon PCTL configuration.
#1 : 1
Peripheral Crossbar (XBAR) Output[6]
End of enumeration elements list.
TMR2SCSSEL : Quadtimer Channel2 Secondary Count Source Select
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pad PTF7 or PTF0, depending upon PCTL configuration.
#1 : 1
Peripheral Crossbar (XBAR) Output[7]
End of enumeration elements list.
TMR3SCSSEL : Quadtimer Channel3 Secondary Count Source Select
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pad PTE5 or PTD1, depending upon PCTL configuration.
#1 : 1
Peripheral Crossbar (XBAR) Output[8]
End of enumeration elements list.
TMR0PCSSEL : Quadtimer Channel0 Primary Count Source Select
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 00
Bus Clock
#01 : 01
Peripheral Crossbar Output [9]
#10 : 10
Peripheral Crossbar Output [10]
#11 : 11
Disabled
End of enumeration elements list.
TMR1PCSSEL : Quadtimer Channel1 Primary Count Source Select
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 00
Bus Clock
#01 : 01
Peripheral Crossbar Output [9]
#10 : 10
Peripheral Crossbar Output [10]
#11 : 11
Disabled
End of enumeration elements list.
TMR2PCSSEL : Quadtimer Channel2 Primary Count Source Select
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 00
Bus Clock
#01 : 01
Peripheral Crossbar Output [9]
#10 : 10
Peripheral Crossbar Output [10]
#11 : 11
Disabled
End of enumeration elements list.
TMR3PCSSEL : Quadtimer Channel3 Primary Count Source Select
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 00
Bus Clock
#01 : 01
Peripheral Crossbar Output [9]
#10 : 10
Peripheral Crossbar Output [10]
#11 : 11
Disabled
End of enumeration elements list.
RTCCLKSEL : RTC Clock select
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC OSC_32K clock selected
#1 : 1
32K IRC Clock selected
End of enumeration elements list.
VREFBUFOUTEN : VrefBuffer Output Enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Buffer does not drive PAD
#1 : 1
Buffer drives selected voltage (selected by vref_buffer_sel) on pad
End of enumeration elements list.
VREFBUFINSEL : VrefBuffer Input Select
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal Reference selected as Buffer Input
#1 : 1
External Reference selected as Buffer Input
End of enumeration elements list.
VREFBUFPD : VrefBuffer Power Down
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Buffer Enabled
#1 : 1
Buffer Powered Down
End of enumeration elements list.
SOPT1 Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPTMR1SEL : LP timer Channel1 Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 00
Pad PTE4
#01 : 01
Pad PTF4
#10 : 10
Pad PTG1
End of enumeration elements list.
LPTMR2SEL : LP timer Channel2 Select
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 00
Pad PTD6
#01 : 01
Pad PTF3
#10 : 10
Pad PTG5
End of enumeration elements list.
LPTMR3SEL : LP timer Channel3 Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Pad PTD5
#01 : 01
Pad PTG0
#10 : 10
Pad PTG6
End of enumeration elements list.
CMPOLPTMR0SEL : Comparator output selection for LPTMR channel0
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
CMP[1] output selected as LPTMR input[0]
#1 : 1
CMP[0] output selected as LPTMR input[0]
End of enumeration elements list.
RAMSBDIS : no description available
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Source bias of System SRAM enabled during VLPR and VLPW modes.
#1 : 1
Source bias of System SRAM disabled during VLPR and VLPW modes.
End of enumeration elements list.
RAMBPEN : RAM Bitline Precharge Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bitline precharge of system SRAM disabled during VLPR and VLPW modes.
#1 : 1
Bitline precharge of system SRAM enabled during VLPR and VLPW modes.
End of enumeration elements list.
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