Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xF byte (0x0)
mem_usage : registers
protection : not protected
MCG Control 1 Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IREFSTEN : Internal Reference Stop Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal reference clock is disabled in Stop mode.
#1 : 1
Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
End of enumeration elements list.
IRCLKEN : Internal Reference Clock Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
MCGIRCLK inactive.
#1 : 1
MCGIRCLK active.
End of enumeration elements list.
IREFS : Internal Reference Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
External reference clock is selected.
#1 : 1
The slow internal reference clock is selected.
End of enumeration elements list.
FRDIV : FLL External Reference Divider
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 000
If RANGE = 0 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32.
#001 : 001
If RANGE = 0 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64.
#010 : 010
If RANGE = 0 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128.
#011 : 011
If RANGE = 0 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
#100 : 100
If RANGE = 0 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512.
#101 : 101
If RANGE = 0 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024.
#110 : 110
If RANGE = 0 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 .
#111 : 111
If RANGE = 0 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .
End of enumeration elements list.
CLKS : Clock Source Select
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit).
#01 : 01
Encoding 1 - Internal reference clock is selected.
#10 : 10
Encoding 2 - External reference clock is selected.
#11 : 11
Encoding 3 - Reserved.
End of enumeration elements list.
MCG Control 2 Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRCS : Internal Reference Clock Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slow internal reference clock selected.
#1 : 1
Fast internal reference clock selected.
End of enumeration elements list.
LP : Low Power Select
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FLL or PLL is not disabled in bypass modes.
#1 : 1
FLL or PLL is disabled in bypass modes (lower power)
End of enumeration elements list.
EREFS0 : External Reference Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
External reference clock requested.
#1 : 1
Oscillator requested.
End of enumeration elements list.
HGO0 : High Gain Oscillator Select
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Configure crystal oscillator for low-power operation.
#1 : 1
Configure crystal oscillator for high-gain operation.
End of enumeration elements list.
RANGE0 : Frequency Range Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 00
Encoding 0 - Low frequency range selected for the crystal oscillator .
#01 : 01
Encoding 1 - High frequency range selected for the crystal oscillator .
End of enumeration elements list.
LOCRE0 : Loss of Clock Reset Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request is generated on a loss of OSC0 external reference clock.
#1 : 1
Generate a reset request on a loss of OSC0 external reference clock.
End of enumeration elements list.
MCG Control 3 Register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCTRIM : Slow Internal Reference Clock Trim Setting
bits : 0 - 7 (8 bit)
access : read-write
MCG Control 4 Register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCFTRIM : Slow Internal Reference Clock Fine Trim
bits : 0 - 0 (1 bit)
access : read-write
FCTRIM : Fast Internal Reference Clock Trim Setting
bits : 1 - 4 (4 bit)
access : read-write
DRST_DRS : DCO Range Select
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
#00 : 00
Encoding 0 - Low range (reset default).
#01 : 01
Encoding 1 - Mid range.
#10 : 10
Encoding 2 - Mid-high range.
#11 : 11
Encoding 3 - High range.
End of enumeration elements list.
DMX32 : DCO Maximum Frequency with 32.768 kHz Reference
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DCO has a default range of 25%.
#1 : 1
DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
End of enumeration elements list.
MCG Control 5 Register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLLSTEN0 : PLL Stop Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
MCGPLLCLK is disabled in any of the Stop modes.
#1 : 1
MCGPLLCLK is enabled if system is in Normal Stop mode.
End of enumeration elements list.
PLLCLKEN0 : PLL Clock Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
MCGPLLCLK is inactive.
#1 : 1
MCGPLLCLK is active.
End of enumeration elements list.
MCG Control 6 Register
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHGPMP_BIAS : Directly controls the PLL Charge Pump Current. Appropiate selection of this value is imperative to ensure stable operation of the PLL closed loop system. The default value for this field is set to 5'b01000 out of reset which generates a nominal 750nA charge pump current (lcp).
bits : 0 - 4 (5 bit)
access : read-only
CME0 : Clock Monitor Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
External clock monitor is disabled for OSC0.
#1 : 1
External clock monitor is enabled for OSC0.
End of enumeration elements list.
PLLS : PLL Select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
FLL is selected.
#1 : 1
PLL is selected (PLL reference clock must be in the range of 31.25-39.0625 KHz prior to setting the PLLS bit).
End of enumeration elements list.
LOLIE0 : Loss of Lock Interrrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated on loss of lock.
#1 : 1
Generate an interrupt request on loss of lock.
End of enumeration elements list.
MCG Status Register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRCST : Internal Reference Clock Status
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Source of internal reference clock is the slow clock (32 kHz IRC).
#1 : 1
Source of internal reference clock is the fast clock (4 MHz IRC).
End of enumeration elements list.
OSCINIT0 : OSC Initialization
bits : 1 - 1 (1 bit)
access : read-only
CLKST : Clock Mode Status
bits : 2 - 3 (2 bit)
access : read-only
Enumeration:
#00 : 00
Encoding 0 - Output of the FLL is selected (reset default).
#01 : 01
Encoding 1 - Internal reference clock is selected.
#10 : 10
Encoding 2 - External reference clock is selected.
#11 : 11
Encoding 3 - Output of the PLL is selected.
End of enumeration elements list.
IREFST : Internal Reference Status
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Source of FLL reference clock is the external reference clock.
#1 : 1
Source of FLL reference clock is the internal reference clock.
End of enumeration elements list.
PLLST : PLL Select Status
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Source of PLLS clock is FLL clock.
#1 : 1
Source of PLLS clock is PLL output clock.
End of enumeration elements list.
LOCK0 : Lock Status
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
PLL is currently unlocked.
#1 : 1
PLL is currently locked.
End of enumeration elements list.
LOLS0 : Loss of Lock Status
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL has not lost lock since LOLS 0 was last cleared.
#1 : 1
PLL has lost lock since LOLS 0 was last cleared.
End of enumeration elements list.
MCG Status and Control Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCS0 : OSC0 Loss of Clock Status
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Loss of OSC0 has not occurred.
#1 : 1
Loss of OSC0 has occurred.
End of enumeration elements list.
FCRDIV : Fast Clock Internal Reference Divider
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
#000 : 000
Divide Factor is 1
#001 : 001
Divide Factor is 2.
#010 : 010
Divide Factor is 4.
#011 : 011
Divide Factor is 8.
#100 : 100
Divide Factor is 16
#101 : 101
Divide Factor is 32
#110 : 110
Divide Factor is 64
#111 : 111
Divide Factor is 128.
End of enumeration elements list.
FLTPRSRV : FLL Filter Preserve Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
FLL filter and FLL frequency will reset on changes to currect clock mode.
#1 : 1
Fll filter and FLL frequency retain their previous values during new clock mode change.
End of enumeration elements list.
ATMF : Automatic Trim Machine Fail Flag
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Automatic Trim Machine completed normally.
#1 : 1
Automatic Trim Machine failed.
End of enumeration elements list.
ATMS : Automatic Trim Machine Select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
32 kHz Internal Reference Clock selected.
#1 : 1
4 MHz Internal Reference Clock selected.
End of enumeration elements list.
ATME : Automatic Trim Machine Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto Trim Machine disabled.
#1 : 1
Auto Trim Machine enabled.
End of enumeration elements list.
MCG Auto Trim Compare Value High Register
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATCVH : ATM Compare Value High
bits : 0 - 7 (8 bit)
access : read-write
MCG Auto Trim Compare Value Low Register
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATCVL : ATM Compare Value Low
bits : 0 - 7 (8 bit)
access : read-write
MCG Control 7 Register
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSCSEL : MCG OSC Clock Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Selects Oscillator (OSCCLK).
#1 : 1
Selects 32 kHz RTC Oscillator.
End of enumeration elements list.
PLL32KREFSEL : MCG PLL 32Khz Reference Clock Select
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 00
Selects 32 kHz RTC Oscillator.
#01 : 01
Selects 32 kHz IRC.
#10 : 10
Selects FLL FRDIV clock.
End of enumeration elements list.
MCG Control 8 Register
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCS1 : RTC Loss of Clock Status
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Loss of RTC has not occur.
#1 : 1
Loss of RTC has occur
End of enumeration elements list.
COARSE_LOLIE : Loss of Coarse Lock Interrrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt request is generated on coarse loss of lock.
#1 : 1
Generate an interrupt request on coarse loss of lock.
End of enumeration elements list.
CME1 : Clock Monitor Enable1
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
External clock monitor is disabled for RTC clock.
#1 : 1
External clock monitor is enabled for RTC clock.
End of enumeration elements list.
LOLRE : PLL Loss of Lock Reset Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request.
#1 : 1
Generate a reset request on a PLL loss of lock indication.
End of enumeration elements list.
LOCRE1 : Loss of Clock Reset Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt request is generated on a loss of RTC external reference clock.
#1 : 1
Generate a reset request on a loss of RTC external reference clock
End of enumeration elements list.
MCG Control 9 Register
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COARSE_LOCK : Coarse Lock Status
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
PLL is currently unlocked.
#1 : 1
PLL is currently locked after first sample.
End of enumeration elements list.
COARSE_LOLS : Coarse Loss of Lock Status
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
PLL has not lost lock since COARSE_LOLS was last cleared.
#1 : 1
PLL has lost lock since COARSE_LOLS was last cleared.
End of enumeration elements list.
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