\n

MCM

Peripheral Memory Blocks

address_offset : 0x8 Bytes (0x0)
size : 0x7C byte (0x0)
mem_usage : registers
protection : not protected

Registers

PID

CPO

PLASC

MATCR

PLAMC

PLACR


PID

Process ID register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PID PID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID

PID : M0_PID For MPU
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

#0 : 0

Reserved for privileged secure tasks

End of enumeration elements list.


CPO

Compute Operation Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPO CPO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPOREQ CPOACK CPOWOI

CPOREQ : Compute Operation Request
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Request is cleared.

#1 : 1

Request Compute Operation.

End of enumeration elements list.

CPOACK : Compute Operation Acknowledge
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Compute operation entry has not completed or compute operation exit has completed.

#1 : 1

Compute operation entry has completed or compute operation exit has not completed.

End of enumeration elements list.

CPOWOI : Compute Operation Wake-up on Interrupt
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect.

#1 : 1

When set, the CPOREQ is cleared on any interrupt or exception vector fetch.

End of enumeration elements list.


PLASC

Crossbar Switch (AXBS) Slave Configuration
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PLASC PLASC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASC

ASC : Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.
bits : 0 - 7 (8 bit)
access : read-only

Enumeration:

#0 : 0

A bus slave connection to AXBS input port n is absent.

#1 : 1

A bus slave connection to AXBS input port n is present.

End of enumeration elements list.


MATCR

Master Attribute Configuration Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MATCR MATCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATC0 RO0 ATC2 RO2

ATC0 : Attribute Configuration Master n
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#00x : 00x

Master attributes are statically forced to {privileged, secure}.

#010 : 010

Master attributes are statically forced to {user, secure}.

#011 : 011

Master attributes are statically forced to {user, nonsecure}.

#100 : 100

Enable master attribute {privileged or user} and statically force {secure}.

#101 : 101

Enable master attribute {privileged or user} and statically force {nonsecure}.

#11x : 11x

Enable master attribute {privileged or user, secure or nonsecure}

End of enumeration elements list.

RO0 : Read-Only Master n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writes to the ATCn are allowed.

#1 : 1

Writes to the ATCn are ignored.

End of enumeration elements list.

ATC2 : Attribute Configuration Master n
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#00x : 00x

Master attributes are statically forced to {privileged, secure}.

#010 : 010

Master attributes are statically forced to {user, secure}.

#011 : 011

Master attributes are statically forced to {user, nonsecure}.

#100 : 100

Enable master attribute {privileged or user} and statically force {secure}.

#101 : 101

Enable master attribute {privileged or user} and statically force {nonsecure}.

#11x : 11x

Enable master attribute {privileged or user, secure or nonsecure}

End of enumeration elements list.

RO2 : Read-Only Master n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writes to the ATCn are allowed.

#1 : 1

Writes to the ATCn are ignored.

End of enumeration elements list.


PLAMC

Crossbar Switch (AXBS) Master Configuration
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PLAMC PLAMC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMC

AMC : Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
bits : 0 - 7 (8 bit)
access : read-only

Enumeration:

#0 : 0

A bus master connection to AXBS input port n is absent

#1 : 1

A bus master connection to AXBS input port n is present

End of enumeration elements list.


PLACR

Platform Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLACR PLACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARB CFCC DFCDA DFCIC DFCC EFDS DFCS ESFC

ARB : Arbitration select
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Fixed-priority arbitration for the crossbar masters

#1 : 1

Round-robin arbitration for the crossbar masters

End of enumeration elements list.

CFCC : Clear Flash Controller Cache
bits : 10 - 10 (1 bit)
access : write-only

DFCDA : Disable Flash Controller Data Caching
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Enable flash controller data caching

#1 : 1

Disable flash controller data caching.

End of enumeration elements list.

DFCIC : Disable Flash Controller Instruction Caching
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Enable flash controller instruction caching.

#1 : 1

Disable flash controller instruction caching.

End of enumeration elements list.

DFCC : Disable Flash Controller Cache
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Enable flash controller cache.

#1 : 1

Disable flash controller cache.

End of enumeration elements list.

EFDS : Enable Flash Data Speculation
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable flash data speculation.

#1 : 1

Enable flash data speculation.

End of enumeration elements list.

DFCS : Disable Flash Controller Speculation
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Enable flash controller speculation.

#1 : 1

Disable flash controller speculation.

End of enumeration elements list.

ESFC : Enable Stalling Flash Controller
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable stalling flash controller when flash is busy.

#1 : 1

Enable stalling flash controller when flash is busy.

End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.