\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
MCU Device ID Code Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DEV_ID : Device Identifier
bits : 0 - 15 (16 bit)
REV_ID : Revision Identifier
bits : 16 - 31 (16 bit)
Debug MCU Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_STOP : Debug Stop Mode
bits : 1 - 1 (1 bit)
DBG_STANDBY : Debug Standby Mode
bits : 2 - 2 (1 bit)
DBG APB freeze register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_TIMER2_STOP : Debug Timer 2 stopped when Core is halted
bits : 0 - 0 (1 bit)
DBG_TIM3_STOP : TIM3 counter stopped when core is halted
bits : 1 - 1 (1 bit)
DBG_TIMER6_STOP : Debug Timer 6 stopped when Core is halted
bits : 4 - 4 (1 bit)
DBG_TIM7_STOP : TIM7 counter stopped when core is halted
bits : 5 - 5 (1 bit)
DBG_RTC_STOP : Debug RTC stopped when Core is halted
bits : 10 - 10 (1 bit)
DBG_WWDG_STOP : Debug Window Wachdog stopped when Core is halted
bits : 11 - 11 (1 bit)
DBG_IWDG_STOP : Debug Independent Wachdog stopped when Core is halted
bits : 12 - 12 (1 bit)
DBG_I2C1_STOP : I2C1 SMBUS timeout mode stopped when core is halted
bits : 21 - 21 (1 bit)
DBG_LPTIM2_STOP : Clocking of LPTIMER2 counter when the core is halted
bits : 30 - 30 (1 bit)
DBG_LPTIM1_STOP : Clocking of LPTIMER1 counter when the core is halted
bits : 31 - 31 (1 bit)
DBG APB freeze register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_TIM1_STOP : DBG_TIM1_STOP
bits : 11 - 11 (1 bit)
DBG_TIM14_STOP : DBG_TIM14_STOP
bits : 15 - 15 (1 bit)
DBG_TIM15_STOP : DBG_TIM15_STOP
bits : 16 - 16 (1 bit)
DBG_TIM16_STOP : DBG_TIM16_STOP
bits : 17 - 17 (1 bit)
DBG_TIM17_STOP : DBG_TIM17_STOP
bits : 18 - 18 (1 bit)
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