\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
Channel Configuration register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#10 : 2
UART0_Receive_Complete
#11 : 3
UART0_Transmit_Complete
#100 : 4
UART1_Receive_Complete
#101 : 5
UART1_Transmit_Complete
#1110 : 14
CAN0Rx
#10000 : 16
SPI0_Receive_Complete
#10001 : 17
SPI0_Transmit_Complete
#10110 : 22
I2C0_Transmission_Complete
#11000 : 24
FTM0_CH0_Event
#11001 : 25
FTM0_CH1_Event
#11010 : 26
FTM0_CH2_Event
#11011 : 27
FTM0_CH3_Event
#11100 : 28
FTM0_CH4_Event
#11101 : 29
FTM0_CH5_Event
#11110 : 30
FTM4_CH0_Event
#11111 : 31
FTM4_CH1_Event
#100000 : 32
FTM1_CH0_Event
#100001 : 33
FTM1_CH1_Event
#100010 : 34
FTM2_CH0_Event
#100011 : 35
FTM2_CH1_Event
#100100 : 36
FTM3_CH0_Event
#100101 : 37
FTM3_CH1_Event
#100110 : 38
FTM3_CH2_Event
#100111 : 39
FTM3_CH3_Event
#101000 : 40
ADC0_COCO
#101001 : 41
ADC1_COCO
#101010 : 42
CMP0_Output
#101011 : 43
CMP1_Output
#101101 : 45
DAC0_Buffer_Limit
#101111 : 47
PDB1_Programmable_Interrupt
#110000 : 48
PDB0_Programmable_Interrupt
#110001 : 49
PORTA_Rising_Falling_Edge
#110010 : 50
PORTB_Rising_Falling_Edge
#110011 : 51
PORTC_Rising_Falling_Edge
#110100 : 52
PORTD_Rising_Falling_Edge
#110101 : 53
PORTE_Rising_Falling_Edge
#110110 : 54
FTM3_CH4_Event
#110111 : 55
FTM3_CH5_Event
#111000 : 56
FTM5_CH0_Event
#111001 : 57
FTM5_CH1_Event
#111010 : 58
DMAMUX_Always_Enabled58
#111011 : 59
DMAMUX_Always_Enabled59
#111100 : 60
DMAMUX_Always_Enabled60
#111101 : 61
DMAMUX_Always_Enabled61
#111110 : 62
DMAMUX_Always_Enabled62
#111111 : 63
DMAMUX_Always_Enabled63
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#10 : 2
UART0_Receive_Complete
#11 : 3
UART0_Transmit_Complete
#100 : 4
UART1_Receive_Complete
#101 : 5
UART1_Transmit_Complete
#1110 : 14
CAN0Rx
#10000 : 16
SPI0_Receive_Complete
#10001 : 17
SPI0_Transmit_Complete
#10110 : 22
I2C0_Transmission_Complete
#11000 : 24
FTM0_CH0_Event
#11001 : 25
FTM0_CH1_Event
#11010 : 26
FTM0_CH2_Event
#11011 : 27
FTM0_CH3_Event
#11100 : 28
FTM0_CH4_Event
#11101 : 29
FTM0_CH5_Event
#11110 : 30
FTM4_CH0_Event
#11111 : 31
FTM4_CH1_Event
#100000 : 32
FTM1_CH0_Event
#100001 : 33
FTM1_CH1_Event
#100010 : 34
FTM2_CH0_Event
#100011 : 35
FTM2_CH1_Event
#100100 : 36
FTM3_CH0_Event
#100101 : 37
FTM3_CH1_Event
#100110 : 38
FTM3_CH2_Event
#100111 : 39
FTM3_CH3_Event
#101000 : 40
ADC0_COCO
#101001 : 41
ADC1_COCO
#101010 : 42
CMP0_Output
#101011 : 43
CMP1_Output
#101101 : 45
DAC0_Buffer_Limit
#101111 : 47
PDB1_Programmable_Interrupt
#110000 : 48
PDB0_Programmable_Interrupt
#110001 : 49
PORTA_Rising_Falling_Edge
#110010 : 50
PORTB_Rising_Falling_Edge
#110011 : 51
PORTC_Rising_Falling_Edge
#110100 : 52
PORTD_Rising_Falling_Edge
#110101 : 53
PORTE_Rising_Falling_Edge
#110110 : 54
FTM3_CH4_Event
#110111 : 55
FTM3_CH5_Event
#111000 : 56
FTM5_CH0_Event
#111001 : 57
FTM5_CH1_Event
#111010 : 58
DMAMUX_Always_Enabled58
#111011 : 59
DMAMUX_Always_Enabled59
#111100 : 60
DMAMUX_Always_Enabled60
#111101 : 61
DMAMUX_Always_Enabled61
#111110 : 62
DMAMUX_Always_Enabled62
#111111 : 63
DMAMUX_Always_Enabled63
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration register
address_offset : 0x15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#10 : 2
UART0_Receive_Complete
#11 : 3
UART0_Transmit_Complete
#100 : 4
UART1_Receive_Complete
#101 : 5
UART1_Transmit_Complete
#1110 : 14
CAN0Rx
#10000 : 16
SPI0_Receive_Complete
#10001 : 17
SPI0_Transmit_Complete
#10110 : 22
I2C0_Transmission_Complete
#11000 : 24
FTM0_CH0_Event
#11001 : 25
FTM0_CH1_Event
#11010 : 26
FTM0_CH2_Event
#11011 : 27
FTM0_CH3_Event
#11100 : 28
FTM0_CH4_Event
#11101 : 29
FTM0_CH5_Event
#11110 : 30
FTM4_CH0_Event
#11111 : 31
FTM4_CH1_Event
#100000 : 32
FTM1_CH0_Event
#100001 : 33
FTM1_CH1_Event
#100010 : 34
FTM2_CH0_Event
#100011 : 35
FTM2_CH1_Event
#100100 : 36
FTM3_CH0_Event
#100101 : 37
FTM3_CH1_Event
#100110 : 38
FTM3_CH2_Event
#100111 : 39
FTM3_CH3_Event
#101000 : 40
ADC0_COCO
#101001 : 41
ADC1_COCO
#101010 : 42
CMP0_Output
#101011 : 43
CMP1_Output
#101101 : 45
DAC0_Buffer_Limit
#101111 : 47
PDB1_Programmable_Interrupt
#110000 : 48
PDB0_Programmable_Interrupt
#110001 : 49
PORTA_Rising_Falling_Edge
#110010 : 50
PORTB_Rising_Falling_Edge
#110011 : 51
PORTC_Rising_Falling_Edge
#110100 : 52
PORTD_Rising_Falling_Edge
#110101 : 53
PORTE_Rising_Falling_Edge
#110110 : 54
FTM3_CH4_Event
#110111 : 55
FTM3_CH5_Event
#111000 : 56
FTM5_CH0_Event
#111001 : 57
FTM5_CH1_Event
#111010 : 58
DMAMUX_Always_Enabled58
#111011 : 59
DMAMUX_Always_Enabled59
#111100 : 60
DMAMUX_Always_Enabled60
#111101 : 61
DMAMUX_Always_Enabled61
#111110 : 62
DMAMUX_Always_Enabled62
#111111 : 63
DMAMUX_Always_Enabled63
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration register
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#10 : 2
UART0_Receive_Complete
#11 : 3
UART0_Transmit_Complete
#100 : 4
UART1_Receive_Complete
#101 : 5
UART1_Transmit_Complete
#1110 : 14
CAN0Rx
#10000 : 16
SPI0_Receive_Complete
#10001 : 17
SPI0_Transmit_Complete
#10110 : 22
I2C0_Transmission_Complete
#11000 : 24
FTM0_CH0_Event
#11001 : 25
FTM0_CH1_Event
#11010 : 26
FTM0_CH2_Event
#11011 : 27
FTM0_CH3_Event
#11100 : 28
FTM0_CH4_Event
#11101 : 29
FTM0_CH5_Event
#11110 : 30
FTM4_CH0_Event
#11111 : 31
FTM4_CH1_Event
#100000 : 32
FTM1_CH0_Event
#100001 : 33
FTM1_CH1_Event
#100010 : 34
FTM2_CH0_Event
#100011 : 35
FTM2_CH1_Event
#100100 : 36
FTM3_CH0_Event
#100101 : 37
FTM3_CH1_Event
#100110 : 38
FTM3_CH2_Event
#100111 : 39
FTM3_CH3_Event
#101000 : 40
ADC0_COCO
#101001 : 41
ADC1_COCO
#101010 : 42
CMP0_Output
#101011 : 43
CMP1_Output
#101101 : 45
DAC0_Buffer_Limit
#101111 : 47
PDB1_Programmable_Interrupt
#110000 : 48
PDB0_Programmable_Interrupt
#110001 : 49
PORTA_Rising_Falling_Edge
#110010 : 50
PORTB_Rising_Falling_Edge
#110011 : 51
PORTC_Rising_Falling_Edge
#110100 : 52
PORTD_Rising_Falling_Edge
#110101 : 53
PORTE_Rising_Falling_Edge
#110110 : 54
FTM3_CH4_Event
#110111 : 55
FTM3_CH5_Event
#111000 : 56
FTM5_CH0_Event
#111001 : 57
FTM5_CH1_Event
#111010 : 58
DMAMUX_Always_Enabled58
#111011 : 59
DMAMUX_Always_Enabled59
#111100 : 60
DMAMUX_Always_Enabled60
#111101 : 61
DMAMUX_Always_Enabled61
#111110 : 62
DMAMUX_Always_Enabled62
#111111 : 63
DMAMUX_Always_Enabled63
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#10 : 2
UART0_Receive_Complete
#11 : 3
UART0_Transmit_Complete
#100 : 4
UART1_Receive_Complete
#101 : 5
UART1_Transmit_Complete
#1110 : 14
CAN0Rx
#10000 : 16
SPI0_Receive_Complete
#10001 : 17
SPI0_Transmit_Complete
#10110 : 22
I2C0_Transmission_Complete
#11000 : 24
FTM0_CH0_Event
#11001 : 25
FTM0_CH1_Event
#11010 : 26
FTM0_CH2_Event
#11011 : 27
FTM0_CH3_Event
#11100 : 28
FTM0_CH4_Event
#11101 : 29
FTM0_CH5_Event
#11110 : 30
FTM4_CH0_Event
#11111 : 31
FTM4_CH1_Event
#100000 : 32
FTM1_CH0_Event
#100001 : 33
FTM1_CH1_Event
#100010 : 34
FTM2_CH0_Event
#100011 : 35
FTM2_CH1_Event
#100100 : 36
FTM3_CH0_Event
#100101 : 37
FTM3_CH1_Event
#100110 : 38
FTM3_CH2_Event
#100111 : 39
FTM3_CH3_Event
#101000 : 40
ADC0_COCO
#101001 : 41
ADC1_COCO
#101010 : 42
CMP0_Output
#101011 : 43
CMP1_Output
#101101 : 45
DAC0_Buffer_Limit
#101111 : 47
PDB1_Programmable_Interrupt
#110000 : 48
PDB0_Programmable_Interrupt
#110001 : 49
PORTA_Rising_Falling_Edge
#110010 : 50
PORTB_Rising_Falling_Edge
#110011 : 51
PORTC_Rising_Falling_Edge
#110100 : 52
PORTD_Rising_Falling_Edge
#110101 : 53
PORTE_Rising_Falling_Edge
#110110 : 54
FTM3_CH4_Event
#110111 : 55
FTM3_CH5_Event
#111000 : 56
FTM5_CH0_Event
#111001 : 57
FTM5_CH1_Event
#111010 : 58
DMAMUX_Always_Enabled58
#111011 : 59
DMAMUX_Always_Enabled59
#111100 : 60
DMAMUX_Always_Enabled60
#111101 : 61
DMAMUX_Always_Enabled61
#111110 : 62
DMAMUX_Always_Enabled62
#111111 : 63
DMAMUX_Always_Enabled63
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#10 : 2
UART0_Receive_Complete
#11 : 3
UART0_Transmit_Complete
#100 : 4
UART1_Receive_Complete
#101 : 5
UART1_Transmit_Complete
#1110 : 14
CAN0Rx
#10000 : 16
SPI0_Receive_Complete
#10001 : 17
SPI0_Transmit_Complete
#10110 : 22
I2C0_Transmission_Complete
#11000 : 24
FTM0_CH0_Event
#11001 : 25
FTM0_CH1_Event
#11010 : 26
FTM0_CH2_Event
#11011 : 27
FTM0_CH3_Event
#11100 : 28
FTM0_CH4_Event
#11101 : 29
FTM0_CH5_Event
#11110 : 30
FTM4_CH0_Event
#11111 : 31
FTM4_CH1_Event
#100000 : 32
FTM1_CH0_Event
#100001 : 33
FTM1_CH1_Event
#100010 : 34
FTM2_CH0_Event
#100011 : 35
FTM2_CH1_Event
#100100 : 36
FTM3_CH0_Event
#100101 : 37
FTM3_CH1_Event
#100110 : 38
FTM3_CH2_Event
#100111 : 39
FTM3_CH3_Event
#101000 : 40
ADC0_COCO
#101001 : 41
ADC1_COCO
#101010 : 42
CMP0_Output
#101011 : 43
CMP1_Output
#101101 : 45
DAC0_Buffer_Limit
#101111 : 47
PDB1_Programmable_Interrupt
#110000 : 48
PDB0_Programmable_Interrupt
#110001 : 49
PORTA_Rising_Falling_Edge
#110010 : 50
PORTB_Rising_Falling_Edge
#110011 : 51
PORTC_Rising_Falling_Edge
#110100 : 52
PORTD_Rising_Falling_Edge
#110101 : 53
PORTE_Rising_Falling_Edge
#110110 : 54
FTM3_CH4_Event
#110111 : 55
FTM3_CH5_Event
#111000 : 56
FTM5_CH0_Event
#111001 : 57
FTM5_CH1_Event
#111010 : 58
DMAMUX_Always_Enabled58
#111011 : 59
DMAMUX_Always_Enabled59
#111100 : 60
DMAMUX_Always_Enabled60
#111101 : 61
DMAMUX_Always_Enabled61
#111110 : 62
DMAMUX_Always_Enabled62
#111111 : 63
DMAMUX_Always_Enabled63
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration register
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#10 : 2
UART0_Receive_Complete
#11 : 3
UART0_Transmit_Complete
#100 : 4
UART1_Receive_Complete
#101 : 5
UART1_Transmit_Complete
#1110 : 14
CAN0Rx
#10000 : 16
SPI0_Receive_Complete
#10001 : 17
SPI0_Transmit_Complete
#10110 : 22
I2C0_Transmission_Complete
#11000 : 24
FTM0_CH0_Event
#11001 : 25
FTM0_CH1_Event
#11010 : 26
FTM0_CH2_Event
#11011 : 27
FTM0_CH3_Event
#11100 : 28
FTM0_CH4_Event
#11101 : 29
FTM0_CH5_Event
#11110 : 30
FTM4_CH0_Event
#11111 : 31
FTM4_CH1_Event
#100000 : 32
FTM1_CH0_Event
#100001 : 33
FTM1_CH1_Event
#100010 : 34
FTM2_CH0_Event
#100011 : 35
FTM2_CH1_Event
#100100 : 36
FTM3_CH0_Event
#100101 : 37
FTM3_CH1_Event
#100110 : 38
FTM3_CH2_Event
#100111 : 39
FTM3_CH3_Event
#101000 : 40
ADC0_COCO
#101001 : 41
ADC1_COCO
#101010 : 42
CMP0_Output
#101011 : 43
CMP1_Output
#101101 : 45
DAC0_Buffer_Limit
#101111 : 47
PDB1_Programmable_Interrupt
#110000 : 48
PDB0_Programmable_Interrupt
#110001 : 49
PORTA_Rising_Falling_Edge
#110010 : 50
PORTB_Rising_Falling_Edge
#110011 : 51
PORTC_Rising_Falling_Edge
#110100 : 52
PORTD_Rising_Falling_Edge
#110101 : 53
PORTE_Rising_Falling_Edge
#110110 : 54
FTM3_CH4_Event
#110111 : 55
FTM3_CH5_Event
#111000 : 56
FTM5_CH0_Event
#111001 : 57
FTM5_CH1_Event
#111010 : 58
DMAMUX_Always_Enabled58
#111011 : 59
DMAMUX_Always_Enabled59
#111100 : 60
DMAMUX_Always_Enabled60
#111101 : 61
DMAMUX_Always_Enabled61
#111110 : 62
DMAMUX_Always_Enabled62
#111111 : 63
DMAMUX_Always_Enabled63
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
Channel Configuration register
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOURCE : DMA Channel Source (Slot)
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#10 : 2
UART0_Receive_Complete
#11 : 3
UART0_Transmit_Complete
#100 : 4
UART1_Receive_Complete
#101 : 5
UART1_Transmit_Complete
#1110 : 14
CAN0Rx
#10000 : 16
SPI0_Receive_Complete
#10001 : 17
SPI0_Transmit_Complete
#10110 : 22
I2C0_Transmission_Complete
#11000 : 24
FTM0_CH0_Event
#11001 : 25
FTM0_CH1_Event
#11010 : 26
FTM0_CH2_Event
#11011 : 27
FTM0_CH3_Event
#11100 : 28
FTM0_CH4_Event
#11101 : 29
FTM0_CH5_Event
#11110 : 30
FTM4_CH0_Event
#11111 : 31
FTM4_CH1_Event
#100000 : 32
FTM1_CH0_Event
#100001 : 33
FTM1_CH1_Event
#100010 : 34
FTM2_CH0_Event
#100011 : 35
FTM2_CH1_Event
#100100 : 36
FTM3_CH0_Event
#100101 : 37
FTM3_CH1_Event
#100110 : 38
FTM3_CH2_Event
#100111 : 39
FTM3_CH3_Event
#101000 : 40
ADC0_COCO
#101001 : 41
ADC1_COCO
#101010 : 42
CMP0_Output
#101011 : 43
CMP1_Output
#101101 : 45
DAC0_Buffer_Limit
#101111 : 47
PDB1_Programmable_Interrupt
#110000 : 48
PDB0_Programmable_Interrupt
#110001 : 49
PORTA_Rising_Falling_Edge
#110010 : 50
PORTB_Rising_Falling_Edge
#110011 : 51
PORTC_Rising_Falling_Edge
#110100 : 52
PORTD_Rising_Falling_Edge
#110101 : 53
PORTE_Rising_Falling_Edge
#110110 : 54
FTM3_CH4_Event
#110111 : 55
FTM3_CH5_Event
#111000 : 56
FTM5_CH0_Event
#111001 : 57
FTM5_CH1_Event
#111010 : 58
DMAMUX_Always_Enabled58
#111011 : 59
DMAMUX_Always_Enabled59
#111100 : 60
DMAMUX_Always_Enabled60
#111101 : 61
DMAMUX_Always_Enabled61
#111110 : 62
DMAMUX_Always_Enabled62
#111111 : 63
DMAMUX_Always_Enabled63
End of enumeration elements list.
ENBL : DMA Channel Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#1 : 1
DMA channel is enabled
End of enumeration elements list.
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